Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.

Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f01ebfda)

DDR scripts are updated to fix DQS gating issue commonly for LPDDR2 and
LPDDR3. That DQS sampling may have problem after enabling the
SDE_0/SDE_1 in MDCTL.

Changes:
  -Based on V2.2, move the "Read DQS Gating Disable" to the step after
   "MR setting", to avoid potential DDR initializaiton failures
   (especially in Plugin Mode).

File:
  http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1



Test:
  Passed stress test on 1 LPDDR2 ARM2 board and 1 LPDDR3 ARM2 board.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8e0351e7)

DDR script is updated to v2.2 to fix potential DQS gating issue. That DQS sampling
may have problem after enabling the SDE_0/SDE_1 in MDCTL.

Changes:
    -Based on V2.1.1, move the "Read DQS Gating Disable" to the step after
     "MR setting", to avoid potential DDR initializaiton failures
     (especially in Plugin Mode).

File:
    http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1



Test:
    Passed stress test on two boards.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8adb838b)

For the out of the box experience, the primary display for the
QWKS board is set to HDMI.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

From testing the performance is better when the voltage
for lpddr2 is set to 1.25V instead of 1.2V.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

Support for the i.MX SX SCM QWKS rev3. The new revision
has support for ov5642 camera, bluetooth and wifi support.

Providing configuration files for:
 - Regular 1gb board
 - spinor

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

Some adjustment to the ddr configuration like:

- Precharge all commands per JEDEC
- Fix the space partition values for 2Gb
- Fix other values that reduce yield of scm parts
  per testing perfomed

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

LPDDR2 script IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc

Updated to add precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM initialization

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(Cherry pick from commit 977a0602)

LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc

Updated to add precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM initialization

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(Cherry pick from commit c9483905)

LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc

Updated to add precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM initialization

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(Cherry pick from commit 97e63e7c)

LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc

Updated to add Precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM initialization

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(Cherry pick from commit fac09919)

LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc

Updated to add Precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM
initialization

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(Cherry pick from commit 73ff1754)

LPDDR2 script MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.inc

Updated to add Precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM initialization

Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(Cherry pick from commit 498f4a79)

The definition of the SWBST_MODE_AUTO at the pfuze100_pmic.h file
changed between uboot versions. On the previous version the shift
to the proper bit field was part of the macro. In the uboot v2016
this macro does not include the shift and needs to be performed
explicitly to properly modify the SWBST_MODE bit field.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

Intially this parameter was added to fix a video stuttering but
with L4.1 the video issue is not present so we can safely get rid
of this parameter.

When using both ldb interfaces in separate mode and passing the
dmfc argument as boot parameter to the kernel, a distortion on
both displays is observed when rendering to the secondary display.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

USB_OTG_ID iomux pad was missconfigured and not selecting the
GPIO1 Alternative for QWKS and the ENET_RX_ERR for EVB, as
a consequence when connecting a USB device the PWR_EN was
disabled. So usb function like "usb start" was not working
as it should.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

Use NXP logo.
The vendor and board dir not changed, only replace the contents
of freescale.bmp.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 0b381fdf)

add splash screen feature for epdc.
it's tested on imx6sll arm2 board and evk board.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit c85c6f2a)

Since we have added the "vs18_enable" parameter for fixed 1.8v I/O, remove
the CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT. This configuration can only work
with one MMC device. If more devices are supported, this will set 1.8v to
all controllers, so will cause problem to 3.3v devices.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c1de6a58)

Change to use the new way to set the vs18_enable field to 1 for fixed 1.8v I/O eMMC.
Don't use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT any longer.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c1bf2d97)

Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC.
Also remove the explicit USDCH2 vendorspec register settings in board codes,
since the driver will take charge of it.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 0c56b681)

Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC.
Also remove the explicit USDCH2 vendorspec register settings in board codes,
since the driver will take charge of it.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 03b2d94b)

When using eMMC with 1.8V I/O, we have to set the VSELECT bit at this USDHC controller
setup and init. The CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT has problem that it will
apply to all USDHC controllers and it only set the 1.8V at init phase. So if user does not
select to the eMMC device, the voltage on the I/O pins are not correct.

This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg structure, so each controller
can have different settings. The default value is 0 for 3.3V, which is compatible with current
codes. When setting this value to 1, at USDHC setup and init phase the driver will set the
VSELECT bit.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ebd872f4)

eMMC is connected fixed to 1.8v, so need to set the LVE of pad
sd2_rst. Also need to set the VSELECT to change all the eMMC pad
(cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak
will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and
SD3 voltage switch.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 07abbd4e)

eMMC is connected fixed to 1.8v, so need to set the LVE of pad
sd2_rst. Also need to set the VSELECT to change all the eMMC pad
(cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak
will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and
SD3 voltage switch.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 0df1d653)

The mfgtool environments only can set in BSP u-boot image, not for android
u-boot. Since android u-boot may go into fastboot in board_r phase which is
earlier than mfgtool environment check. The USB status from android fastboot
will cause u-boot to configure mfgtool environment.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 066f001a19bdc51b0fc0d65bcb87081b01f957c2)
(cherry picked from commit 03f99563)

add one more extra NAND partition in u-boot environment setting to
support Android.

Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 38bd0d64)

Update ddr script to 2.1.1

Script:
http://compass.freescale.net/livelink/livelink/235732623/EVK_IMX6SLL_LPDDR3_400MHz_512MB_32bit_V2.1.1.txt?func=doc.Fetch&nodeid=235732623



Version 2.1.1:
  -Update [MMDC_MPRDDLCTL] and [MMDC_MPWRDLCTL] based on calibration results
  -setmem /32 0x021B0848 = 0x3F393B3C   // [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration Register
  -setmem /32 0x021B0850 = 0x262C3826  // [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration Register

Tested on two boards.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit a3e5ebaa)

Add mx6sll evk board support.
USB/LCDIF/I2C/SD/EMMC/WDOG supported.

The ddr script is from mx6sll lpddr3 arm2 board.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 74054cc9)

Change the 'kONFIG' to 'CONFIG', otherwise will get build warning: unexpected data

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 4deeb824)

To SD, there is no erase group, then the value erase_grp_size
will be default 1. When erasing SD blocks, the blocks will be
erased one by one, which is time consuming.

We use AU_SIZE as a group to speed up the erasing.

Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB.
`time mmc erase 0x100000 0x2000`
time: 44.856 seconds (before optimization)
time: 0.335 seconds  (after optimization)

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stephen Warren <swarren@nvidia.com>
(cherry picked from commit e492dbb4)
(cherry picked from commit a9beae5f)

Add function to read SD_STATUS information.
According to the information, get erase_timeout/erase_size/erase_offset.
Add a structure sd_ssr to include the erase related information.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stephen Warren <swarren@nvidia.com>
(cherry picked from commit 3697e599)
(cherry picked from commit be950ab9)

Changes:
Version 2.1
  -Issue a Precharge-All command prior to the MRW Reset command.
      setmem /32 0x021B001C = 0x00008050  // [MMDC_MDSCR]  precharge all to CS0
      setmem /32 0x021B001C = 0x00008058  // [MMDC_MDSCR]  precharge all to CS1

  -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results
      setmem /32 0x021B0848 = 0x3A383C40   // [MMDC_MPRDDLCTL]
      setmem /32 0x021B0850 = 0x242C3020   // [MMDC_MPWRDLCTL]

File:
http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1



Test:
Passed overnight memtester on one i.MX6SLL LPDDR2 ARM2 board.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5ad998cb)

Since the UART1 register base name is changed from UART1_IPS_BASE_ADDR
to UART1_BASE to align with other i.MX6 chips. Should update the board
configuration header file with the new name.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 18019b8f)

Since the LPDDR2/3 does not have reset pin, to keep safe reset, we need
to use WDOG_B to reset PMIC. Add pinmux and relevant settings.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit be0b2d9c)

Changes from v1.2 to v2.2:
Version 2.2
	-Issue a Precharge-All command prior to the MRW Reset command.
	-setmem /32 0x021B001C = 0x00008050  // [MMDC_MDSCR]  precharge all to CS0
	-setmem /32 0x021B001C = 0x00008058  // [MMDC_MDSCR]  precharge all to CS1
Version 2.1
        -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results
        -setmem /32 0x021B0848 = 0x3C3A3C3C   // [MMDC_MPRDDLCTL]
        -setmem /32 0x021B0850 = 0x24293625   // [MMDC_MPWRDLCTL]
Version 1.2.1
        -Fix a typo. setmem /32 0x020E052C = 0x00000030
        -Fix a typo. setmem /32 0x021B0800 = 0xA1390003

File:
http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1



Test:
Overnight memtester passed on two i.MX6SLL LPDDR3 ARM2 boards.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 92946cba)

Since mx6sll has no ethernet controller, we take USB ethernet device as
network device by default.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit f6c75d01)

Add mx6sll lpddr3/lpddr2 arm2 support.
LCDIF/SPI/USB/PMIC supported.

LPDDR3 DDR version: 1.2
LPDDR2 DDR version: initial version.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
(cherry picked from commit 497134af)

Update lcdif regs for i.MX6SLL

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit a0b08491)