MLK-14689 mx7ulp: Workaround APLL PFD2 to 345.6Mhz

The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1.
This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz.
So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem.
The correct fix should let GPU handle the clock rate in kernel.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e931d534)