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Commit 5c0433b3 authored by Ye Li's avatar Ye Li
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MLK-14533 mx7ulp_evk: Change APLL and its PFD0 frequencies


To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since
the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is
201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources
from APLL PFDs are higher than this max rate.

The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must
change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus.

Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12),
with settings:

PFD0 FRAC:  32
APLL MULT:  22
APLL NUM:   2
APLL DENOM: 5

Signed-off-by: default avatarYe Li <ye.li@nxp.com>
Tested-by: default avatarFancy Fang <chen.fang@nxp.com>
(cherry picked from commit 91be2789)
parent 3b1b0f40
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