Jz4740 NAND flash controller can support:
* MLC NAND as well as SLC NAND
* all 8-bit/16-bit NAND flash devices
* HAMMING and RS hardware ECC
* automatic boot up from NAND flash devices

nand_ecclayout is set up for 2GiB NAND chip mounted in Qi LB60.
We'll bring up boot-from-NAND support in nand_spl/ in the future.

Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>

This fixes that u-boot gets stuck when a bitflip was detected
during "ubi part <ubi_device>". If a bitflip was detected UBI tries
to copy the PEB to a different place. This needs that the eba table
are initialized, but this was done after the wear levelling worker
detects the bitflip. So changes the initialisation of these two
tasks in u-boot.

This is a u-boot specific patch and not needed in the linux layer,
because due to commit 1b1f9a9d
UBI: Ensure that "background thread" operations are really executed
we schedule these tasks in place and not as in linux after the inital
task which schedule this new task is finished.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.

Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.

Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Fix:
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:226:19: warning: variable 'mtd_list' set but not used [-Wunused-but-set-variable]
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:225:6: warning: unused variable 'devices_found'
cfi_mtd.c: In function 'cfi_mtd_init':
cfi_mtd.c:226:19: warning: variable 'mtd_list' set but not used [-Wunused-but-set-variable]
[-Wunused-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>

This avoids colision with nand subsystem's functions.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

The eLBC NAND driver currently follows up each program/write operation with a
read-back of the page, in order to [ostensibly] fill in ECC data for the
caller. However, the page address used for this read is always -1, so the read
will never work correctly.  Remove this useless (and potentially problematic)
block of code.

v2: fix broken mailer

Signed-off-by: mhench <mhench@elutions.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
[scottwood@freescale.com: use chip instead of redundant priv_nand]
Signed-off-by: Scott Wood <scottwood@freescale.com>

When writing 0x4000 to the unlockend_blkaddr register, large writes to
a 2k page NAND sometimes fail. The current kernel driver writes 0xFFFF
to this register for V2 of the nand controller.

However on an i.MX31 this also fixes writes larger than 32MB.
The datasheet is very unspecific, but (0x4000=16384)*2000
roughly fits the limits we're encountering with NAND writes.
This problem might be NAND chip specific.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Signed-off-by: Scott Wood <scottwood@freescale.com>

The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay.
The Data Transfer from Cell to Register is >= 35us. Other Vendors
and older chips normally use >= 25us. To have enough margin 40us
is selected.

Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>

vmt.c: In function ‘ubi_free_volume’:
vmt.c:681:6: warning: variable ‘err’ set but not used
[-Wunused-but-set-variable]

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>

nand_bbt.c: In function ‘search_bbt’:
nand_bbt.c:465:6: warning: variable ‘bits’ set but not used
[-Wunused-but-set-variable]

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>

Adds NAND library to SPL.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Add NAND support (including spl) on IFC, such as is found on the p1010.

Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC.  UBI should
work, as it does not use OOB for anything but ECC.

When hardware ECC is not enabled in CSOR, software ECC is now used.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

On some systems, we get a warning when %lu is used with size_t's, so
use the correct format string.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The Winbond W25X40 is now being used in the IP02 (and possibly IP04).
Tested and working on the actual device.

Signed-off-by: Simon Guinot <sguinot@lacie.com>

Signed-off-by: Shaohui Xie <b21989@freescale.com>
Cc: Mike Frysinger <vapier@gentoo.org>

Add support of MX25L4005 and MX25L8005 according to the datasheet
http://www.mct.net/download/macronix/mx25l8005.pdf



This patch has been tested with MX25L4005 and MX25L8005

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Newer SST flashes have dropped the Auto Address Increment (AAI) word
programming (WP) modes in favor of the standard page programming mode
that most flashes now support.  So add a flags field to the different
flashes to support both modes with new and old styles.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Every spi flash uses the same write disable command, so unify this in
the common code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Fixed commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>

These defines are used in only one place, so just inline them.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Now that the common spi_flash structure tracks all the info that these
drivers need, kill off their local state indirection and use just what
the common code provides.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Once we add a new page_size field for write lengths, we can unify the
write methods for most of the spi flash drivers.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Every spi flash uses the same write enable command, so unify this in
the common code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

This patch adds support for 16 bit NAND devices attached to the
NDFC on ppc4xx processors. Two config entries were added:

  CONFIG_SYS_NDFC_16        - Setting this tells the NDFC that a
			      16 bit device is attached.
  CONFIG_SYS_NDFC_EBC0_CFG  - This is for the External Bus
			      Controller configuration register.

Also, a new ndfc_read_byte() function was added which does not
first convert the data to little endian.

The NAND SPL was also modified to do 16bit bad block testing
when a 16 bit chip is being used.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Add a flag to nand_read_skip_bad() such that if true, any trailing
pages in an eraseblock whose contents are entirely 0xff will be
dropped.

The implementation is via a new drop_ffs() function which is
based on the function of the same name from the ubiformat
utility by Artem Bityutskiy.

This is as-per the reccomendations of the UBI FAQ [1]

[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo



Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Artem Bityutskiy <dedekind1@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an
operation which is mutually exclusive with the 'usual' way of writing.

Add a check that client code does not specify WITH_YAFFS_OOB along with any
other flags and add a comment indicating that the WITH_YAFFS_OOB flag should
not be mixed with other flags.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

In a future commit the behaviour of nand_write_skip_bad()
will be further extended.

Convert the only flag currently passed to the nand_write_
skip_bad() function to a bitfield of only one allocated
member. This should avoid an explosion of int's at the
end of the parameter list or the ambiguous calls like

nand_write_skip_bad(info, offset, len, buf, 0, 1, 1);
nand_write_skip_bad(info, offset, len, buf, 0, 1, 0);

Instead there will be:

nand_write_skip_bad(info, offset, len, buf, WITH_YAFFS_OOB |
			WITH_OTHER);

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Replace an incorrect 'read' with 'write' in a comment.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>

For newer STM parts where CFI >= 1.1, there is a byte in the extended
structure that declares the flash layout type (just like the AMD parts),
so key off of that to find out when we need to reverse the geometry.

This can be seen with M29W640 parts where U-Boot does:
Bank # 1: CFI conformant FLASH (16 x 16)  Size: 8 MB in 135 Sectors
  AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED
  Erase timeout: 8192 ms, write timeout: 1 ms
  Buffer write timeout: 1 ms, buffer size: 16 bytes

  Sector Start Addresses:
  20000000   RO   20002000   RO   20004000   RO   20006000   RO   20008000   RO
  2000A000   RO   2000C000   RO   2000E000   RO   20010000   RO   20020000   RO
  ...

But Linux does:
physmap platform flash device: 00800000 at 20000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank.
                 Manufacturer ID 0x000020 Chip ID 0x0022ed
physmap-flash.0: Swapping erase regions for top-boot CFI table.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>

The status polling can take a while, so make sure we kick the
watchdog after each successful poll.

Signed-off-by: Patrick Sestier <psestier@mircom.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Avoid relocation problem by fix global declaration.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Move the header file and definitions of ftsmc020
static memory control unit from a320 SoC folder to
"drivers/mtd" folder.

This change will let other SoC which also use ftsmc020
could share the same header file.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

I ran into a problem where the reset was failing except when I enabled
debugging support.  After talking with Garret Swalling at Spansion I
was told that the GL-N series of devices require a 500ns wait for the
reset to complete.  The below patch adds a 1us delay after all reset
commands.

-Aaron Williams

Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com>
Signed-off-by: Stefan Roese <sr@denx.de>

tested on the a4m072 board with a S29GL512P flash.

flinfo without this patch
Bank # 1: CFI conformant flash (16 x 16)  Size: 32 MB in 256 Sectors
  AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E
  Erase timeout: 16384 ms, write timeout: 2 ms
  Buffer write timeout: 5 ms, buffer size: 32 bytes
[...]

flinfo with this patch
Bank # 1: CFI conformant flash (16 x 16)  Size: 32 MB in 256 Sectors
  AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2301
  Erase timeout: 16384 ms, write timeout: 2 ms
  Buffer write timeout: 5 ms, buffer size: 32 bytes
[...]

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

The M29W800DT parts also report their geometry with the sector layout
reversed.  So add that ID to the flash_fixup_stm function.

Otherwise, we get:
bfin> flinfo

Bank # 1: CFI conformant FLASH (16 x 16)  Size: 1 MB in 19 Sectors
  AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22D7
  Erase timeout: 8192 ms, write timeout: 1 ms

  Sector Start Addresses:
  20000000        20004000        20006000        20008000        20010000
  20020000        20030000        20040000        20050000        20060000
  20070000        20080000        20090000        200A0000        200B0000
  200C0000        200D0000        200E0000        200F0000

Reported-by: Jianxi Fu <fujianxi@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>