Stefan Bigler
authored
The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay. The Data Transfer from Cell to Register is >= 35us. Other Vendors and older chips normally use >= 25us. To have enough margin 40us is selected. Signed-off-by:Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by:
Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Stefan Roese <sr@denx.de> Signed-off-by:
Scott Wood <scottwood@freescale.com>
| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| nand | ||
| onenand | ||
| spi | ||
| ubi | ||
| Makefile | ||
| at45.c | ||
| cfi_flash.c | ||
| cfi_mtd.c | ||
| dataflash.c | ||
| ftsmc020.c | ||
| jedec_flash.c | ||
| mtdconcat.c | ||
| mtdcore.c | ||
| mtdpart.c | ||
| mw_eeprom.c | ||
| spr_smi.c | ||