Now that we've got boards.cfg and most people have converted over,
start warning people who have yet to so we can phase board configs
completely out of the Makefile.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

These commands should work around various "hardware" ECC and BCH methods.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
[scottwood@freescale.com: s/write the page/access the page/]
Signed-off-by: Scott Wood <scottwood@freescale.com>

to add the "NOR Boot Configuration Word" on AM18xx based boards,
define CONFIG_SYS_DV_NOR_BOOT_CFG.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Paulraj Sandeep <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Adds power library to the new spl

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Adds NAND library to SPL.

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

DDR2 has different ODT table and values. Adding table according to Samsung
application note.

Fix additive latency calculation to avoid interger underflow.

Also converted typedef dynamic_odt_t to struct dynamic_odt.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The following boards share a common design but with minor variations
between them:

P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC

The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.

Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Stefan Roese <sr@denx.de>

This is a trivial fix in the documentation, which corrects
board_init_r() source reference.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>

This patch contains the generic changes required after
change to generic API in the previous patch.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Rolf Offermanns <rof@sysgo.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Thomas Elste <info@elste.org>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Alex Züpke <azu@sysgo.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marius Gröger <mag@sysgo.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: George G. Davis <gdavis@mvista.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Curt Brune <curt@cucy.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marius Gröger <mag@sysgo.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Alex Züpke <azu@sysgo.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

Signed-off-by: Wolfgang Denk <wd@denx.de>

c2dd0d45 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.

Also add some documentation for cache usage in ARM.

Signed-off-by: Aneesh V <aneesh@ti.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stelian Pop <stelian.pop@leadtechdesign.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Gary Jennejohn <garyj@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Remove lpd7a400 and lpd7a404 boards.

Signed-off-by: Wolfgang Denk <wd@denx.de>

Remove edb9301, edb9302, edb9302a, edb9307, edb9307a, edb9312,
edb9315 and edb9315a boards.

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andrea Scian <andrea.scian@dave-tech.it>

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Rowel Atienza <rowel@diwalabs.com>