Add iomux settings for i.MX6 SLL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>

For i.MX6, the mux width is 4, not 3. So enlarge the width.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.

Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.

Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
using these pins.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

We should also take MX6D option in consideration when defining
imx_iomux_v3_setup_pad().

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr
  (0x302C0000) each conroller provides control and mux mode pad
  registers but shares iomuxc input select register with iomuxc-lpsr
  IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings
  for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3
  driver for these LPSR pins.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>

PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four
I2C instances available in VF610.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Add GPIO driver support to Freescale VF610

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>

On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.

Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.

The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.

Signed-off-by: Ye.Li <B37916@freescale.com>

Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.

Changed register settings to comply with JEDEC required values.

Changed timing parameters because they included full clock
periods that were doing nothing.

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>

Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.

Signed-off-by: Stefan Agner <stefan@agner.ch>

Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in
IOMUX_PAD structure.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>

Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list
and add macros for declaring the pad_list that take into account the
SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL
iomux).

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL
register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>

The macro allows easy setting in per-pin, as for example:

,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----

The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.

The following quote from the datasheet:

,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----

This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.

Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio
Estevam <fabio.estevam@freescale.com> and Eric Bénard
<eric@eukrea.com> for helping to properly trace this down.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>

This patch adds the IOMUX support for Vybrid VF610 platform.

There is a little difference for IOMUXC module between VF610 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
VF610, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.

Signed-off-by: Alison Wang <b18965@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

PUE requires PKE to mean something, as do pull values with PUE, so do not
compell users to explicitly use PKE and PUE everywhere. This is also what is
done on Linux and what has already been done for i.MX51.

By the way, remove some unused pad control definitions.

There is no change of behavior.

Note that SPI_PAD_CTRL was defined by several boards with a pull value, but
without PKE or PUE, which means that no pull was actually enabled in the pad.
This might be a bug in those boards, but this patch does not change the
behavior, so it just removes the meaningless pull value from those definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

This macro will be useful for future changes.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

Keep pad control definitions together, and organize definitions in a more
legible way.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

Commit dc88403e "iomux-v3: Place pad control definitions into common file" broke
mx51_efikamx because it made i.MX6's pad control definitions conflict with
i.MX51's.

i.MX51's pad control definitions are actually common to some other i.MX
(25/35/53), so move them to the common iomux-v3.h (just like what is done in
Linux's), and select the correct definitions depending on whether CONFIG_MX6 is
defined or not.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

Instead of having the same PAD control definition in each MX6 variant pin file,
place it into a common location.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

They never return anything also than 0, so lets change the function
to void instead.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>

Move mx6 specific defines to arch-mx6 directory.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>