ENGR00235821 mx6: correct work flow of PFDs

PFDs need to be gate/ungate after PLL lock to reset
PFDs to right state. Otherwise PFDs may lose correct
state in state-machine, then no output clock.
For i.MX6DL and i.MX6SL, ROM have taken care of PFD396
already since the bus clock needs it.

Signed-off-by: Anson Huang <b20788@freescale.com>