- Rework tlb and law tables.
- PCI2 is not available on MPC8548CDS, so remove it.
- Move the memory map to the board config file.
- Rewrite the board info according to the manual.
- Remove unnecessary macros and redefine some macros to align with other boards.
- Fix some typos.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device
from Qi hardware:

http://en.qi-hardware.com/wiki/Ben_NanoNote
http://en.qi-hardware.com/wiki/Main_Page
http://en.wikipedia.org/wiki/Qi_hardware



This Jz4740-based clamshell device does not use NOR flash to boot.
The initial bring-up assumes that U-Boot is directly loaded into SDRAM
using USB boot tool, and starts from 0x80100000.

About USB boot tool
-------------------

Jz4740 is one of the XBurst processors with USB boot functionality
supported.  The CPU can boot from a small ROM in the LSI, initialize
CPU and USB module, then wait for USB commands from the USB host.
We can send 8 KB binary data to the CPU cache using USB boot tool.

USB boot tool is available to the public at Ingenic website.  Also
there is an alternative Debian package named xburst-tools.

Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>

MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum, so that the SDHC write
protected pin polarity does not follow the SD card standard in MPC8536
Rev 1.0 silicon.

The MPC8536DS board invert the SDHC_WP pin as a workaround.  However, this
silicon erratum has been fixed in Rev 1.1, So need invert the SDHC_WP
polarity again when use the MPC8536 Rev1.1 and greater on MPC8536DS board.

Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
   so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
   to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.

Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.

Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.

Removed ODT overriding for P2020DS as it is not necessary.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This is long over due.  All but two net drivers have been converted, but
those have now been dropped.

The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined.  So here we scrub the
core code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The current km_arm boards have a Power-On test jumper. When this
jumper is set, this triggers some Power-On tests on the board.

This patch enables the support of this jumper for starting the
memory_regions test when the jumper is set.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>

Commit "PPC: Cleanup tqm8xx_pcmcia.c" will clean up the PCMCIA code
to use I/O accessors instead of plain volatile pointer accesses.
This will result in about 300 byte bigger code.  Fix custom linker
script to make room for this.

While we are at it, drop unmaintained u-boot.lds.debug linker script.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Wolfgang Denk <wd@denx.de>

nand.c:36: error: static declaration of 'nand_read_buf' follows non-static declaration
/home/marex/u-boot/include/nand.h:139: error: previous declaration of 'nand_read_buf' was here

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz.

Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Align the output for PCI. Replace "PCI" with "PCI1".

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>

CPLD 2.2 removed board watch dog support due to the limitation of CPLD
capacity after adding all the requested features, such as switch overriding.
There is no pin-compatible upgrade part available for current PCB design.
So remove codes related to it.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833,
1000, 1066 and 1333 were verified on this board with SO-DIMM
(UG51U6400N8SU-ACF).

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.

SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

CPLD 2.0 provides a new register which bit[0] is set to '1' will reset
board with initializing the CPLD registers to default values. And add
bit[6] of register at offset 0x5 to use to enable flash bank selection.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The EST SBC8260 is over 10 years old, and the SBC8240 older than
that.  With the tiny amount of RAM (by today's standards), there
really isn't anyone interested in running the latest U-boot on
these EOL products anymore.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: jon.diekema@smiths-aerospace.com

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

Let common code set the machine ID.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Let common code set the machine ID.

Cc: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Cc: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <jason.hui@linaro.org>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Add the initial support for MX25PDK booting from SD card via internal boot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Avoid the usage of extern in C file as pointed out by checkpatch.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Add NAND SPL support to the devkit8000 config

Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Without this change CS's configured for synchronous clocking cannot
read data.

Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

The existing timing does not quite meet the minimum requirements
in the LAN9221 datasheet. The timing in this patch solves problems
noticed on some parts. The patch also combines the CS configuration
for the overo and igep0020 boards per request.

Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>