The default DDR freq is 400MHz or 800M data rate,
the old settings is pure wrong for the default case.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Moved up the initialization of GD so C code like set_tlb() can use
gd->flags to determine if we've relocated or not in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

If the virtual address for CCSRBAR is the same after relocation but
the physical address is changing we'd end up having two TLB entries with
the same VA.  Instead we new us the new CCSRBAR virt address + 4k as a
temp virt address to access the old CCSRBAR to relocate it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

The BR_PHYS_ADDR macro is useful on all machines that have local bus
which is pretty much all 83xx/85xx/86xx chips.

Additionally most 85xx & 86xx will need it if they want to support
36-bit physical addresses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

Add define used to determine if PCI1 interface is in PCI or PCIX mode.

Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

The current code will cause the creation of a 4GB window
starting at 0 if we have more than 4GB of RAM installed,
which overlaps with PCI_MEM space and causes pci_bus_to_phys()
to return erroneous information. Limit the size to 4GB - 1;
which causes the code to create one 2GB and one 1GB window
instead.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>

since commit be0bd823
tlb entry for socrates DDR SDRAM will be reconfigured
by setup_ddr_tlbs() from initdram() causing an
inconsistency with previously configured DDR SDRAM tlb
entry from tlb_table:

socrates>l2cam 7 9
IDX  PID      EPN  SIZE V TS           RPN U0-U3 WIMGE UUUSSS
  7 : 00 00000000 256MB V  0 -> 0_00000000  0000 -I-G- ---RWX
  8 : 00 00000000 256MB V  0 -> 0_00000000  0000 ----- ---RWX
  9 : 00 10000000 256MB V  0 -> 0_10000000  0000 ----- ---RWX

This patch makes the presence of the DDR SDRAM tlb entry in
the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
inconsistency.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>

All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>

we need TLB entry for DDR at !SPD case.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

This caused the operation to be needlessly repeated if there were
no bad blocks and no errors.

Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

This BSP should be outside u-boot source tree.
The second reason is that xilinx ppc405 was moved to generic platform.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

This patch disables some unused features from the PCI405 configuration
to keep U-Boot image size below 192k.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if
CONFIG_AT91RM9200 is defined and nor preloader is used.

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>

With this patch UBI can be used on CFI flash chips.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Remove a printf() from add_mtd_device(), which produces spurious output.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Add cfi-mtd driver, which exports CFI flash to MTD layer.
This allows CFI flash devices to be used from MTD layer.

Building of the new driver is controlled by CONFIG_FLASH_CFI_MTD
option. Initialization is done by calling cfi_mtd_init() from
flash_init().

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Add interface for flash verbosity control. It allows
to disable output from low-level flash API. It is useful
when calling these low-level functions from context other
than flash commands (for example the MTD/CFI interface
implmentation).

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Export flash_sector_size() function from drivers/mtd/cfi_flash.c,
so that it can be used in the upcoming cfi-mtd driver.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>

This patch defines all flash access functions as weak so that
they can be overridden by board specific versions.

This will be used by the upcoming VCTH board support where the NOR
FLASH unfortunately can't be accessed memory-mapped. Special
accessor functions are needed here.

To enable this weak functions you need to define
CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS in your board config header.
Otherwise the "old" default functions will be used resulting
in smaller code.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>

Currently the size parameters of the UBI commands (e.g. "ubi write") are
decoded as decimal instead of hex as default. This patch now interprets
all these values consistantly as hex, as all other standard U-Boot commands
do.

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

 This patch enables support for EXT2, and increases the
CONFIG_SYS_BOOTMAPSZ size for the default configuration
of the katmai boards to use them as the RAID-reference
AMCC setups.

 EXT2 enabling allows one to boot kernels from the EXT2
formatted Compact Flash cards.

 CONFIG_SYS_BOOTMAPSZ increasing allows one to boot the
Linux kernels, which use PAGE_SIZE of 256KB. Otherwise,
the memory area with DTB file (which is placed at the
end of the bootmap area) will turn out to be overlapped
with the BSS segment of the 256KB kernel, and zeroed
in early_init() of Linux.

 Actually, increasing of the bootmap size could be done
via setting of the bootm_size U-Boot variable, but it looks
like the current U-Boot implementation have some bootm_size-
related functionality lost. In many places through the U-Boot
code the CONFIG_SYS_BOOTMAPSZ definition is used directly
(instead of trying to read the corresponding value from the
environment). The same is truth for the boot_jump_linux()
function in lib_ppc/bootm.c, where U-Boot transfers control
to Linux passing the CONFIG_SYS_BOOTMAPSZ (not bootm_size)
value to the booting kernel.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM & ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

The definitions of bits in SDR_CFG are incorrect, and not used within
U-Boot.  Therefore, they can be removed.

The naming of the sdr_ddrdl/sdr_cfg registers do not follow conventions,
and are unused, so they can be removed too.

A definition for SDR0_DDRCFG is added.

Signed-off-by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Convert IO macros to readx/writex.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

This patch corrects a small bug in the "if" condition:
the parameter "flag" is 0 and the "if" condition is always true.
The result is - the boom command doesn't start the kernel.
Affected targets: all arm based.

Signed-off-by: Ilko Iliev <iliev@ronetix.at>

At least some (old ?) versions of the AT91Bootstrap do not set up the
PLLB correctly to 48 MHz in order to make USB host function correctly.

This patch sets up the PLLB to the same values Linux uses, and makes USB
work ok on the following CPUs:
	- AT91CAP9
	- AT91SAM9260
	- AT91SAM9263

This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all
the relevant AT91CAP9/AT91SAM9 atmel boards.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Introduce AT91_CPU_CLOCK and use it for displaying the CPU
speed in the LCD driver.

Also make AT91_MAIN_CLOCK and AT91_MASTER_CLOCK reflect the
corresponding board clocks.

Signed-off-by: Stelian Pop <stelian@popies.net>