- Aug 01, 2011
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Wolfgang Denk authored
Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by:
Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by:
Andre <Schwarz<andre.schwarz@matrix-vision.de>
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- Oct 03, 2009
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Peter Tyser authored
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by:
Peter Tyser <ptyser@xes-inc.com>
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- Dec 05, 2008
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- Oct 18, 2008
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- Aug 12, 2008
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- May 20, 2008
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Wolfgang Denk authored
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by:
Wolfgang Denk <wd@denx.de>
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- Jan 09, 2008
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Matthias Fuchs authored
This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by:
Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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- Sep 24, 2005
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Wolfgang Denk authored
add MII routines to the au1x00 ethernet driver; add USB ohci driver (work in progress) Patch by Thomas Sailer, 20 Jan 2005
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Wolfgang Denk authored
The virtex2 FPGA download code watches for init going active during a download of config data as an error condition. init also goes active after a configuration is finished in concert with the done signal. So far, the code does not check for done active until all of the configuration data is sent. If configuration data has a few extra pad bytes at the end, this would cause an error message even though the download had suceeded. NOTE: virtex2 slave serial and spartan2 versions may still have the same problem. Patch by Andrew Dyer, 12 Jan 2005
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- Feb 27, 2004
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Wolfgang Denk authored
- Timeouts in FPGA code should be based on CFG_HZ - Minor cleanup in code for Altera FPGA ACEX1K * Patch by Steven Scholz, 25 Feb 2004: Changed "Directory Hierarchy" section in README * Patch by Masami Komiya, 25 Feb 2004: Reduce copy count in nfs_read_reply() of NFS code
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- Aug 21, 2002
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Wolfgang Denk authored
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