This is needed so that we could use this macro for non-UBI code.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

Now that the PCI, SATA et al compile problems have been resolved, the
cludge that was applied to avoid them can be removed

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

Primary intent is to resolve build errors for this board which has been
neglected for a very long time. I do not have one of these boards, so I
cannot test functionality

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD
on 18th May 2008 as part of a general i386 / sc520 fixup which was never
applied

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in
commit ff4e66e9, regressed by commit 6d7f610b)

Cast PCI_ROM_ADDRESS_MASK to u32

Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO

Change call to pci_find_class() to pci_find_devices(). This is based on a
patch submitted on 1st March 2007 (Patch that fixes the compilation errors
for sc520_cdp board) by mushtaq_k

This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be
specified in the board config file.  Dummy values have been added for the
SC520 CDP board to enable compilation, but since I do not have one of these,
I do know what the values should be

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

The current configuration of the Environment has the redundant copy of the
environment in the Boot Flash - This was never the intent. The Environment
should instead be in the first two sectors of the first Strata Flash

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Since the NAND code now uses 64bit code, make sure we enable support for
ADI Blackfin boards in printf to avoid the warning:
nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

If the memory layout pushes the stack out of the default DCPLB coverage,
the exception handler may trigger a double fault by trying to push onto
the uncovered stack.  So handle the exception stack similar to the kernel
by using the top of the scratch pad SRAM.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The default console size indirectly applies to length of env vars, so a
smaller length makes it hard to pass longer command lines to kernels.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

The CM-BF537U is similar to the CM-BF537E module, but enough to need its
own board port.

Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Since the Blackfin ABI favors higher scratch registers by default, use the
last scratch register (P3) for global data rather than the first (P5).
This allows the compiler's register allocator to use higher number scratch
P registers, which in turn better matches the Blackfin instruction set,
which reduces the size of U-Boot by more than 1024 bytes...

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Add dns and ntp to default networking commands, and ask for more dhcp
options to better configure the network environment.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

DM646x is an SOC from TI which has both an ARM and a DSP.
There are multiple variants of the SOC mainly dealing with different
core speeds.
This patch adds the initial framework for the DM646x SOC.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

The Default mode that is built for the Davinci DVEVM happens
to be the NOR mode.
When we want to build for the NAND mode, we get a compilation
error. This is overcome by defining the CONFIG_MTD_DEVICE
flag in the NAND mode.
The image built for NAND mode was successfully tested on the
DaVinci DM6446 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp	r0, #0
   beq	earlier_than_label

Which was lost information to

   cmp	r0, #CPU_3XX_ES20
   blt	earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>

This patch removes the asm/sizes.h header file from being
included in the DaVinci SOC configs.
References to SZ_xx have been replaced by appropriate
bit shifted values.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Wolfgang Denk <wd@denx.de>

This patch adds support for the DM365 EVM.
It has been tested on a DM365 EVM.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

This patch adds support for the DevKit8000 board.

Signed-off-by: Frederik Kriewitz <frederik@kriewitz.eu>

The Calao TNY-A9260 and TNY-9G20 are boards manufactured and sold by
Calao Systems <http://www.calao-systems.com

>. Their components are very
similar to the AT91SAM9260EK board, so their configuration is based on
the configuration of this board. There are however some differences:
different clocks, no LCD, no ethernet. They also can use SPI EEPROM to
store the environment.

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

This feature can be used to trigger special command "sysrstcmd" using
reset key long press event and environment variable "sysrstdelay" is set
(useful for reset to factory or manufacturing mode execution)

Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
The counter value is stored in the SYSRSTn Length Counter Register
The counter is based on the 25-MHz reference clock (40ns)
It is a 29-bit counter, yielding a maximum counting duration of
2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
it remains at this value until counter reset is triggered by setting
bit 31 of KW_REG_SYSRST_CNT

Implementation:
Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be
executed if pre-defined in environment variables.
This feature will be disabled if "sysrstdelay" variable is unset.

for-ex.
setenv sysrst_cmd "echo starting factory reset;
		   nand erase 0xa0000 0x20000;
		   echo finish ed sysrst command;"
will erase particular nand sector if triggered by this event

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

The Calao SBC35-A9G20 board is manufactured and sold by Calao Systems
<http://www.calao-systems.com>. It is built around an AT91SAM9G20 ARM SoC
running at 400MHz. It features an Ethernet port, an SPI RTC backed by an onboard
battery , an SD/MMC slot, a CompactFlash slot, 64Mo of SDRAM, 256Mo of NAND
flash, two USB host ports, and an USB device port. More informations can be
found at <http://www.calao-systems.com/articles.php?lng=en&pg=5936

>

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>

This patch adds support for i.MX27-LITEKIT development board from
LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
flash, FEC ethernet controller integrated into i.MX27.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Wolfgang Denk <wd@denx.de>

Remove duplicate set_cr

set_cr is defined in both asm-arm/proc-armv/system.h and
include/asm-arm/system.h. This patch removes it (and some duplicate
defines) from the former.

Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>

Call fsl_pci_init_port() to initialize all the PCIe ports on the board.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

fsl_pci_init_port can be called from board specific PCI initialization
routines to setup the PCI (or PCIe) controller.  This will reduce code
redundancy in most of the 85xx/86xx FSL board ports that setup PCI.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END
memory test hangs if run without arguments. Set them to sane values, so
that all available 512MB of RAM excluding exception vectors at the bottom
and u-boot code and stack at the top can be tested.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

To match all other 85xx platforms we are removing BEDBUG support.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The code base adds P1 & P2 RDB platforms support.
The folder and file names can cater to future SOCs of P1/P2 family.
P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series.

Tested following on P2020RDB:
1. eTSECs
2. DDR, NAND, NOR, I2C.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>