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- Sep 30, 2011
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York Sun authored
DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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York Sun authored
Reduce the calculation error to 1ps. Signed-off-by:
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York Sun authored
The two slots on the same controller have different addresses. Signed-off-by:
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York Sun authored
Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by:
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Kumar Gala authored
The P2041RDB has almost identical setup for TLB, LAWS, and PCI with other P-Series CoreNet platforms. The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the TLB and LAW setup tables. Signed-off-by: -
Kumar Gala authored
We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and P5020DS. There is a significant amount of commonality shared between these boards that we can refactor into common code: * Initial LAW setup * Initial TLB setup * PCI setup We start by moving the shared code between P3041DS, P4080DS, and P5020DS into a common directory to be shared with other P-Series CoreNet boards. Signed-off-by: -
Kumar Gala authored
Useful for various debug to know how various regsters might be set in a human readable form. Signed-off-by: -
Kumar Gala authored
We shouldn't be setting execute permissions on TLB entries that will not actually have any code run from them. Signed-off-by: -
Ramneek Mehresh authored
USB protocol macros (CONFIG_USB_EHCI ...) to be included only when CONFIG_HAS_FSL_DR_USB is defined for a board. Presence of USB DR controller should be declared along with the underlying protocol used in the controller Signed-off-by:
Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by:
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York Sun authored
RDIMM has different timing parameters from UDIMM. Create new tables for RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for future use. Signed-off-by:
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York Sun authored
DDR RCW varies at different speeds. It is common for all platform. Move it out from corenet_ds. Signed-off-by:
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York Sun authored
Extend CAS write Latency (CWL) table to comply with DDR3 spec Signed-off-by:
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Kumar Gala authored
The MPC8536 seems to use only 3 bits for the major revision field in the SVR rather than the 4 bits used by all other processors. The most significant bit is used as a mfg code on MPC8536. Signed-off-by: -
Kumar Gala authored
Move extern of pci_of_setup() into corenet_ds.h Signed-off-by: -
Mingkai Hu authored
Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board. The five dTSEC can be routed to two on-board RGMII phy, three on-board SGMII phy or four SGMII phy on SGMII riser card according to different serdes protocol configuration and board lane configuration. Also updated the device tree to direct the Fmac MAC to the correct PHY. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
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Roy Zang authored
The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
Lei Xu <B33228@freescale.com> Signed-off-by:
Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by:
Shaohui Xie <b21989@freescale.com> Signed-off-by:
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Timur Tabi authored
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS & P5020DS ("Hydra"). The lane_to_slot[] array is initialized dynamically, since board switches can be used to control the muxing of SERDES lanes to slots. The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate slot. The SERDES configuration is queried to help determine the routing between MACs and slot/phy combination. If a XAUI card is inserted, muxing for that card is enabled and never turned off. The PHY address for the 10G XAUI card depends on the slot in which it's inserted. If it's in slot 1, the address is 4. If it's in slot 2, the address is 0. Update the MDIO routing in the P3041DS and P5020DS device trees based on the board-level muxing. The SERDES configuration determines which SGMII/XGMII boards are located in which slots, and so the MDIO bus needs to be muxed correctly whenever talking to a PHY connected to any Fman MAC. The Fman Ethernet nodes in the device tree also need to be routed to the correct PHYs. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by:Timur Tabi <timur@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com> Signed-off-by:
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Andy Fleming authored
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS. The board supports add-on cards for SGMII and XAUI functionality. Which slots on the board these cards are in is a function of the SERDES option selected and muxes on the board. Additionally because of the high-configurablity which MDIO bus one is connected to is "selected" via an FPGA register. We create dummy MDIO bus for the phy layer and hide the mux manipulation in this dummy layer. Add fman fdt helper function in board common code it'll be used by several freescale boards that do various muxing of the MDIO signals based on which controller/interface one is trying to talk to. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by:
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Kumar Gala authored
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Dai Haruki <dai.haruki@freescale.com> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Zhao Chenhui authored
Remove unnecessary or dead code/includes. Signed-off-by:
Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by:
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Timur Tabi authored
Some SOCs have discontiguously-numbered cores, and so we can't determine the valid core numbers via the FRR register any more. We define CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions to process the mask and enumerate over the set of valid cores. Signed-off-by:
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Kumar Gala authored
We shouldn't be setting execute permissions on TLB entries that will not actually have any code run from them. Signed-off-by: -
Kumar Gala authored
Add a helper function that will return a phandle value for the given node. If the node doesn't have a phandle already one will be created. Signed-off-by:
Gerald Van Baren <vanbaren@cideas.com>
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Kumar Gala authored
The old fdt_create_phandle didn't actually create a phandle it just set one. We'll introduce a new helper that actually does creation. Signed-off-by:
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Kumar Gala authored
Add ifdef protection around fman specific code related to device tree clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't be executing this code. Signed-off-by: -
Poonam Aggrwal authored
Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
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Poonam Aggrwal authored
Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by:
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Poonam Aggrwal authored
Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by:
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Poonam Aggrwal authored
For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by:
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Dipen Dudhat authored
And various defines to enable NAND support and NAND spl code for the P1010RDB platform. Signed-off-by:
Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by:
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Dipen Dudhat authored
Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by:
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Poonam Aggrwal authored
Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by:
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Li Yang authored
The following boards share a common design but with minor variations between them: P1020MSBG-PC P1020RDB-PC P1020UTM-PC P1021RDB-PC P1024RDB P1025RDB P2020RDB-PC The P1020RDB-PC shares its roots in the existing P1020RDB board design, however uses DDR3 instead of DDR2. P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK. Key features on these boards include: * DDR3 * NOR flash * NAND flash (on RDB's only) * SPI flash (on RDB's only) * SDHC/MMC card slot * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) * PCIE slot and mini-PCIE slots As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM is used to store SPD data. In case of absent or corrupted SPD, falling back to timing data embedded in the source code will be used. Raw timing data is extracted from DDR chip datasheet. Different speeds of DDR are supported with this approach. ODT option is forced to fit this set of boards, again because they don't have regular DIMMs. CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification for writing timing. VSC firmware Address is defined by default in config file for eTSEC1. SD width is based off DIP switch. DIP switch is detected on the board by reading i2c bus and setting the appropriate mux values. Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have pins multiplexing. QE function needs to be disabled to access Nor Flash and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Zhao Chenhui <b26998@freescale.com> Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by:
Tang Yuantian <b29983@freescale.com> Signed-off-by:
Xie Xiaobo <X.Xie@freescale.com> Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by:
Akhil Goyal <akhil.goyal@freescale.com>
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Timur Tabi authored
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by:
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Timur Tabi authored
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by:
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Kumar Gala authored
Signed-off-by: -
Ramneek Mehresh authored
Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by:
Remy Bohmer <linux@bohmer.net> Signed-off-by:
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- Sep 29, 2011
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Wolfgang Denk authored
Signed-off-by:Wolfgang Denk <wd@denx.de>
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- Sep 28, 2011
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Linus Walleij authored
Since commit d388298a by Stefano Babic this file is no longer needed so delete it. Cc: Stefano Babic <sbabic@denx.de> Cc: Loïc Minier <loic.minier@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Wolfgang Denk authored
This reverts commit 041c5422. The lines removed by this commit weren't redundant. The logic is (and probably should be better commented): Find the intersection of the advertised capabilities of both sides of the link (lpa). From that intersection, find the highest capability we can run at (that will be the negotiated link). Now imagine that the intersection (lpa) is (LPA_100HALF | LPA_10FULL). The code will now set phydev->speed to 100, and phydev->duplex to 1, but this link does not support 100FULL. Kudos to Andy Fleming <afleming@gmail.com> for binging this to attention and for the explanation. Signed-off-by:
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