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  1. Jun 08, 2010
    • Cyril Chemparathy's avatar
      ARM1176: TI: TNETV107X soc initial support · 3712367c
      Cyril Chemparathy authored
      
      TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
      bunch on on-chip integrated peripherals.  This is an initial commit with
      basic functionality, more commits with drivers, etc. to follow.
      
      Signed-off-by: default avatarCyril Chemparathy <cyril@ti.com>
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      3712367c
    • Cyril Chemparathy's avatar
      ARM1176: Coexist with other ARM1176 platforms · 678e008c
      Cyril Chemparathy authored
      
      The current ARM1176 CPU specific code is too specific to the SMDK6400
      architecture.  The following changes were necessary prerequisites for the
      addition of other SoCs based on ARM1176.
      
      Existing board's (SMDK6400) configuration has been modified to keep behavior
      unchanged despite these changes.
      
      1. Peripheral port remap configurability
      The earlier code had hardcoded remap values specific to s3c64xx in start.S.
      This change makes the peripheral port remap addresses and sizes configurable.
      
      2. U-Boot code relocation support
      Most architectures allow u-boot code to run initially at a different
      address (possibly in NOR) and then get relocated to its final resting place
      in RAM.  Added support for this capability in ARM1176 architecture.
      
      3. Disable TCM if necessary
      If a ROM based bootloader happened to have initialized TCM, we disable it here
      to keep things sane.
      
      4. Remove unnecessary SoC specific includes
      ARM1176 code does not really need this SoC specific include.  The presence
      of this include prevents builds on other ARM1176 archs.
      
      5. Modified virt-to-phys conversion during MMU disable
      The original MMU disable code masks out too many bits from the load address
      when it tries to figure out the physical address of the jump target label.
      Consequently, it ends up branching to the wrong address after disabling the
      MMU.
      
      Signed-off-by: default avatarCyril Chemparathy <cyril@ti.com>
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      678e008c
  2. Jun 06, 2010
    • Asen Dimov's avatar
      add new board pm9g45 · b5d289fc
      Asen Dimov authored
      
      Add the new board PM9G45 from Ronetix GmbH.
      * AT91SAM9G45 MCU at 400Mhz.
      * 128MB DDR2 SDRAM
      * 256MB NAND
      * 10/100 MBits Ethernet DP83848
      * Serial number chip DS2401
      
      The board is made as SODIMM200 module.
      For more info www.ronatix.at or info@ronetix.at.
      
      Signed-off-by: default avatarAsen Dimov <dimov@ronetix.at>
      b5d289fc
  3. Jun 01, 2010
    • George G. Davis's avatar
      ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments · 409a07c9
      George G. Davis authored
      
      The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
      instruction which means "Invalidate Both Caches" when in fact the intent
      is to clean and invalidate all caches.  So add an "mcr p15, 0, %0, c7,
      c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
      Both Caches" instruction to insure that memory is consistent with any
      dirty cache lines.
      
      Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
      that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
      used.
      
      Signed-off-by: default avatarGeorge G. Davis <gdavis@mvista.com>
      409a07c9
  4. May 28, 2010
  5. May 26, 2010
  6. May 21, 2010
  7. May 19, 2010
  8. May 17, 2010
  9. May 16, 2010
  10. May 15, 2010
  11. May 12, 2010
    • York Sun's avatar
      Enabled support for Rev 1.3 SPD for DDR2 DIMMs · bcb6c2bb
      York Sun authored
      
      SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
      The difference has ben examined and the code is compatible.
      Speed bins is not verified on hardware for CL7 at this moment.
      
      This patch also enables SPD Rev 1.x where x is up to "F". According to SPD
      spec, the lower nibble is optionally used to determine which additinal bytes
      or attribute bits have been defined. Software can safely use defaults. However,
      the upper nibble should always be checked.
      
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      bcb6c2bb
    • Kumar Gala's avatar
      85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled · f54fe87a
      Kumar Gala authored
      
      On the MPC85xx platform if we have SATA its connected on SERDES.
      Determing if SATA is enabled via sata_initialize should not be board
      specific and thus we move it out of the MPC8536DS board code.
      
      Additionally, now that we have is_serdes_configured() we can determine
      if the given SATA port is enabled and error out if its not in the
      driver.
      
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      f54fe87a
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