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  1. Jun 22, 2010
  2. Jun 21, 2010
  3. Jun 17, 2010
  4. Jun 14, 2010
  5. Jun 13, 2010
    • Wolfgang Denk's avatar
      Prepare v2010-rc2 · a9046b9e
      Wolfgang Denk authored
      
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      a9046b9e
    • Marek Vasut's avatar
      PXA: Align stack to 8 bytes · 3a96ad85
      Marek Vasut authored
      
      Part of this patch is by: Mikhail Kshevetskiy.
      
      Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD
      instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour
      is undefined.
      
      The issue was observed when working with the NAND code, which was rendered
      disfunctional. Also, the vsprintf() function had serious problems with printing
      64bit wide long longs. After aligning the stack, this wrong behaviour is no
      longer present.
      
      Tested on:
      	Marvell Littleton PXA310 board
      	Toradex Colibri PXA320 board
      	Aeronix Zipit Z2 PXA270 handheld
      	Voipac PXA270 board
      
      Signed-off-by: default avatarMarek Vasut <marek.vasut@gmail.com>
      3a96ad85
  6. Jun 10, 2010
  7. Jun 08, 2010
  8. Jun 07, 2010
  9. Jun 06, 2010
    • Asen Dimov's avatar
      add new board pm9g45 · b5d289fc
      Asen Dimov authored
      
      Add the new board PM9G45 from Ronetix GmbH.
      * AT91SAM9G45 MCU at 400Mhz.
      * 128MB DDR2 SDRAM
      * 256MB NAND
      * 10/100 MBits Ethernet DP83848
      * Serial number chip DS2401
      
      The board is made as SODIMM200 module.
      For more info www.ronatix.at or info@ronetix.at.
      
      Signed-off-by: default avatarAsen Dimov <dimov@ronetix.at>
      b5d289fc
  10. Jun 04, 2010
  11. Jun 01, 2010
    • George G. Davis's avatar
      ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments · 409a07c9
      George G. Davis authored
      
      The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
      instruction which means "Invalidate Both Caches" when in fact the intent
      is to clean and invalidate all caches.  So add an "mcr p15, 0, %0, c7,
      c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
      Both Caches" instruction to insure that memory is consistent with any
      dirty cache lines.
      
      Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
      that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
      used.
      
      Signed-off-by: default avatarGeorge G. Davis <gdavis@mvista.com>
      409a07c9
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