Skip to content
Snippets Groups Projects
Commit f133796d authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)


Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout.  Set timeout to maximum to avoid.

Based on a patch from Lan Chunhe <b25806@freescale.com>

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 868da593
No related branches found
No related tags found
No related merge requests found
...@@ -65,6 +65,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ...@@ -65,6 +65,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
puts("Work-around for Erratum CPC-A003 enabled\n"); puts("Work-around for Erratum CPC-A003 enabled\n");
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
puts("Work-around for Erratum ELBC-A001 enabled\n");
#endif
return 0; return 0;
} }
......
/* /*
* Copyright 2010 Freescale Semiconductor, Inc. * Copyright 2010-2011 Freescale Semiconductor, Inc.
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License * modify it under the terms of the GNU General Public License
...@@ -34,6 +34,11 @@ void init_early_memctl_regs(void) ...@@ -34,6 +34,11 @@ void init_early_memctl_regs(void)
{ {
uint init_br1 = 1; uint init_br1 = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
/* Set the local bus monitor timeout value to the maximum */
clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
#endif
#ifdef CONFIG_MPC85xx #ifdef CONFIG_MPC85xx
/* if cs1 is already set via debugger, leave cs0/cs1 alone */ /* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (get_lbc_br(1) & BR_V) if (get_lbc_br(1) & BR_V)
......
/* /*
* Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc. * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
...@@ -295,6 +295,8 @@ void lbc_sdram_init(void); ...@@ -295,6 +295,8 @@ void lbc_sdram_init(void);
#define LBCR_EPAR_SHIFT 16 #define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00 #define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8 #define LBCR_BMT_SHIFT 8
#define LBCR_BMTPS 0x0000000F
#define LBCR_BMTPS_SHIFT 0
/* LCRR - Clock Ratio Register /* LCRR - Clock Ratio Register
*/ */
......
...@@ -43,5 +43,6 @@ ...@@ -43,5 +43,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#include "corenet_ds.h" #include "corenet_ds.h"
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment