ppc/85xx: Map boot page guarded for MP boot

We already map the page cache-inhibited.  There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

board/freescale/mpc8572ds/tlb.c

@@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */

board/freescale/p1_p2_rdb/tlb.c

@@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */

board/freescale/p2020ds/tlb.c

@@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */

cpu/mpc85xx/mp.c

@@ -312,7 +312,7 @@ void setup_mp(void)
 		disable_tlb(i);
 
 		set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
 		memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);

cpu/mpc85xx/release.S

@@ -166,8 +166,8 @@ __secondary_start_page:
 	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
 	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 	mtspr	SPRN_MAS1,r11
-	oris	r11,r13,(MAS2_I)@h
-	ori	r11,r13,(MAS2_I)@l
+	oris	r11,r13,(MAS2_I|MAS2_G)@h
+	ori	r11,r13,(MAS2_I|MAS2_G)@l
 	mtspr	SPRN_MAS2,r11
 	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
 	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l