Skip to content
Snippets Groups Projects
Commit 97c9f290 authored by Felix Radensky's avatar Felix Radensky Committed by Stefan Roese
Browse files

ppc4xx: Fix sending type 1 PCI transactions


The list of 4xx SoCs that should send type 1 PCI transactions
is not defined correctly. As a result PCI-PCI bridges and devices
behind them are not identified. The following 4xx variants should
send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.

Signed-off-by: default avatarFelix Radensky <felix@embedded-sol.com>
Signed-off-by: default avatarStefan Roese <sr@denx.de>
parent 57ae8a5c
No related branches found
No related tags found
No related merge requests found
...@@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ ...@@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \ return 0; \
} }
#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) #elif defined(CONFIG_440GX) || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ #define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \ static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \ indirect_##rw##_config_##size(struct pci_controller *hose, \
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment