Initial mpc8610hpcd cpu/, README and include/ files.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

cpu/mpc86xx/cpu.c

@@ -41,6 +41,8 @@ checkcpu(void)
 	uint major, minor;
 	uint lcrr;		/* local bus clock ratio register */
 	uint clkdiv;		/* clock divider portion of lcrr */
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
 
 	puts("Freescale PowerPC\n");
 
@@ -54,8 +56,14 @@ checkcpu(void)
 
 	switch (ver) {
 	case PVR_VER(PVR_86xx):
-		puts("E600");
-		break;
+	{
+		uint msscr0 = mfspr(MSSCR0);
+		printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
+		if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
+			puts("\n    Core1Translation Enabled");
+		debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
+	}
+	break;
 	default:
 		puts("Unknown");
 		break;
@@ -76,6 +84,9 @@ checkcpu(void)
 		puts("8641");
 	    }
 	    break;
+	case SVR_8610:
+		puts("8610");
+		break;
 	default:
 		puts("Unknown");
 		break;

doc/README.mpc8610hpcd

+Freescale MPC8610HPCD board
+===========================
+
+
+Building U-Boot
+---------------
+
+    $ make MPC8610HPCD_config
+    Configuring for MPC8610HPCD board...
+
+    $ make
+
+
+Flashing U-Boot
+---------------
+The flash is 128M starting at 0xF800_0000.
+
+The alternate image is at 0xFBF0_0000
+The      boot image is at 0xFFF0_0000.
+
+
+To Flash U-Boot into the booting bank:
+
+	tftp 1000000 u-boot.bin
+	protect off all
+	erase fff00000 +$filesize
+	cp.b 1000000 fff00000 $filesize
+
+
+To Flash U-boot into the alternate bank
+
+	tftp 1000000 u-boot.bin
+	erase fbf00000 +$filesize
+	cp.b 1000000 fbf00000 $filesize
+
+
+pixis_reset command
+-------------------
+A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
+using the FPGA sequencer.  When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+	pixis_reset
+	pixis_reset altbank
+	pixis_reset altbank wd
+	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+	/* reset to current bank, like "reset" command */
+	pixis_reset
+
+	/* reset board but use the to alternate flash bank */
+	pixis_reset altbank
+
+	/* reset board, use alternate flash bank with watchdog timer enabled*/
+	pixis_reset altbank wd
+
+	/* reset board to alternate bank with frequency changed.
+	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+	 */
+	pixis-reset altbank cf 40 2.5 10

include/asm-ppc/processor.h

@@ -875,6 +875,7 @@
 #define SVR_8544_E	0x803C
 #define SVR_8548	0x8031
 #define SVR_8548_E	0x8039
+#define SVR_8610	0x80A0
 #define SVR_8641	0x8090
 #define SVR_8568_E	0x807D