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Commit 7cee1dfd authored by Kumar Gala's avatar Kumar Gala
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powerpc/86xx: Convert SBC8641 to use common SRIO init code

parent 1b77ca8a
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...@@ -51,7 +51,6 @@ struct law_entry law_table[] = { ...@@ -51,7 +51,6 @@ struct law_entry law_table[] = {
#endif #endif
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
}; };
int num_law_entries = ARRAY_SIZE(law_table); int num_law_entries = ARRAY_SIZE(law_table);
...@@ -57,6 +57,9 @@ ...@@ -57,6 +57,9 @@
*/ */
#define CONFIG_SYS_SCRATCH_VA 0xe8000000 #define CONFIG_SYS_SCRATCH_VA 0xe8000000
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_PCI 1 /* Enable PCIE */ #define CONFIG_PCI 1 /* Enable PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
...@@ -297,9 +300,9 @@ ...@@ -297,9 +300,9 @@
/* /*
* RapidIO MMU * RapidIO MMU
*/ */
#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
/* /*
* General PCI * General PCI
...@@ -417,10 +420,10 @@ ...@@ -417,10 +420,10 @@
* BAT2 512M Cache-inhibited, guarded * BAT2 512M Cache-inhibited, guarded
* 0xc000_0000 512M RapidIO Memory * 0xc000_0000 512M RapidIO Memory
*/ */
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/* /*
......
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