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vesta
u-boot-2015.04
Commits
793670c3
Commit
793670c3
authored
16 years ago
by
Sergei Poselenov
Committed by
Wolfgang Denk
16 years ago
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Fixed reset for socrates
Signed-off-by:
Sergei Poselenov
<
sposelenov@emcraft.com
>
parent
e18575d5
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Changes
1
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1 changed file
cpu/mpc85xx/cpu.c
+14
-9
14 additions, 9 deletions
cpu/mpc85xx/cpu.c
with
14 additions
and
9 deletions
cpu/mpc85xx/cpu.c
+
14
−
9
View file @
793670c3
...
@@ -174,28 +174,33 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
...
@@ -174,28 +174,33 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
{
uint
pvr
;
uint
pvr
;
uint
ver
;
uint
ver
;
unsigned
long
val
,
msr
;
pvr
=
get_pvr
();
pvr
=
get_pvr
();
ver
=
PVR_VER
(
pvr
);
ver
=
PVR_VER
(
pvr
);
if
(
ver
&
1
){
if
(
ver
&
1
){
/* e500 v2 core has reset control register */
/* e500 v2 core has reset control register */
volatile
unsigned
int
*
rstcr
;
volatile
unsigned
int
*
rstcr
;
rstcr
=
(
volatile
unsigned
int
*
)(
CFG_IMMR
+
0xE00B0
);
rstcr
=
(
volatile
unsigned
int
*
)(
CFG_IMMR
+
0xE00B0
);
*
rstcr
=
0x2
;
/* HRESET_REQ */
*
rstcr
=
0x2
;
/* HRESET_REQ */
}
else
{
udelay
(
100
);
}
/*
/*
* Fallthrough if the code above failed
* Initiate hard reset in debug control register DBCR0
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
* Make sure MSR[DE] = 1
*/
*/
unsigned
long
val
,
msr
;
msr
=
mfmsr
();
msr
=
mfmsr
();
msr
|=
MSR_DE
;
msr
|=
MSR_DE
;
mtmsr
(
msr
);
mtmsr
(
msr
);
val
=
mfspr
(
DBCR0
);
val
|=
0x70000000
;
mtspr
(
DBCR0
,
val
);
val
=
mfspr
(
DBCR0
);
val
|=
0x70000000
;
mtspr
(
DBCR0
,
val
);
}
return
1
;
return
1
;
}
}
...
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