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Shaohui Xie authored
CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
Shaohui Xie authoredCPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by:
