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Commit efd14598 authored by David Mondou's avatar David Mondou
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Enable unknown reserved bit as per eval kit.

parent d5e5c7e0
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......@@ -198,12 +198,12 @@
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x00001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x00001820
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x40001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x40001820
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
......@@ -214,8 +214,8 @@
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x00001820
MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x00001820
MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x40001820
MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x40001820
>;
};
......
......@@ -213,22 +213,22 @@
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x00001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x00001820
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x40001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x40001820
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x00001820
MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x00001820
MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x40001820
MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x40001820
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x00001820
MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x00001820
MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x40001820
MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x40001820
>;
};
......
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