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vesta
meta-vesta
Commits
b397de13
Commit
b397de13
authored
6 years ago
by
David Mondou
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Added ring and dcd pins to Gemalto device tree overlay
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0f4d41a2
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recipes-kernel/linux/linux-fslc-imx/device-tree/vesta-300B.dts
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3 additions, 1 deletion
...es-kernel/linux/linux-fslc-imx/device-tree/vesta-300B.dts
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recipes-kernel/linux/linux-fslc-imx/device-tree/vesta-300B.dts
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b397de13
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@@ -370,7 +370,7 @@
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x000010B0 /* Ring */
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x000010B0 /* DCD */
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x000010B0
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x000010B0
/* Cell Wakeup */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000010B0 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x000010B0 /* Cell pwr shtdn */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x000010B0 /* Cell reset */
...
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@@ -382,6 +382,8 @@
pinctrl_gemalto_cellmdm: gemaltocellmdmgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x000010B0 /* Ring */
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x000010B0 /* DCD */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000010B0 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x000010B0 /* Cell pwr shtdn */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x000010B0 /* Cell IGT */
...
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