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Commit a9358bbd authored by David Mondou's avatar David Mondou
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Add tau board support

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recipes-extended/openocd/files/imx-tau.cfg 0 → 100644
+ 35
− 0
View file @ a9358bbd
#
# Config for using NXP IMX CPU
#
# This is best used with a fast enough buffer but also
# is suitable for direct connection if the target voltage
# matches to host voltage and the cable is short enough.
#
#
interface imx_gpio
# For most IMX processors 0x0209c000
imx_gpio_peripheral_base 0x0209c000
# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
# These depend on system clock, calibrated for IMX6UL@528MHz
# imx_gpio_speed SPEED_COEFF SPEED_OFFSET
imx_gpio_speed_coeffs 50000 50
# Each of the JTAG lines need a gpio number set: tck tms tdi tdo.
# Example configuration:
# imx_gpio_jtag_nums 6 7 8 9
# SWD interface pins: swclk swdio
# Example configuration:
imx_gpio_swd_nums 22 23
# imx_gpio_trst_num 120
reset_config none separate
# imx_gpio_srst_num 11
# reset_config srst_only srst_push_pull
# or if you have both connected,
# reset_config trst_and_srst srst_push_pull
recipes-extended/openocd/openocd_0.10.0.bb
+ 3
− 0
View file @ a9358bbd
......@@ -22,6 +22,7 @@ SRC_URI = "git://git.rigado.com/vesta/openocd;protocol=https \
file://gwmode-rm-zephyr.sh \
file://r41z_program.sh \
file://load_zephyr \
file://imx-tau.cfg \
"
do_configure() {
......@@ -58,6 +59,7 @@ do_install() {
install -m 0744 ${WORKDIR}/gwmode-zephyr.sh ${D}${bindir}
install -m 0744 ${WORKDIR}/gwmode-rm-zephyr.sh ${D}${bindir}
install -m 0744 ${WORKDIR}/r41z_program.sh ${D}${bindir}
install -m 0744 ${WORKDIR}/imx-tau.cfg ${D}/usr/share/openocd/scripts/interface
install -d ${D}${sysconfdir}/init.d
install -m 0755 ${WORKDIR}/load_zephyr ${D}${sysconfdir}/init.d
......@@ -76,6 +78,7 @@ FILES_${PN} += " \
/usr/share/openocd/scripts/target/swj-dp.tcl \
/usr/share/openocd/scripts/interface/imx-native.cfg \
/usr/share/openocd/scripts/cpu/arm/arm7tdmi.tcl \
/usr/share/openocd/scripts/interface/imx-tau.cfg \
"
COMPATIBLE_MACHINE = "(vesta|imx6ul)"
recipes-kernel/linux/linux-fslc-imx.inc
+ 4
− 0
View file @ a9358bbd
......@@ -25,6 +25,7 @@ SRC_URI += "file://defconfig \
file://device-tree/310-00110-0006.dts \
file://device-tree/310-00121-0001.dts \
file://device-tree/310-00121-0003.dts \
file://device-tree/310-00125-0002.dts \
file://device-tree/vesta-mfg.dtsi \
file://patches/0001-QCA6234-driver.patch \
file://patches/0001-bluebourne.patch \
......@@ -64,6 +65,7 @@ do_configure_append() {
cp ${WORKDIR}/device-tree/310-00110-0006.dts ${S}/arch/${ARCH}/boot/dts
cp ${WORKDIR}/device-tree/310-00121-0001.dts ${S}/arch/${ARCH}/boot/dts
cp ${WORKDIR}/device-tree/310-00121-0003.dts ${S}/arch/${ARCH}/boot/dts
cp ${WORKDIR}/device-tree/310-00125-0002.dts ${S}/arch/${ARCH}/boot/dts
}
do_install_append() {
......@@ -73,6 +75,7 @@ do_install_append() {
install -m 755 ${B}/arch/${ARCH}/boot/dts/310-00110-0006.dtb ${D}${base_libdir}/firmware/overlays/310-00110-0006.dtbo
install -m 755 ${B}/arch/${ARCH}/boot/dts/310-00121-0001.dtb ${D}${base_libdir}/firmware/overlays/310-00121-0001.dtbo
install -m 755 ${B}/arch/${ARCH}/boot/dts/310-00121-0003.dtb ${D}${base_libdir}/firmware/overlays/310-00121-0003.dtbo
install -m 755 ${B}/arch/${ARCH}/boot/dts/310-00125-0002.dtb ${D}${base_libdir}/firmware/overlays/310-00125-0002.dtbo
}
FILES_kernel-base += " \
......@@ -81,4 +84,5 @@ FILES_kernel-base += " \
${base_libdir}/firmware/overlays/310-00110-0006.dtbo \
${base_libdir}/firmware/overlays/310-00121-0001.dtbo \
${base_libdir}/firmware/overlays/310-00121-0003.dtbo \
${base_libdir}/firmware/overlays/310-00125-0002.dtbo \
"
recipes-kernel/linux/linux-fslc-imx/device-tree/vesta-500.dts
+ 100
− 9
View file @ a9358bbd
......@@ -72,6 +72,11 @@
compatible = "rigado,vesta-exp-card";
status = "disabled";
};
tau_board: tau_board {
compatible = "rigado,vesta-exp-card";
status = "disabled";
};
};
&cpu0 {
......@@ -303,6 +308,16 @@
>;
};
pinctrl_uart4_flowctrl: uart4grp_flowctrl {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00001020
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00001020
MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x00001020
MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x00001020
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x00001020
......@@ -310,33 +325,57 @@
>;
};
pinctrl_uart5_flowctrl: uart5grp_flowctrl {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x00001020
MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x00001020
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x00001020
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x00001020
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x00001020
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x00001020
MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00001020
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00001008
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00001008
MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00001008
MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x00001008
MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x00001008
>;
};
pinctrl_uart7_flowctrl: uart7grp_flowctrl {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00001008
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00001008
MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x00001008
MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x00001008
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00001020
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00001020
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00001020
>;
};
pinctrl_uart8_flowctrl: uart8grp_flowctrl {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b1
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b1
MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00001008
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000090A0
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00001008
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000090A0
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000090A0
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000090A0
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000090A0
......@@ -392,6 +431,26 @@
>;
};
pinctrl_tau80: tau80grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x00001020 /* BLE1_INT_IN */
MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x00001020 /* BLE2_INT_IN */
MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x00001020 /* BLE3_INT_IN */
MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x00001020 /* BLE4_INT_IN */
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x00001020 /* BLE1_RST_N */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x00001020 /* BLE2_RST_N */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00001020 /* BLE3_RST_N */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00001020 /* BLE4_RST_N */
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00001020 /* SWD_CLK1 */
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x00001020 /* SWD_CLK2 */
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x00001020 /* SWD_CLK3 */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x00001020 /* SWD_IO */
>;
};
};
};
......@@ -431,11 +490,43 @@
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_flowctrl>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5_flowctrl>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
status = "disabled";
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
pinctrl-0 = <&pinctrl_uart7_flowctrl>;
fsl,uart-has-rtscts;
status = "okay";
status = "disabled";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8_flowctrl>;
fsl,uart-has-rtscts;
status = "disabled";
};
&usbotg1 {
......
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