Commit a80e2bde authored by David Mondou's avatar David Mondou
Browse files

Adjust eth and cell pin drive strengths. Enable uart7 by default

parent 3401afdc
......@@ -205,8 +205,8 @@
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x000010A0
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00001820
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x00002008
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00002008
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00001088
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00001088
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40001008
......@@ -368,28 +368,28 @@
pinctrl_vz_cellmdm: vzcellmdmgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x000010B0 /* Ring */
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x000010B0 /* DCD */
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x000010B0 /* Cell Wakeup */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000010B0 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x000010B0 /* Cell pwr shtdn */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x000010B0 /* Cell reset */
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x000010B0 /* Cell disable */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x000010B0 /* Clee status */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x000010B0 /* Cell pwr key */
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x00001020 /* Ring */
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00001020 /* DCD */
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x00001020 /* Cell Wakeup */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x00001020 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x00001020 /* Cell pwr shtdn */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x00001020 /* Cell reset */
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00001020 /* Cell disable */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00001020 /* Clee status */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00001020 /* Cell pwr key */
>;
};
pinctrl_gemalto_cellmdm: gemaltocellmdmgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x000010B0 /* Ring */
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x000010B0 /* DCD */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000010B0 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x000010B0 /* Cell pwr shtdn */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x000010B0 /* Cell IGT */
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x000010B0 /* Cell EOFF */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x000010B0 /* Clee status */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x000010B0 /* Cell shdn */
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x00001020 /* Ring */
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00001020 /* DCD */
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x00001020 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x00001020 /* Cell pwr shtdn */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00001020 /* Cell IGT */
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00001020 /* Cell EOFF */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00001020 /* Clee status */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x00001020 /* Cell shdn */
>;
};
......@@ -432,6 +432,13 @@
status = "okay";
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "host";
disable-over-current;
......
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