Newer
Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
/*
* Copyright (C) 2018 Rigado
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"
/ {
model = "Rigado Vesta 300B Board ";
compatible = "fsl,vesta-500", "fsl,vesta-300B", "fsl,imx6ull";
version = "1.0.0";
chosen {
stdout-path = &uart2;
};
memory {
reg = <0x80000000 0x8000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x200000>;
linux,cma-default;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_can_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "can-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vref_3v3: regulator@1 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
/* All expansion cards should be listed here, as disabled */
verizon_cellmdm: verizon_cellmdm {
compatible = "rigado,vesta-exp-card";
status = "disabled";
};
gemalto_cellmdm: gemalto_cellmdm {
compatible = "rigado,vesta-exp-card";
status = "disabled";
};
};
&cpu0 {
arm-supply = <®_arm>;
soc-supply = <®_soc>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <ðphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
ethphy1: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
};
};
&gpc {
fsl,cpu_pupscr_sw2iso = <0x1>;
fsl,cpu_pupscr_sw = <0x0>;
fsl,cpu_pdnscr_iso2sw = <0x1>;
fsl,cpu_pdnscr_iso = <0x1>;
fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
exp_eeprom@50 {
compatible = "24c32";
reg = <0x50>;
pagesize = <32>;
#address-cells = <1>;
#size-cells = <1>;
exp0_data: exp_data@0 {
reg = <0 0x4A>;
};
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
status = "okay";
vref-supply = <®_vref_3v3>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx6ull_evk: imx6ull_evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x00001020 /* BLE_RST_N */
MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x00001020 /* SWDIO */
MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x00001020 /* SWCLK */
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x00001020 /* PMIC INT N */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x00001020 /* BT GPIO */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x00001020 /* BT RST N */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x00001020 /* ENET1 RST N */
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x00001020 /* RST BTN */
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x00001020 /* BT INT N */
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x00001020 /* ENET1 INT N */
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x000010A0 /* eMMC RST N */
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x00013020 /* user btn */
>;
};
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x00001020
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x00001020
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 00001020
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x00001020
MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x00001020
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x00001020
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x00001020
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x00001020
MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x00001020
MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00001020
MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00001020
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0001b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x0001b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0001b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0001b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x0001b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x0001b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0001b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0001b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x0001b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x40001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x40001820
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x40001820
MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x40001820
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x40001820
MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x40001820
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x00009030
>;
};
pinctrl_pwm6: pwm6grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x00007030
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x00009020
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x00001020
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x00001020
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x00001020
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x00001020
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x00001020
>;
};
pinctrl_sjc: sjcgrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__SJC_MOD 0x00003020
MX6UL_PAD_JTAG_TCK__SJC_TCK 0x00003020
MX6UL_PAD_JTAG_TDO__SJC_TDO 0x00009021
MX6UL_PAD_JTAG_TMS__SJC_TMS 0x00007020
MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x00007020
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x00001020
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x00001020
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x00001020
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x00001020
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x00001020
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x00001020
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00001020
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00001020
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00001020
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00001020
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00001020
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00001020
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x00001020
MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x00001020
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x00001020
MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00001020
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00001020
MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00001020
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00001020
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00001020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x000010A0
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000090A0
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000090A0
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000090A0
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000090A0
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000090A0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000090A0
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000010A0
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000010A0
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000010A0
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000010A0
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000010A0
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000010A0
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000010A0
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000010A0
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000090A0
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x000010B0
>;
};
pinctrl_vz_cellmdm: vzcellmdmgrp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x000010B0
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000010B0 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x000010B0 /* Cell pwr shtdn */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x000010B0 /* Cell reset */
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x000010B0 /* Cell disable */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x000010B0 /* Clee status */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x000010B0 /* Cell pwr key */
>;
};
pinctrl_gemalto_cellmdm: gemaltocellmdmgrp {
fsl,pins = <
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000010B0 /* VBUS EN */
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x000010B0 /* Cell pwr shtdn */
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x000010B0 /* Cell IGT */
MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x000010B0 /* Cell EOFF */
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x000010B0 /* Clee status */
MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x000010B0 /* Cell shdn */
>;
};
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
clocks = <&clks IMX6UL_CLK_PWM2>,
<&clks IMX6UL_CLK_PWM2>;
};
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";
clocks = <&clks IMX6UL_CLK_PWM6>,
<&clks IMX6UL_CLK_PWM6>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbphy1 {
tx-d-cal = <0x5>;
};
&usbphy2 {
tx-d-cal = <0x5>;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,wdog_b;
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifi>;
no-1-8-v;
non-removable;
bus-width = <4>;
pm-ignore-notify;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
bus-width = <8>;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
/* Vesta expansion card DT overlay manager - based on beaglebone cape manager */
/ {
vesta_overlaymgr {
compatible = "rigado,vesta-overlaymgr";
status = "okay";
nvmem-cells = <&exp0_data>;
nvmem-cell-names = "slot0";
#slots = <1>;
/* map board revisions to compatible definitions */
baseboardmaps {
baseboard_vesta: board@0 {
board-name ="vesta";
compatible-name = "rigado,vesta";
};
};
};
};