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#define USB_ERREN_DFN8EN (uint8_t)0x08 //
#define USB_ERREN_CRC16EN (uint8_t)0x04 //
#define USB_ERREN_CRC5EOFEN (uint8_t)0x02 //
#define USB_ERREN_PIDERREN (uint8_t)0x01 //
#define USB0_STAT *(volatile uint8_t *)0x40072090 // Status Register
#define USB_STAT_TX (uint8_t)0x08 //
#define USB_STAT_ODD (uint8_t)0x04 //
#define USB_STAT_ENDP(n) (uint8_t)((n) >> 4) //
#define USB0_CTL *(volatile uint8_t *)0x40072094 // Control Register
#define USB_CTL_JSTATE (uint8_t)0x80 //
#define USB_CTL_SE0 (uint8_t)0x40 //
#define USB_CTL_TXSUSPENDTOKENBUSY (uint8_t)0x20 //
#define USB_CTL_RESET (uint8_t)0x10 //
#define USB_CTL_HOSTMODEEN (uint8_t)0x08 //
#define USB_CTL_RESUME (uint8_t)0x04 //
#define USB_CTL_ODDRST (uint8_t)0x02 //
#define USB_CTL_USBENSOFEN (uint8_t)0x01 //
#define USB0_ADDR *(volatile uint8_t *)0x40072098 // Address Register
#define USB0_BDTPAGE1 *(volatile uint8_t *)0x4007209C // BDT Page Register 1
#define USB0_FRMNUML *(volatile uint8_t *)0x400720A0 // Frame Number Register Low
#define USB0_FRMNUMH *(volatile uint8_t *)0x400720A4 // Frame Number Register High
#define USB0_TOKEN *(volatile uint8_t *)0x400720A8 // Token Register
#define USB0_SOFTHLD *(volatile uint8_t *)0x400720AC // SOF Threshold Register
#define USB0_BDTPAGE2 *(volatile uint8_t *)0x400720B0 // BDT Page Register 2
#define USB0_BDTPAGE3 *(volatile uint8_t *)0x400720B4 // BDT Page Register 3
#define USB0_ENDPT0 *(volatile uint8_t *)0x400720C0 // Endpoint Control Register
#define USB_ENDPT_HOSTWOHUB (uint8_t)0x80 // host only, enable low speed
#define USB_ENDPT_RETRYDIS (uint8_t)0x40 // host only, set to disable NAK retry
#define USB_ENDPT_EPCTLDIS (uint8_t)0x10 // 0=control, 1=bulk, interrupt, isync
#define USB_ENDPT_EPRXEN (uint8_t)0x08 // enables the endpoint for RX transfers.
#define USB_ENDPT_EPTXEN (uint8_t)0x04 // enables the endpoint for TX transfers.
#define USB_ENDPT_EPSTALL (uint8_t)0x02 // set to stall endpoint
#define USB_ENDPT_EPHSHK (uint8_t)0x01 // enable handshaking during a transaction, generally set unless Isochronous
#define USB0_ENDPT1 *(volatile uint8_t *)0x400720C4 // Endpoint Control Register
#define USB0_ENDPT2 *(volatile uint8_t *)0x400720C8 // Endpoint Control Register
#define USB0_ENDPT3 *(volatile uint8_t *)0x400720CC // Endpoint Control Register
#define USB0_ENDPT4 *(volatile uint8_t *)0x400720D0 // Endpoint Control Register
#define USB0_ENDPT5 *(volatile uint8_t *)0x400720D4 // Endpoint Control Register
#define USB0_ENDPT6 *(volatile uint8_t *)0x400720D8 // Endpoint Control Register
#define USB0_ENDPT7 *(volatile uint8_t *)0x400720DC // Endpoint Control Register
#define USB0_ENDPT8 *(volatile uint8_t *)0x400720E0 // Endpoint Control Register
#define USB0_ENDPT9 *(volatile uint8_t *)0x400720E4 // Endpoint Control Register
#define USB0_ENDPT10 *(volatile uint8_t *)0x400720E8 // Endpoint Control Register
#define USB0_ENDPT11 *(volatile uint8_t *)0x400720EC // Endpoint Control Register
#define USB0_ENDPT12 *(volatile uint8_t *)0x400720F0 // Endpoint Control Register
#define USB0_ENDPT13 *(volatile uint8_t *)0x400720F4 // Endpoint Control Register
#define USB0_ENDPT14 *(volatile uint8_t *)0x400720F8 // Endpoint Control Register
#define USB0_ENDPT15 *(volatile uint8_t *)0x400720FC // Endpoint Control Register
#define USB0_USBCTRL *(volatile uint8_t *)0x40072100 // USB Control Register
#define USB_USBCTRL_SUSP (uint8_t)0x80 // Places the USB transceiver into the suspend state.
#define USB_USBCTRL_PDE (uint8_t)0x40 // Enables the weak pulldowns on the USB transceiver.
#define USB0_OBSERVE *(volatile uint8_t *)0x40072104 // USB OTG Observe Register
#define USB_OBSERVE_DPPU (uint8_t)0x80 //
#define USB_OBSERVE_DPPD (uint8_t)0x40 //
#define USB_OBSERVE_DMPD (uint8_t)0x10 //
#define USB0_CONTROL *(volatile uint8_t *)0x40072108 // USB OTG Control Register
#define USB_CONTROL_DPPULLUPNONOTG (uint8_t)0x10 // Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode.
#define USB0_USBTRC0 *(volatile uint8_t *)0x4007210C // USB Transceiver Control Register 0
#define USB_USBTRC_USBRESET (uint8_t)0x80 //
#define USB_USBTRC_USBRESMEN (uint8_t)0x20 //
#define USB_USBTRC_SYNC_DET (uint8_t)0x02 //
#define USB_USBTRC_USB_RESUME_INT (uint8_t)0x01 //
#define USB0_USBFRMADJUST *(volatile uint8_t *)0x40072114 // Frame Adjust Register
// Chapter 41: USB Device Charger Detection Module (USBDCD)
#define USBDCD_CONTROL *(volatile uint32_t *)0x40035000 // Control register
#define USBDCD_CLOCK *(volatile uint32_t *)0x40035004 // Clock register
#define USBDCD_STATUS *(volatile uint32_t *)0x40035008 // Status register
#define USBDCD_TIMER0 *(volatile uint32_t *)0x40035010 // TIMER0 register
#define USBDCD_TIMER1 *(volatile uint32_t *)0x40035014 // TIMER1 register
#define USBDCD_TIMER2 *(volatile uint32_t *)0x40035018 // TIMER2 register
// Chapter 43: SPI (DSPI)
#define SPI0_MCR *(volatile uint32_t *)0x4002C000 // DSPI Module Configuration Register
#define SPI_MCR_MSTR (uint32_t)0x80000000 // Master/Slave Mode Select
#define SPI_MCR_CONT_SCKE (uint32_t)0x40000000 //
#define SPI_MCR_DCONF(n) (((n) & 3) << 28) //
#define SPI_MCR_FRZ (uint32_t)0x08000000 //
#define SPI_MCR_MTFE (uint32_t)0x04000000 //
#define SPI_MCR_ROOE (uint32_t)0x01000000 //
#define SPI_MCR_PCSIS(n) (((n) & 0x1F) << 16) //
#define SPI_MCR_DOZE (uint32_t)0x00008000 //
#define SPI_MCR_MDIS (uint32_t)0x00004000 //
#define SPI_MCR_DIS_TXF (uint32_t)0x00002000 //
#define SPI_MCR_DIS_RXF (uint32_t)0x00001000 //
#define SPI_MCR_CLR_TXF (uint32_t)0x00000800 //
#define SPI_MCR_CLR_RXF (uint32_t)0x00000400 //
#define SPI_MCR_SMPL_PT(n) (((n) & 3) << 8) //
#define SPI_MCR_HALT (uint32_t)0x00000001 //
#define SPI0_TCR *(volatile uint32_t *)0x4002C008 // DSPI Transfer Count Register
#define SPI0_CTAR0 *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Master Mode
#define SPI_CTAR_DBR (uint32_t)0x80000000 // Double Baud Rate
#define SPI_CTAR_FMSZ(n) (((n) & 15) << 27) // Frame Size (+1)
#define SPI_CTAR_CPOL (uint32_t)0x04000000 // Clock Polarity
#define SPI_CTAR_CPHA (uint32_t)0x02000000 // Clock Phase
#define SPI_CTAR_LSBFE (uint32_t)0x01000000 // LSB First
#define SPI_CTAR_PCSSCK(n) (((n) & 3) << 22) // PCS to SCK Delay Prescaler
#define SPI_CTAR_PASC(n) (((n) & 3) << 20) // After SCK Delay Prescaler
#define SPI_CTAR_PDT(n) (((n) & 3) << 18) // Delay after Transfer Prescaler
#define SPI_CTAR_PBR(n) (((n) & 3) << 16) // Baud Rate Prescaler
#define SPI_CTAR_CSSCK(n) (((n) & 15) << 12) // PCS to SCK Delay Scaler
#define SPI_CTAR_ASC(n) (((n) & 15) << 8) // After SCK Delay Scaler
#define SPI_CTAR_DT(n) (((n) & 15) << 4) // Delay After Transfer Scaler
#define SPI_CTAR_BR(n) (((n) & 15) << 0) // Baud Rate Scaler
#define SPI0_CTAR0_SLAVE *(volatile uint32_t *)0x4002C00C // DSPI Clock and Transfer Attributes Register, In Slave Mode
#define SPI0_CTAR1 *(volatile uint32_t *)0x4002C010 // DSPI Clock and Transfer Attributes Register, In Master Mode
#define SPI0_SR *(volatile uint32_t *)0x4002C02C // DSPI Status Register
#define SPI_SR_TCF (uint32_t)0x80000000 // Transfer Complete Flag
#define SPI_SR_TXRXS (uint32_t)0x40000000 // TX and RX Status
#define SPI_SR_EOQF (uint32_t)0x10000000 // End of Queue Flag
#define SPI_SR_TFUF (uint32_t)0x08000000 // Transmit FIFO Underflow Flag
#define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag
#define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag
#define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag
#define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register
#define SPI0_PUSHR *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Master Mode
#define SPI_PUSHR_CONT (uint32_t)0x80000000 //
#define SPI_PUSHR_CTAS(n) (((n) & 7) << 28) //
#define SPI_PUSHR_EOQ (uint32_t)0x08000000 //
#define SPI_PUSHR_CTCNT (uint32_t)0x04000000 //
#define SPI_PUSHR_PCS(n) (((n) & 31) << 16) //
#define SPI0_PUSHR_SLAVE *(volatile uint32_t *)0x4002C034 // DSPI PUSH TX FIFO Register In Slave Mode
#define SPI0_POPR *(volatile uint32_t *)0x4002C038 // DSPI POP RX FIFO Register
#define SPI0_TXFR0 *(volatile uint32_t *)0x4002C03C // DSPI Transmit FIFO Registers
#define SPI0_TXFR1 *(volatile uint32_t *)0x4002C040 // DSPI Transmit FIFO Registers
#define SPI0_TXFR2 *(volatile uint32_t *)0x4002C044 // DSPI Transmit FIFO Registers
#define SPI0_TXFR3 *(volatile uint32_t *)0x4002C048 // DSPI Transmit FIFO Registers
#define SPI0_RXFR0 *(volatile uint32_t *)0x4002C07C // DSPI Receive FIFO Registers
#define SPI0_RXFR1 *(volatile uint32_t *)0x4002C080 // DSPI Receive FIFO Registers
#define SPI0_RXFR2 *(volatile uint32_t *)0x4002C084 // DSPI Receive FIFO Registers
#define SPI0_RXFR3 *(volatile uint32_t *)0x4002C088 // DSPI Receive FIFO Registers
// Chapter 44: Inter-Integrated Circuit (I2C)
#define I2C0_A1 *(volatile uint8_t *)0x40066000 // I2C Address Register 1
#define I2C0_F *(volatile uint8_t *)0x40066001 // I2C Frequency Divider register
#define I2C0_C1 *(volatile uint8_t *)0x40066002 // I2C Control Register 1
#define I2C_C1_IICEN (uint8_t)0x80 // I2C Enable
#define I2C_C1_IICIE (uint8_t)0x40 // I2C Interrupt Enable
#define I2C_C1_MST (uint8_t)0x20 // Master Mode Select
#define I2C_C1_TX (uint8_t)0x10 // Transmit Mode Select
#define I2C_C1_TXAK (uint8_t)0x08 // Transmit Acknowledge Enable
#define I2C_C1_RSTA (uint8_t)0x04 // Repeat START
#define I2C_C1_WUEN (uint8_t)0x02 // Wakeup Enable
#define I2C_C1_DMAEN (uint8_t)0x01 // DMA Enable
#define I2C0_S *(volatile uint8_t *)0x40066003 // I2C Status register
#define I2C_S_TCF (uint8_t)0x80 // Transfer Complete Flag
#define I2C_S_IAAS (uint8_t)0x40 // Addressed As A Slave
#define I2C_S_BUSY (uint8_t)0x20 // Bus Busy
#define I2C_S_ARBL (uint8_t)0x10 // Arbitration Lost
#define I2C_S_RAM (uint8_t)0x08 // Range Address Match
#define I2C_S_SRW (uint8_t)0x04 // Slave Read/Write
#define I2C_S_IICIF (uint8_t)0x02 // Interrupt Flag
#define I2C_S_RXAK (uint8_t)0x01 // Receive Acknowledge
#define I2C0_D *(volatile uint8_t *)0x40066004 // I2C Data I/O register
#define I2C0_C2 *(volatile uint8_t *)0x40066005 // I2C Control Register 2
#define I2C_C2_GCAEN (uint8_t)0x80 // General Call Address Enable
#define I2C_C2_ADEXT (uint8_t)0x40 // Address Extension
#define I2C_C2_HDRS (uint8_t)0x20 // High Drive Select
#define I2C_C2_SBRC (uint8_t)0x10 // Slave Baud Rate Control
#define I2C_C2_RMEN (uint8_t)0x08 // Range Address Matching Enable
#define I2C_C2_AD(n) ((n) & 7) // Slave Address, upper 3 bits
#define I2C0_FLT *(volatile uint8_t *)0x40066006 // I2C Programmable Input Glitch Filter register
#define I2C0_RA *(volatile uint8_t *)0x40066007 // I2C Range Address register
#define I2C0_SMB *(volatile uint8_t *)0x40066008 // I2C SMBus Control and Status register
#define I2C0_A2 *(volatile uint8_t *)0x40066009 // I2C Address Register 2
#define I2C0_SLTH *(volatile uint8_t *)0x4006600A // I2C SCL Low Timeout Register High
#define I2C0_SLTL *(volatile uint8_t *)0x4006600B // I2C SCL Low Timeout Register Low
// Chapter 45: Universal Asynchronous Receiver/Transmitter (UART)
#define UART0_BDH *(volatile uint8_t *)0x4006A000 // UART Baud Rate Registers: High
#define UART0_BDL *(volatile uint8_t *)0x4006A001 // UART Baud Rate Registers: Low
#define UART0_C1 *(volatile uint8_t *)0x4006A002 // UART Control Register 1
#define UART_C1_LOOPS (uint8_t)0x80 // When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input
#define UART_C1_UARTSWAI (uint8_t)0x40 // UART Stops in Wait Mode
#define UART_C1_RSRC (uint8_t)0x20 // When LOOPS is set, the RSRC field determines the source for the receiver shift register input
#define UART_C1_M (uint8_t)0x10 // 9-bit or 8-bit Mode Select
#define UART_C1_WAKE (uint8_t)0x08 // Determines which condition wakes the UART
#define UART_C1_ILT (uint8_t)0x04 // Idle Line Type Select
#define UART_C1_PE (uint8_t)0x02 // Parity Enable
#define UART_C1_PT (uint8_t)0x01 // Parity Type, 0=even, 1=odd
#define UART0_C2 *(volatile uint8_t *)0x4006A003 // UART Control Register 2
#define UART_C2_TIE (uint8_t)0x80 // Transmitter Interrupt or DMA Transfer Enable.
#define UART_C2_TCIE (uint8_t)0x40 // Transmission Complete Interrupt Enable
#define UART_C2_RIE (uint8_t)0x20 // Receiver Full Interrupt or DMA Transfer Enable
#define UART_C2_ILIE (uint8_t)0x10 // Idle Line Interrupt Enable
#define UART_C2_TE (uint8_t)0x08 // Transmitter Enable
#define UART_C2_RE (uint8_t)0x04 // Receiver Enable
#define UART_C2_RWU (uint8_t)0x02 // Receiver Wakeup Control
#define UART_C2_SBK (uint8_t)0x01 // Send Break
#define UART0_S1 *(volatile uint8_t *)0x4006A004 // UART Status Register 1
#define UART_S1_TDRE (uint8_t)0x80 // Transmit Data Register Empty Flag
#define UART_S1_TC (uint8_t)0x40 // Transmit Complete Flag
#define UART_S1_RDRF (uint8_t)0x20 // Receive Data Register Full Flag
#define UART_S1_IDLE (uint8_t)0x10 // Idle Line Flag
#define UART_S1_OR (uint8_t)0x08 // Receiver Overrun Flag
#define UART_S1_NF (uint8_t)0x04 // Noise Flag
#define UART_S1_FE (uint8_t)0x02 // Framing Error Flag
#define UART_S1_PF (uint8_t)0x01 // Parity Error Flag
#define UART0_S2 *(volatile uint8_t *)0x4006A005 // UART Status Register 2
#define UART0_C3 *(volatile uint8_t *)0x4006A006 // UART Control Register 3
#define UART0_D *(volatile uint8_t *)0x4006A007 // UART Data Register
#define UART0_MA1 *(volatile uint8_t *)0x4006A008 // UART Match Address Registers 1
#define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2
#define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4
#define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5
#define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register
#define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register
#define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register
#define UART0_PFIFO *(volatile uint8_t *)0x4006A010 // UART FIFO Parameters
#define UART_PFIFO_TXFE (uint8_t)0x80
#define UART_PFIFO_RXFE (uint8_t)0x08
#define UART0_CFIFO *(volatile uint8_t *)0x4006A011 // UART FIFO Control Register
#define UART_CFIFO_TXFLUSH (uint8_t)0x80 //
#define UART_CFIFO_RXFLUSH (uint8_t)0x40 //
#define UART_CFIFO_RXOFE (uint8_t)0x04 //
#define UART_CFIFO_TXOFE (uint8_t)0x02 //
#define UART_CFIFO_RXUFE (uint8_t)0x01 //
#define UART0_SFIFO *(volatile uint8_t *)0x4006A012 // UART FIFO Status Register
#define UART_SFIFO_TXEMPT (uint8_t)0x80
#define UART_SFIFO_RXEMPT (uint8_t)0x40
#define UART_SFIFO_RXOF (uint8_t)0x04
#define UART_SFIFO_TXOF (uint8_t)0x02
#define UART_SFIFO_RXUF (uint8_t)0x01
#define UART0_TWFIFO *(volatile uint8_t *)0x4006A013 // UART FIFO Transmit Watermark
#define UART0_TCFIFO *(volatile uint8_t *)0x4006A014 // UART FIFO Transmit Count
#define UART0_RWFIFO *(volatile uint8_t *)0x4006A015 // UART FIFO Receive Watermark
#define UART0_RCFIFO *(volatile uint8_t *)0x4006A016 // UART FIFO Receive Count
#define UART0_C7816 *(volatile uint8_t *)0x4006A018 // UART 7816 Control Register
#define UART0_IE7816 *(volatile uint8_t *)0x4006A019 // UART 7816 Interrupt Enable Register
#define UART0_IS7816 *(volatile uint8_t *)0x4006A01A // UART 7816 Interrupt Status Register
#define UART0_WP7816T0 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register
#define UART0_WP7816T1 *(volatile uint8_t *)0x4006A01B // UART 7816 Wait Parameter Register
#define UART0_WN7816 *(volatile uint8_t *)0x4006A01C // UART 7816 Wait N Register
#define UART0_WF7816 *(volatile uint8_t *)0x4006A01D // UART 7816 Wait FD Register
#define UART0_ET7816 *(volatile uint8_t *)0x4006A01E // UART 7816 Error Threshold Register
#define UART0_TL7816 *(volatile uint8_t *)0x4006A01F // UART 7816 Transmit Length Register
#define UART0_C6 *(volatile uint8_t *)0x4006A021 // UART CEA709.1-B Control Register 6
#define UART0_PCTH *(volatile uint8_t *)0x4006A022 // UART CEA709.1-B Packet Cycle Time Counter High
#define UART0_PCTL *(volatile uint8_t *)0x4006A023 // UART CEA709.1-B Packet Cycle Time Counter Low
#define UART0_B1T *(volatile uint8_t *)0x4006A024 // UART CEA709.1-B Beta1 Timer
#define UART0_SDTH *(volatile uint8_t *)0x4006A025 // UART CEA709.1-B Secondary Delay Timer High
#define UART0_SDTL *(volatile uint8_t *)0x4006A026 // UART CEA709.1-B Secondary Delay Timer Low
#define UART0_PRE *(volatile uint8_t *)0x4006A027 // UART CEA709.1-B Preamble
#define UART0_TPL *(volatile uint8_t *)0x4006A028 // UART CEA709.1-B Transmit Packet Length
#define UART0_IE *(volatile uint8_t *)0x4006A029 // UART CEA709.1-B Interrupt Enable Register
#define UART0_WB *(volatile uint8_t *)0x4006A02A // UART CEA709.1-B WBASE
#define UART0_S3 *(volatile uint8_t *)0x4006A02B // UART CEA709.1-B Status Register
#define UART0_S4 *(volatile uint8_t *)0x4006A02C // UART CEA709.1-B Status Register
#define UART0_RPL *(volatile uint8_t *)0x4006A02D // UART CEA709.1-B Received Packet Length
#define UART0_RPREL *(volatile uint8_t *)0x4006A02E // UART CEA709.1-B Received Preamble Length
#define UART0_CPW *(volatile uint8_t *)0x4006A02F // UART CEA709.1-B Collision Pulse Width
#define UART0_RIDT *(volatile uint8_t *)0x4006A030 // UART CEA709.1-B Receive Indeterminate Time
#define UART0_TIDT *(volatile uint8_t *)0x4006A031 // UART CEA709.1-B Transmit Indeterminate Time
#define UART1_BDH *(volatile uint8_t *)0x4006B000 // UART Baud Rate Registers: High
#define UART1_BDL *(volatile uint8_t *)0x4006B001 // UART Baud Rate Registers: Low
#define UART1_C1 *(volatile uint8_t *)0x4006B002 // UART Control Register 1
#define UART1_C2 *(volatile uint8_t *)0x4006B003 // UART Control Register 2
#define UART1_S1 *(volatile uint8_t *)0x4006B004 // UART Status Register 1
#define UART1_S2 *(volatile uint8_t *)0x4006B005 // UART Status Register 2
#define UART1_C3 *(volatile uint8_t *)0x4006B006 // UART Control Register 3
#define UART1_D *(volatile uint8_t *)0x4006B007 // UART Data Register
#define UART1_MA1 *(volatile uint8_t *)0x4006B008 // UART Match Address Registers 1
#define UART1_MA2 *(volatile uint8_t *)0x4006B009 // UART Match Address Registers 2
#define UART1_C4 *(volatile uint8_t *)0x4006B00A // UART Control Register 4
#define UART1_C5 *(volatile uint8_t *)0x4006B00B // UART Control Register 5
#define UART1_ED *(volatile uint8_t *)0x4006B00C // UART Extended Data Register
#define UART1_MODEM *(volatile uint8_t *)0x4006B00D // UART Modem Register
#define UART1_IR *(volatile uint8_t *)0x4006B00E // UART Infrared Register
#define UART1_PFIFO *(volatile uint8_t *)0x4006B010 // UART FIFO Parameters
#define UART1_CFIFO *(volatile uint8_t *)0x4006B011 // UART FIFO Control Register
#define UART1_SFIFO *(volatile uint8_t *)0x4006B012 // UART FIFO Status Register
#define UART1_TWFIFO *(volatile uint8_t *)0x4006B013 // UART FIFO Transmit Watermark
#define UART1_TCFIFO *(volatile uint8_t *)0x4006B014 // UART FIFO Transmit Count
#define UART1_RWFIFO *(volatile uint8_t *)0x4006B015 // UART FIFO Receive Watermark
#define UART1_RCFIFO *(volatile uint8_t *)0x4006B016 // UART FIFO Receive Count
#define UART1_C7816 *(volatile uint8_t *)0x4006B018 // UART 7816 Control Register
#define UART1_IE7816 *(volatile uint8_t *)0x4006B019 // UART 7816 Interrupt Enable Register
#define UART1_IS7816 *(volatile uint8_t *)0x4006B01A // UART 7816 Interrupt Status Register
#define UART1_WP7816T0 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register
#define UART1_WP7816T1 *(volatile uint8_t *)0x4006B01B // UART 7816 Wait Parameter Register
#define UART1_WN7816 *(volatile uint8_t *)0x4006B01C // UART 7816 Wait N Register
#define UART1_WF7816 *(volatile uint8_t *)0x4006B01D // UART 7816 Wait FD Register
#define UART1_ET7816 *(volatile uint8_t *)0x4006B01E // UART 7816 Error Threshold Register
#define UART1_TL7816 *(volatile uint8_t *)0x4006B01F // UART 7816 Transmit Length Register
#define UART1_C6 *(volatile uint8_t *)0x4006B021 // UART CEA709.1-B Control Register 6
#define UART1_PCTH *(volatile uint8_t *)0x4006B022 // UART CEA709.1-B Packet Cycle Time Counter High
#define UART1_PCTL *(volatile uint8_t *)0x4006B023 // UART CEA709.1-B Packet Cycle Time Counter Low
#define UART1_B1T *(volatile uint8_t *)0x4006B024 // UART CEA709.1-B Beta1 Timer
#define UART1_SDTH *(volatile uint8_t *)0x4006B025 // UART CEA709.1-B Secondary Delay Timer High
#define UART1_SDTL *(volatile uint8_t *)0x4006B026 // UART CEA709.1-B Secondary Delay Timer Low
#define UART1_PRE *(volatile uint8_t *)0x4006B027 // UART CEA709.1-B Preamble
#define UART1_TPL *(volatile uint8_t *)0x4006B028 // UART CEA709.1-B Transmit Packet Length
#define UART1_IE *(volatile uint8_t *)0x4006B029 // UART CEA709.1-B Interrupt Enable Register
#define UART1_WB *(volatile uint8_t *)0x4006B02A // UART CEA709.1-B WBASE
#define UART1_S3 *(volatile uint8_t *)0x4006B02B // UART CEA709.1-B Status Register
#define UART1_S4 *(volatile uint8_t *)0x4006B02C // UART CEA709.1-B Status Register
#define UART1_RPL *(volatile uint8_t *)0x4006B02D // UART CEA709.1-B Received Packet Length
#define UART1_RPREL *(volatile uint8_t *)0x4006B02E // UART CEA709.1-B Received Preamble Length
#define UART1_CPW *(volatile uint8_t *)0x4006B02F // UART CEA709.1-B Collision Pulse Width
#define UART1_RIDT *(volatile uint8_t *)0x4006B030 // UART CEA709.1-B Receive Indeterminate Time
#define UART1_TIDT *(volatile uint8_t *)0x4006B031 // UART CEA709.1-B Transmit Indeterminate Time
#define UART2_BDH *(volatile uint8_t *)0x4006C000 // UART Baud Rate Registers: High
#define UART2_BDL *(volatile uint8_t *)0x4006C001 // UART Baud Rate Registers: Low
#define UART2_C1 *(volatile uint8_t *)0x4006C002 // UART Control Register 1
#define UART2_C2 *(volatile uint8_t *)0x4006C003 // UART Control Register 2
#define UART2_S1 *(volatile uint8_t *)0x4006C004 // UART Status Register 1
#define UART2_S2 *(volatile uint8_t *)0x4006C005 // UART Status Register 2
#define UART2_C3 *(volatile uint8_t *)0x4006C006 // UART Control Register 3
#define UART2_D *(volatile uint8_t *)0x4006C007 // UART Data Register
#define UART2_MA1 *(volatile uint8_t *)0x4006C008 // UART Match Address Registers 1
#define UART2_MA2 *(volatile uint8_t *)0x4006C009 // UART Match Address Registers 2
#define UART2_C4 *(volatile uint8_t *)0x4006C00A // UART Control Register 4
#define UART2_C5 *(volatile uint8_t *)0x4006C00B // UART Control Register 5
#define UART2_ED *(volatile uint8_t *)0x4006C00C // UART Extended Data Register
#define UART2_MODEM *(volatile uint8_t *)0x4006C00D // UART Modem Register
#define UART2_IR *(volatile uint8_t *)0x4006C00E // UART Infrared Register
#define UART2_PFIFO *(volatile uint8_t *)0x4006C010 // UART FIFO Parameters
#define UART2_CFIFO *(volatile uint8_t *)0x4006C011 // UART FIFO Control Register
#define UART2_SFIFO *(volatile uint8_t *)0x4006C012 // UART FIFO Status Register
#define UART2_TWFIFO *(volatile uint8_t *)0x4006C013 // UART FIFO Transmit Watermark
#define UART2_TCFIFO *(volatile uint8_t *)0x4006C014 // UART FIFO Transmit Count
#define UART2_RWFIFO *(volatile uint8_t *)0x4006C015 // UART FIFO Receive Watermark
#define UART2_RCFIFO *(volatile uint8_t *)0x4006C016 // UART FIFO Receive Count
#define UART2_C7816 *(volatile uint8_t *)0x4006C018 // UART 7816 Control Register
#define UART2_IE7816 *(volatile uint8_t *)0x4006C019 // UART 7816 Interrupt Enable Register
#define UART2_IS7816 *(volatile uint8_t *)0x4006C01A // UART 7816 Interrupt Status Register
#define UART2_WP7816T0 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register
#define UART2_WP7816T1 *(volatile uint8_t *)0x4006C01B // UART 7816 Wait Parameter Register
#define UART2_WN7816 *(volatile uint8_t *)0x4006C01C // UART 7816 Wait N Register
#define UART2_WF7816 *(volatile uint8_t *)0x4006C01D // UART 7816 Wait FD Register
#define UART2_ET7816 *(volatile uint8_t *)0x4006C01E // UART 7816 Error Threshold Register
#define UART2_TL7816 *(volatile uint8_t *)0x4006C01F // UART 7816 Transmit Length Register
#define UART2_C6 *(volatile uint8_t *)0x4006C021 // UART CEA709.1-B Control Register 6
#define UART2_PCTH *(volatile uint8_t *)0x4006C022 // UART CEA709.1-B Packet Cycle Time Counter High
#define UART2_PCTL *(volatile uint8_t *)0x4006C023 // UART CEA709.1-B Packet Cycle Time Counter Low
#define UART2_B1T *(volatile uint8_t *)0x4006C024 // UART CEA709.1-B Beta1 Timer
#define UART2_SDTH *(volatile uint8_t *)0x4006C025 // UART CEA709.1-B Secondary Delay Timer High
#define UART2_SDTL *(volatile uint8_t *)0x4006C026 // UART CEA709.1-B Secondary Delay Timer Low
#define UART2_PRE *(volatile uint8_t *)0x4006C027 // UART CEA709.1-B Preamble
#define UART2_TPL *(volatile uint8_t *)0x4006C028 // UART CEA709.1-B Transmit Packet Length
#define UART2_IE *(volatile uint8_t *)0x4006C029 // UART CEA709.1-B Interrupt Enable Register
#define UART2_WB *(volatile uint8_t *)0x4006C02A // UART CEA709.1-B WBASE
#define UART2_S3 *(volatile uint8_t *)0x4006C02B // UART CEA709.1-B Status Register
#define UART2_S4 *(volatile uint8_t *)0x4006C02C // UART CEA709.1-B Status Register
#define UART2_RPL *(volatile uint8_t *)0x4006C02D // UART CEA709.1-B Received Packet Length
#define UART2_RPREL *(volatile uint8_t *)0x4006C02E // UART CEA709.1-B Received Preamble Length
#define UART2_CPW *(volatile uint8_t *)0x4006C02F // UART CEA709.1-B Collision Pulse Width
#define UART2_RIDT *(volatile uint8_t *)0x4006C030 // UART CEA709.1-B Receive Indeterminate Time
#define UART2_TIDT *(volatile uint8_t *)0x4006C031 // UART CEA709.1-B Transmit Indeterminate Time
// Chapter 46: Synchronous Audio Interface (SAI)
#define I2S0_TCSR *(volatile uint32_t *)0x4002F000 // SAI Transmit Control Register
#define I2S0_TCR1 *(volatile uint32_t *)0x4002F004 // SAI Transmit Configuration 1 Register
#define I2S0_TCR2 *(volatile uint32_t *)0x4002F008 // SAI Transmit Configuration 2 Register
#define I2S0_TCR3 *(volatile uint32_t *)0x4002F00C // SAI Transmit Configuration 3 Register
#define I2S0_TCR4 *(volatile uint32_t *)0x4002F010 // SAI Transmit Configuration 4 Register
#define I2S0_TCR5 *(volatile uint32_t *)0x4002F014 // SAI Transmit Configuration 5 Register
#define I2S0_TDR0 *(volatile uint32_t *)0x4002F020 // SAI Transmit Data Register
#define I2S0_TFR0 *(volatile uint32_t *)0x4002F040 // SAI Transmit FIFO Register
#define I2S0_TMR *(volatile uint32_t *)0x4002F060 // SAI Transmit Mask Register
#define I2S0_RCSR *(volatile uint32_t *)0x4002F080 // SAI Receive Control Register
#define I2S0_RCR1 *(volatile uint32_t *)0x4002F084 // SAI Receive Configuration 1 Register
#define I2S0_RCR2 *(volatile uint32_t *)0x4002F088 // SAI Receive Configuration 2 Register
#define I2S0_RCR3 *(volatile uint32_t *)0x4002F08C // SAI Receive Configuration 3 Register
#define I2S0_RCR4 *(volatile uint32_t *)0x4002F090 // SAI Receive Configuration 4 Register
#define I2S0_RCR5 *(volatile uint32_t *)0x4002F094 // SAI Receive Configuration 5 Register
#define I2S0_RDR0 *(volatile uint32_t *)0x4002F0A0 // SAI Receive Data Register
#define I2S0_RFR0 *(volatile uint32_t *)0x4002F0C0 // SAI Receive FIFO Register
#define I2S0_RMR *(volatile uint32_t *)0x4002F0E0 // SAI Receive Mask Register
#define I2S0_MCR *(volatile uint32_t *)0x4002F100 // SAI MCLK Control Register
#define I2S0_MDR *(volatile uint32_t *)0x4002F104 // SAI MCLK Divide Register
// Chapter 47: General-Purpose Input/Output (GPIO)
#define GPIOA_PDOR *(volatile uint32_t *)0x400FF000 // Port Data Output Register
#define GPIOA_PSOR *(volatile uint32_t *)0x400FF004 // Port Set Output Register
#define GPIOA_PCOR *(volatile uint32_t *)0x400FF008 // Port Clear Output Register
#define GPIOA_PTOR *(volatile uint32_t *)0x400FF00C // Port Toggle Output Register
#define GPIOA_PDIR *(volatile uint32_t *)0x400FF010 // Port Data Input Register
#define GPIOA_PDDR *(volatile uint32_t *)0x400FF014 // Port Data Direction Register
#define GPIOB_PDOR *(volatile uint32_t *)0x400FF040 // Port Data Output Register
#define GPIOB_PSOR *(volatile uint32_t *)0x400FF044 // Port Set Output Register
#define GPIOB_PCOR *(volatile uint32_t *)0x400FF048 // Port Clear Output Register
#define GPIOB_PTOR *(volatile uint32_t *)0x400FF04C // Port Toggle Output Register
#define GPIOB_PDIR *(volatile uint32_t *)0x400FF050 // Port Data Input Register
#define GPIOB_PDDR *(volatile uint32_t *)0x400FF054 // Port Data Direction Register
#define GPIOC_PDOR *(volatile uint32_t *)0x400FF080 // Port Data Output Register
#define GPIOC_PSOR *(volatile uint32_t *)0x400FF084 // Port Set Output Register
#define GPIOC_PCOR *(volatile uint32_t *)0x400FF088 // Port Clear Output Register
#define GPIOC_PTOR *(volatile uint32_t *)0x400FF08C // Port Toggle Output Register
#define GPIOC_PDIR *(volatile uint32_t *)0x400FF090 // Port Data Input Register
#define GPIOC_PDDR *(volatile uint32_t *)0x400FF094 // Port Data Direction Register
#define GPIOD_PDOR *(volatile uint32_t *)0x400FF0C0 // Port Data Output Register
#define GPIOD_PSOR *(volatile uint32_t *)0x400FF0C4 // Port Set Output Register
#define GPIOD_PCOR *(volatile uint32_t *)0x400FF0C8 // Port Clear Output Register
#define GPIOD_PTOR *(volatile uint32_t *)0x400FF0CC // Port Toggle Output Register
#define GPIOD_PDIR *(volatile uint32_t *)0x400FF0D0 // Port Data Input Register
#define GPIOD_PDDR *(volatile uint32_t *)0x400FF0D4 // Port Data Direction Register
#define GPIOE_PDOR *(volatile uint32_t *)0x400FF100 // Port Data Output Register
#define GPIOE_PSOR *(volatile uint32_t *)0x400FF104 // Port Set Output Register
#define GPIOE_PCOR *(volatile uint32_t *)0x400FF108 // Port Clear Output Register
#define GPIOE_PTOR *(volatile uint32_t *)0x400FF10C // Port Toggle Output Register
#define GPIOE_PDIR *(volatile uint32_t *)0x400FF110 // Port Data Input Register
#define GPIOE_PDDR *(volatile uint32_t *)0x400FF114 // Port Data Direction Register
// Chapter 48: Touch sense input (TSI)
#define TSI0_GENCS *(volatile uint32_t *)0x40045000 // General Control and Status Register
#define TSI_GENCS_LPCLKS (uint32_t)0x10000000 //
#define TSI_GENCS_LPSCNITV(n) (((n) & 15) << 24) //
#define TSI_GENCS_NSCN(n) (((n) & 31) << 19) //
#define TSI_GENCS_PS(n) (((n) & 7) << 16) //
#define TSI_GENCS_EOSF (uint32_t)0x00008000 //
#define TSI_GENCS_OUTRGF (uint32_t)0x00004000 //
#define TSI_GENCS_EXTERF (uint32_t)0x00002000 //
#define TSI_GENCS_OVRF (uint32_t)0x00001000 //
#define TSI_GENCS_SCNIP (uint32_t)0x00000200 //
#define TSI_GENCS_SWTS (uint32_t)0x00000100 //
#define TSI_GENCS_TSIEN (uint32_t)0x00000080 //
#define TSI_GENCS_TSIIE (uint32_t)0x00000040 //
#define TSI_GENCS_ERIE (uint32_t)0x00000020 //
#define TSI_GENCS_ESOR (uint32_t)0x00000010 //
#define TSI_GENCS_STM (uint32_t)0x00000002 //
#define TSI_GENCS_STPE (uint32_t)0x00000001 //
#define TSI0_SCANC *(volatile uint32_t *)0x40045004 // SCAN Control Register
#define TSI_SCANC_REFCHRG(n) (((n) & 15) << 24) //
#define TSI_SCANC_EXTCHRG(n) (((n) & 7) << 16) //
#define TSI_SCANC_SMOD(n) (((n) & 255) << 8) //
#define TSI_SCANC_AMCLKS(n) (((n) & 3) << 3) //
#define TSI_SCANC_AMPSC(n) (((n) & 7) << 0) //
#define TSI0_PEN *(volatile uint32_t *)0x40045008 // Pin Enable Register
#define TSI0_WUCNTR *(volatile uint32_t *)0x4004500C // Wake-Up Channel Counter Register
#define TSI0_CNTR1 *(volatile uint32_t *)0x40045100 // Counter Register
#define TSI0_CNTR3 *(volatile uint32_t *)0x40045104 // Counter Register
#define TSI0_CNTR5 *(volatile uint32_t *)0x40045108 // Counter Register
#define TSI0_CNTR7 *(volatile uint32_t *)0x4004510C // Counter Register
#define TSI0_CNTR9 *(volatile uint32_t *)0x40045110 // Counter Register
#define TSI0_CNTR11 *(volatile uint32_t *)0x40045114 // Counter Register
#define TSI0_CNTR13 *(volatile uint32_t *)0x40045118 // Counter Register
#define TSI0_CNTR15 *(volatile uint32_t *)0x4004511C // Counter Register
#define TSI0_THRESHOLD *(volatile uint32_t *)0x40045120 // Low Power Channel Threshold Register
// Nested Vectored Interrupt Controller, Table 3-4 & ARMv7 ref, appendix B3.4 (page 750)
#define NVIC_ENABLE_IRQ(n) (*((volatile uint32_t *)0xE000E100 + (n >> 5)) = (1 << (n & 31)))
#define NVIC_DISABLE_IRQ(n) (*((volatile uint32_t *)0xE000E180 + (n >> 5)) = (1 << (n & 31)))
#define NVIC_SET_PENDING(n) (*((volatile uint32_t *)0xE000E200 + (n >> 5)) = (1 << (n & 31)))
#define NVIC_CLEAR_PENDING(n) (*((volatile uint32_t *)0xE000E280 + (n >> 5)) = (1 << (n & 31)))
#define NVIC_ISER0 *(volatile uint32_t *)0xE000E100
#define NVIC_ISER1 *(volatile uint32_t *)0xE000E104
#define NVIC_ICER0 *(volatile uint32_t *)0xE000E180
#define NVIC_ICER1 *(volatile uint32_t *)0xE000E184
//#define NVIC_SET_PRIORITY(n, p)
#define IRQ_DMA_CH0 0
#define IRQ_DMA_CH1 1
#define IRQ_DMA_CH2 2
#define IRQ_DMA_CH3 3
#define IRQ_DMA_ERROR 4
#define IRQ_FTFL_COMPLETE 6
#define IRQ_FTFL_COLLISION 7
#define IRQ_LOW_VOLTAGE 8
#define IRQ_LLWU 9
#define IRQ_WDOG 10
#define IRQ_I2C0 11
#define IRQ_SPI0 12
#define IRQ_I2S0_TX 13
#define IRQ_I2S0_RX 14
#define IRQ_UART0_LON 15
#define IRQ_UART0_STATUS 16
#define IRQ_UART0_ERROR 17
#define IRQ_UART1_STATUS 18
#define IRQ_UART1_ERROR 19
#define IRQ_UART2_STATUS 20
#define IRQ_UART2_ERROR 21
#define IRQ_ADC0 22
#define IRQ_CMP0 23
#define IRQ_CMP1 24
#define IRQ_FTM0 25
#define IRQ_FTM1 26
#define IRQ_CMT 27
#define IRQ_RTC_ALARM 28
#define IRQ_RTC_SECOND 29
#define IRQ_PIT_CH0 30
#define IRQ_PIT_CH1 31
#define IRQ_PIT_CH2 32
#define IRQ_PIT_CH3 33
#define IRQ_PDB 34
#define IRQ_USBOTG 35
#define IRQ_USBDCD 36
#define IRQ_TSI 37
#define IRQ_MCG 38
#define IRQ_LPTMR 39
#define IRQ_PORTA 40
#define IRQ_PORTB 41
#define IRQ_PORTC 42
#define IRQ_PORTD 43
#define IRQ_PORTE 44
#define IRQ_SOFTWARE 45
#define __disable_irq() asm volatile("CPSID i");
#define __enable_irq() asm volatile("CPSIE i");
// System Control Space (SCS), ARMv7 ref manual, B3.2, page 708
#define SCB_CPUID *(const uint32_t *)0xE000ED00 // CPUID Base Register
#define SCB_ICSR *(volatile uint32_t *)0xE000ED04 // Interrupt Control and State
#define SCB_ICSR_PENDSTSET (uint32_t)0x04000000
#define SCB_VTOR *(volatile uint32_t *)0xE000ED08 // Vector Table Offset
#define SCB_AIRCR *(volatile uint32_t *)0xE000ED0C // Application Interrupt and Reset Control
#define SCB_SCR *(volatile uint32_t *)0xE000ED10 // System Control Register
#define SCB_CCR *(volatile uint32_t *)0xE000ED14 // Configuration and Control
#define SCB_SHPR1 *(volatile uint32_t *)0xE000ED18 // System Handler Priority Register 1
#define SCB_SHPR2 *(volatile uint32_t *)0xE000ED1C // System Handler Priority Register 2
#define SCB_SHPR3 *(volatile uint32_t *)0xE000ED20 // System Handler Priority Register 3
#define SCB_SHCSR *(volatile uint32_t *)0xE000ED24 // System Handler Control and State
#define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register
#define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status
#define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status
#define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address
#define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status
#define SYST_CSR_COUNTFLAG (uint32_t)0x00010000
#define SYST_CSR_CLKSOURCE (uint32_t)0x00000004
#define SYST_CSR_TICKINT (uint32_t)0x00000002
#define SYST_CSR_ENABLE (uint32_t)0x00000001
#define SYST_RVR *(volatile uint32_t *)0xE000E014 // SysTick Reload Value Register
#define SYST_CVR *(volatile uint32_t *)0xE000E018 // SysTick Current Value Register
#define SYST_CALIB *(const uint32_t *)0xE000E01C // SysTick Calibration Value
#define ARM_DEMCR *(volatile uint32_t *)0xE000EDFC // Debug Exception and Monitor Control
#define ARM_DEMCR_TRCENA (1 << 24) // Enable debugging & monitoring blocks
#define ARM_DWT_CTRL *(volatile uint32_t *)0xE0001000 // DWT control register
#define ARM_DWT_CTRL_CYCCNTENA (1 << 0) // Enable cycle count
#define ARM_DWT_CYCCNT *(volatile uint32_t *)0xE0001004 // Cycle count register
extern void nmi_isr(void);
extern void hard_fault_isr(void);
extern void memmanage_fault_isr(void);
extern void bus_fault_isr(void);
extern void usage_fault_isr(void);
extern void svcall_isr(void);
extern void debugmonitor_isr(void);
extern void pendablesrvreq_isr(void);
extern void systick_isr(void);
extern void dma_ch0_isr(void);
extern void dma_ch1_isr(void);
extern void dma_ch2_isr(void);
extern void dma_ch3_isr(void);
extern void dma_error_isr(void);
extern void flash_cmd_isr(void);
extern void flash_error_isr(void);
extern void low_voltage_isr(void);
extern void wakeup_isr(void);
extern void watchdog_isr(void);
extern void i2c0_isr(void);
extern void spi0_isr(void);
extern void i2s0_tx_isr(void);
extern void i2s0_rx_isr(void);
extern void uart0_lon_isr(void);
extern void uart0_status_isr(void);
extern void uart0_error_isr(void);
extern void uart1_status_isr(void);
extern void uart1_error_isr(void);
extern void uart2_status_isr(void);
extern void uart2_error_isr(void);
extern void adc0_isr(void);
extern void cmp0_isr(void);
extern void cmp1_isr(void);
extern void ftm0_isr(void);
extern void ftm1_isr(void);
extern void cmt_isr(void);
extern void rtc_alarm_isr(void);
extern void rtc_seconds_isr(void);
extern void pit0_isr(void);
extern void pit1_isr(void);
extern void pit2_isr(void);
extern void pit3_isr(void);
extern void pdb_isr(void);
extern void usb_isr(void);
extern void usb_charge_isr(void);
extern void tsi0_isr(void);
extern void mcg_isr(void);
extern void lptmr_isr(void);
extern void porta_isr(void);
extern void portb_isr(void);
extern void portc_isr(void);
extern void portd_isr(void);
extern void porte_isr(void);
extern void software_isr(void);
static inline void watchdog_refresh(void)
{
__disable_irq();
WDOG_REFRESH = 0xA602;
WDOG_REFRESH = 0xB480;
__enable_irq();
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committed
static inline void watchdog_reboot(void)
{
// Any invalid write to the WDOG registers will trigger an immediate reboot
WDOG_REFRESH = 0;
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committed
}
#ifdef __cplusplus
}
#endif
#endif