From 497134af4819241d49bbc22f1849756c7c06eb2e Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Tue, 11 Oct 2016 13:32:54 +0800
Subject: [PATCH] MLK-13307-15 imx: mx6sll: add mx6sll arm2 support
Add mx6sll lpddr3/lpddr2 arm2 support.
LCDIF/SPI/USB/PMIC supported.
LPDDR3 DDR version: 1.2
LPDDR2 DDR version: initial version.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
---
arch/arm/cpu/armv7/mx6/Kconfig | 7 +
board/freescale/mx6sll_arm2/Kconfig | 12 +
board/freescale/mx6sll_arm2/Makefile | 10 +
board/freescale/mx6sll_arm2/imximage.cfg | 125 +++++
.../freescale/mx6sll_arm2/imximage_lpddr2.cfg | 125 +++++
board/freescale/mx6sll_arm2/mx6sll_arm2.c | 523 ++++++++++++++++++
board/freescale/mx6sll_arm2/plugin.S | 273 +++++++++
configs/mx6sll_lpddr2_arm2_defconfig | 5 +
configs/mx6sll_lpddr3_arm2_defconfig | 5 +
configs/mx6sll_lpddr3_arm2_spinor_defconfig | 5 +
include/configs/mx6sll_arm2.h | 262 +++++++++
11 files changed, 1352 insertions(+)
create mode 100644 board/freescale/mx6sll_arm2/Kconfig
create mode 100644 board/freescale/mx6sll_arm2/Makefile
create mode 100644 board/freescale/mx6sll_arm2/imximage.cfg
create mode 100644 board/freescale/mx6sll_arm2/imximage_lpddr2.cfg
create mode 100644 board/freescale/mx6sll_arm2/mx6sll_arm2.c
create mode 100644 board/freescale/mx6sll_arm2/plugin.S
create mode 100644 configs/mx6sll_lpddr2_arm2_defconfig
create mode 100644 configs/mx6sll_lpddr3_arm2_defconfig
create mode 100644 configs/mx6sll_lpddr3_arm2_spinor_defconfig
create mode 100644 include/configs/mx6sll_arm2.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 23ede29c85..20bca8c29d 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -102,6 +102,12 @@ config TARGET_MX6SLEVK
select DM
select DM_THERMAL
+config TARGET_MX6SLL_ARM2
+ bool "mx6sll arm2"
+ select MX6SLL
+ select DM
+ select DM_THERMAL
+
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select MX6SX
@@ -232,6 +238,7 @@ source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sll_arm2/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
diff --git a/board/freescale/mx6sll_arm2/Kconfig b/board/freescale/mx6sll_arm2/Kconfig
new file mode 100644
index 0000000000..9865a7472a
--- /dev/null
+++ b/board/freescale/mx6sll_arm2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SLL_ARM2
+
+config SYS_BOARD
+ default "mx6sll_arm2"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6sll_arm2"
+
+endif
diff --git a/board/freescale/mx6sll_arm2/Makefile b/board/freescale/mx6sll_arm2/Makefile
new file mode 100644
index 0000000000..75a414c5a9
--- /dev/null
+++ b/board/freescale/mx6sll_arm2/Makefile
@@ -0,0 +1,10 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sll_arm2.o
+
+extra-$(CONFIG_USE_PLUGIN) := plugin.bin
+$(obj)/plugin.bin: $(obj)/plugin.o
+ $(OBJCOPY) -O binary --gap-fill 0xff $< $@
diff --git a/board/freescale/mx6sll_arm2/imximage.cfg b/board/freescale/mx6sll_arm2/imximage.cfg
new file mode 100644
index 0000000000..c39f9a1dd7
--- /dev/null
+++ b/board/freescale/mx6sll_arm2/imximage.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sll_arm2/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E0520 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x40404040
+DATA 4 0x021B0850 0x40404040
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100B22
+DATA 4 0x021B0038 0x00170778
+DATA 4 0x021B0014 0x00C700DB
+DATA 4 0x021B0018 0x00201718
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0xC4190000
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x83018030
+DATA 4 0x021B001C 0x83018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1310003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sll_arm2/imximage_lpddr2.cfg b/board/freescale/mx6sll_arm2/imximage_lpddr2.cfg
new file mode 100644
index 0000000000..16adbfb3e4
--- /dev/null
+++ b/board/freescale/mx6sll_arm2/imximage_lpddr2.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sll_arm2/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x40404040
+DATA 4 0x021B0850 0x40404040
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100A82
+DATA 4 0x021B0038 0x00170777
+DATA 4 0x021B0014 0x00C70093
+DATA 4 0x021B0018 0x00201708
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0xC3110000
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x82018030
+DATA 4 0x021B001C 0x82018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sll_arm2/mx6sll_arm2.c b/board/freescale/mx6sll_arm2/mx6sll_arm2.c
new file mode 100644
index 0000000000..a8f40daaf7
--- /dev/null
+++ b/board/freescale/mx6sll_arm2/mx6sll_arm2.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-mx6/clock.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <mxsfb.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+#include <asm/imx-common/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EPD */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ /* conflict with usb_otg2_pwr */
+ .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C1_SCL__GPIO3_IO12 | PC,
+ .gp = IMX_GPIO_NR(3, 12),
+ },
+ .sda = {
+ /* conflict with usb_otg2_oc */
+ .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C1_SDA__GPIO3_IO13 | PC,
+ .gp = IMX_GPIO_NR(3, 13),
+ },
+};
+
+/* I2C2 for LCD and ADV */
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_I2C2_SCL__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_I2C2_SCL__GPIO3_IO14 | PC,
+ .gp = IMX_GPIO_NR(3, 14),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_I2C2_SDA__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_I2C2_SDA__GPIO3_IO15 | PC,
+ .gp = IMX_GPIO_NR(3, 15),
+ },
+};
+
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const led_pads[] = {
+ MX6_PAD_EPDC_VCOM1__GPIO2_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+/* 8bit SD1 */
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA4__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA5__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA6__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA7__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_KEY_ROW7__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* WP */
+ MX6_PAD_GPIO4_IO22__SD1_WP | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* EMMC */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* DQS */
+ MX6_PAD_GPIO4_IO21__SD2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RST_B */
+ MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* Wifi SD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD */
+ MX6_PAD_REF_CLK_32K__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+
+ imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+ {USDHC1_BASE_ADDR, 0, 8, 1},
+ {USDHC2_BASE_ADDR, 0, 8},
+ {USDHC3_BASE_ADDR, 0, 4},
+};
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 27)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+ return devno;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = 1;
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ * mmc2 USDHC3
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+ return 0;
+ }
+
+ if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+static struct pmic *pfuze;
+int power_init_board(void)
+{
+ int ret;
+ u32 rev_id, value;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ pfuze = pmic_get("PFUZE100");
+ if (!pfuze)
+ return -ENODEV;
+
+ ret = pmic_probe(pfuze);
+ if (ret)
+ return ret;
+
+ ret = pfuze_mode_init(pfuze, APS_PFM);
+ if (ret < 0)
+ return ret;
+
+ pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+ pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
+
+ /* set SW1AB standby volatage 0.975V */
+ pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+ value &= ~0x3f;
+ value |= PFUZE100_SW1ABC_SETP(9750);
+ pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+ value &= ~0xc0;
+ value |= 0x40;
+ pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+ /* set SW1C staby volatage 0.975V */
+ pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+ value &= ~0x3f;
+ value |= 0x1b;
+ pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+ value &= ~0xc0;
+ value |= 0x40;
+ pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+ /* CS0 */
+ MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ ARRAY_SIZE(ecspi1_pads));
+ gpio_direction_output(IMX_GPIO_NR(4, 11), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+ MX6_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA00__LCD_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA01__LCD_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA02__LCD_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA03__LCD_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA04__LCD_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA05__LCD_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA06__LCD_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA07__LCD_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA08__LCD_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA09__LCD_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* Use GPIO for Brightness adjustment, duty cycle = period */
+ MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+
+{
+ int ret;
+
+ ret = enable_lcdif_clock(dev->bus);
+ if (ret) {
+ printf("Enable LCDIF clock failed, %d\n", ret);
+ return;
+ }
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+ /* Reset the LCD */
+ gpio_direction_output(IMX_GPIO_NR(2, 19) , 0);
+ udelay(500);
+ gpio_direction_output(IMX_GPIO_NR(2, 19) , 1);
+
+ gpio_direction_output(IMX_GPIO_NR(4, 8) , 1);
+
+ /* Set Brightness to high */
+ gpio_direction_output(IMX_GPIO_NR(3, 23) , 1);
+}
+
+struct display_info_t const displays[] = {{
+ .bus = MX6SLL_LCDIF_BASE_ADDR,
+ .addr = 0,
+ .pixfmt = 24,
+ .detect = NULL,
+ .enable = do_enable_parallel_lcd,
+ .mode = {
+ .name = "MCIMX28LCD",
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29850,
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+ MX6_PAD_KEY_COL4__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW4__USB_OTG1_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+ MX6_PAD_KEY_COL5__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+int board_usb_phy_mode(int port)
+{
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
+ ARRAY_SIZE(usb_otg1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+ ARRAY_SIZE(usb_otg2_pads));
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return 1;
+ }
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ enable_uart_clk(true);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_MXC_SPI
+ setup_spinor();
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_LPDDR2
+ puts("Board: MX6SLL LPDDR2 ARM2\n");
+#else
+ puts("Board: MX6SLL LPDDR3 ARM2\n");
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/mx6sll_arm2/plugin.S b/board/freescale/mx6sll_arm2/plugin.S
new file mode 100644
index 0000000000..b3741aaf93
--- /dev/null
+++ b/board/freescale/mx6sll_arm2/plugin.S
@@ -0,0 +1,273 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sll_lpddr3_arm2_setting
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x00080000
+ str r1, [r0, #0x550]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x534]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x2AC]
+ str r1, [r0, #0x548]
+ str r1, [r0, #0x520]
+ ldr r1, =0x00020000
+ str r1, [r0, #0x530]
+ ldr r1, =0x00003030
+ str r1, [r0, #0x2B0]
+ str r1, [r0, #0x2B4]
+ str r1, [r0, #0x2B8]
+ str r1, [r0, #0x2BC]
+
+ ldr r1, =0x00020000
+ str r1, [r0, #0x540]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x544]
+ str r1, [r0, #0x54C]
+ str r1, [r0, #0x554]
+ str r1, [r0, #0x558]
+ str r1, [r0, #0x294]
+ str r1, [r0, #0x298]
+ str r1, [r0, #0x29C]
+ str r1, [r0, #0x2A0]
+
+ ldr r1, =0x00082030
+ str r1, [r0, #0x2C0]
+
+ ldr r0, =MMDC_P0_BASE_ADDR
+ ldr r1, =0x00008000
+ str r1, [r0, #0x1C]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x084700C7
+ str r1, [r0, #0x85C]
+ ldr r1, =0x00400000
+ str r1, [r0, #0x890]
+
+ ldr r1, =0x40404040
+ str r1, [r0, #0x848]
+ str r1, [r0, #0x850]
+
+ ldr r1, =0x33333333
+ str r1, [r0, #0x81C]
+ str r1, [r0, #0x820]
+ str r1, [r0, #0x824]
+ str r1, [r0, #0x828]
+
+ ldr r1, =0xf3333333
+ str r1, [r0, #0x82C]
+ str r1, [r0, #0x830]
+ str r1, [r0, #0x834]
+ str r1, [r0, #0x838]
+
+ ldr r1, =0x24922492
+ str r1, [r0, #0x8C0]
+ ldr r1, =0x00000800
+ str r1, [r0, #0x8B8]
+
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x53574333
+ str r1, [r0, #0x00C]
+ ldr r1, =0x00100B22
+ str r1, [r0, #0x010]
+ ldr r1, =0x00170778
+ str r1, [r0, #0x038]
+ ldr r1, =0x00C700DB
+ str r1, [r0, #0x014]
+ ldr r1, =0x00201718
+ str r1, [r0, #0x018]
+ ldr r1, =0x0F9F26D2
+ str r1, [r0, #0x02C]
+ ldr r1, =0x009F0E10
+ str r1, [r0, #0x030]
+ ldr r1, =0x0000005F
+ str r1, [r0, #0x040]
+ ldr r1, =0xC4190000
+ str r1, [r0, #0x000]
+ ldr r1, =0x20000000
+ str r1, [r0, #0x83C]
+
+ ldr r1, =0x003F8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x003F8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x83018030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x83018038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038038
+ str r1, [r0, #0x01C]
+
+ ldr r1, =0x00001800
+ str r1, [r0, #0x020]
+ ldr r1, =0xA1310003
+ str r1, [r0, #0x800]
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x00011006
+ str r1, [r0, #0x404]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x01C]
+.endm
+
+.macro imx6sll_lpddr2_arm2_setting
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x00080000
+ str r1, [r0, #0x550]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x534]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x2AC]
+ str r1, [r0, #0x548]
+ str r1, [r0, #0x52C]
+ ldr r1, =0x00020000
+ str r1, [r0, #0x530]
+ ldr r1, =0x00003030
+ str r1, [r0, #0x2B0]
+ str r1, [r0, #0x2B4]
+ str r1, [r0, #0x2B8]
+ str r1, [r0, #0x2BC]
+
+ ldr r1, =0x00020000
+ str r1, [r0, #0x540]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x544]
+ str r1, [r0, #0x54C]
+ str r1, [r0, #0x554]
+ str r1, [r0, #0x558]
+ str r1, [r0, #0x294]
+ str r1, [r0, #0x298]
+ str r1, [r0, #0x29C]
+ str r1, [r0, #0x2A0]
+
+ ldr r1, =0x00082030
+ str r1, [r0, #0x2C0]
+
+ ldr r0, =MMDC_P0_BASE_ADDR
+ ldr r1, =0x00008000
+ str r1, [r0, #0x1C]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x084700C7
+ str r1, [r0, #0x85C]
+ ldr r1, =0x00400000
+ str r1, [r0, #0x890]
+
+ ldr r1, =0x40404040
+ str r1, [r0, #0x848]
+ str r1, [r0, #0x850]
+
+ ldr r1, =0x33333333
+ str r1, [r0, #0x81C]
+ str r1, [r0, #0x820]
+ str r1, [r0, #0x824]
+ str r1, [r0, #0x828]
+
+ ldr r1, =0xf3333333
+ str r1, [r0, #0x82C]
+ str r1, [r0, #0x830]
+ str r1, [r0, #0x834]
+ str r1, [r0, #0x838]
+
+ ldr r1, =0x24922492
+ str r1, [r0, #0x8C0]
+ ldr r1, =0x00000800
+ str r1, [r0, #0x8B8]
+
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x53574333
+ str r1, [r0, #0x00C]
+ ldr r1, =0x00100A82
+ str r1, [r0, #0x010]
+ ldr r1, =0x00170777
+ str r1, [r0, #0x038]
+ ldr r1, =0x00C70093
+ str r1, [r0, #0x014]
+ ldr r1, =0x00201708
+ str r1, [r0, #0x018]
+ ldr r1, =0x0F9F26D2
+ str r1, [r0, #0x02C]
+ ldr r1, =0x009F0E10
+ str r1, [r0, #0x030]
+ ldr r1, =0x0000004F
+ str r1, [r0, #0x040]
+ ldr r1, =0xC3110000
+ str r1, [r0, #0x000]
+ ldr r1, =0x20000000
+ str r1, [r0, #0x83C]
+
+ ldr r1, =0x003F8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x003F8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x82018030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x82018038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038038
+ str r1, [r0, #0x01C]
+
+ ldr r1, =0x00001800
+ str r1, [r0, #0x020]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x00011006
+ str r1, [r0, #0x404]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x01C]
+.endm
+.macro imx6_clock_gating
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0xffffffff
+ str r1, [r0, #0x068]
+ str r1, [r0, #0x06c]
+ str r1, [r0, #0x070]
+ str r1, [r0, #0x074]
+ str r1, [r0, #0x078]
+ str r1, [r0, #0x07c]
+ str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_LPDDR2)
+ imx6sll_lpddr2_arm2_setting
+#else
+ imx6sll_lpddr3_arm2_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/configs/mx6sll_lpddr2_arm2_defconfig b/configs/mx6sll_lpddr2_arm2_defconfig
new file mode 100644
index 0000000000..cacb7b89c8
--- /dev/null
+++ b/configs/mx6sll_lpddr2_arm2_defconfig
@@ -0,0 +1,5 @@
+kONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage_lpddr2.cfg,LPDDR2"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLL_ARM2=y
+CONFIG_CMD_GPIO=y
diff --git a/configs/mx6sll_lpddr3_arm2_defconfig b/configs/mx6sll_lpddr3_arm2_defconfig
new file mode 100644
index 0000000000..e388336c17
--- /dev/null
+++ b/configs/mx6sll_lpddr3_arm2_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLL_ARM2=y
+CONFIG_CMD_GPIO=y
diff --git a/configs/mx6sll_lpddr3_arm2_spinor_defconfig b/configs/mx6sll_lpddr3_arm2_spinor_defconfig
new file mode 100644
index 0000000000..95d959fb56
--- /dev/null
+++ b/configs/mx6sll_lpddr3_arm2_spinor_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_arm2/imximage.cfg,SYS_BOOT_SPINOR"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLL_ARM2=y
+CONFIG_CMD_GPIO=y
diff --git a/include/configs/mx6sll_arm2.h b/include/configs/mx6sll_arm2.h
new file mode 100644
index 0000000000..526c992f14
--- /dev/null
+++ b/include/configs/mx6sll_arm2.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#undef CONFIG_CMD_SET
+
+/* uncomment for PLUGIN mode support */
+/* #define CONFIG_USE_PLUGIN */
+
+/* uncomment for SECURE mode support */
+/* #define CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+ "rdinit=/linuxrc " \
+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+ "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+ "g_mass_storage.iSerialNumber=\"\" "\
+ "\0" \
+ "initrd_addr=0x83800000\0" \
+ "initrd_high=0xffffffff\0" \
+ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS \
+ "epdc_waveform=epdc_splash.bin\0" \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sll-lpddr3-arm2.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=1\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#ifdef CONFIG_LPDDR2
+#define PHYS_SDRAM_SIZE SZ_1G
+#else
+#define PHYS_SDRAM_SIZE SZ_2G
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
+
+#ifdef CONFIG_SYS_BOOT_SPINOR
+#define CONFIG_SYS_USE_SPINOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#else
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_VIDEO
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (12 * SZ_64K)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#ifdef CONFIG_SYS_USE_SPINOR
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#define CONFIG_SF_DEFAULT_CS 0
+#endif
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+
+/*#define CONFIG_MXC_EPDC 1*/
+
+/*
+ * EPDC SPLASH SCREEN Configs
+ */
+#ifdef CONFIG_MXC_EPDC
+ /*
+ * Framebuffer and LCD
+ */
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_CMD_BMP
+ #define CONFIG_LCD
+ #define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#ifdef CONFIG_MXC_EPDC
+ #undef LCD_TEST_PATTERN
+ #define LCD_BPP LCD_MONOCHROME
+
+ #define CONFIG_WAVEFORM_BUF_SIZE 0x200000
+#endif
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#endif /* __CONFIG_H */
--
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