Timur Tabi
authored
The MPIC initialization code for Freescale e500 CPUs was not using I/O accessors, and it was not issuing a read-back to the MPIC after setting mixed mode. This may be the cause of a spurious interrupt on some systems. Signed-off-by:Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| Makefile | ||
| commproc.c | ||
| config.mk | ||
| cpu.c | ||
| cpu_init.c | ||
| ddr-gen1.c | ||
| ddr-gen2.c | ||
| ddr-gen3.c | ||
| ether_fcc.c | ||
| fdt.c | ||
| interrupts.c | ||
| mp.c | ||
| mp.h | ||
| mpc8536_serdes.c | ||
| pci.c | ||
| qe_io.c | ||
| release.S | ||
| resetvec.S | ||
| serial_scc.c | ||
| speed.c | ||
| start.S | ||
| tlb.c | ||
| traps.c | ||
| u-boot.lds | ||