- 29 Apr, 2015 40 commits
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Nitin Garg authored
Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by:Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
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Han Xu authored
add this parameter in u-boot as a temporary workaround. Signed-off-by:Han Xu <b45815@freescale.com> (cherry picked from commit f0beee980914360c8783406ef8694974467eb07b)
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Ye.Li authored
Incorrect hab_rvt addresses were used for getting HAB functions. Need to change to addresses in unified section. Signed-off-by:Ye.Li <B37916@freescale.com> (cherry picked from commit 5ae1cb9d8e7cd7babd1d7ef7f2303664a4e15c26)
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Peng Fan authored
Fix reading temperature. Signed-off-by:Peng Fan <Peng.Fan@freescale.com>
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Peng Fan authored
This patch is from commit "f2c5102bf3763d77a227c1cba7fcd49e3db53a1d". " According the latest datasheet Rev.0,2/2015, the VDDSOC_IN voltage in standby/DSM mode is 1.05V. As we use PFM mode of pFuse and this mode has 3% tolerance issue, so the standby mode voltage should be (1.05 * 1.03) = 1.0815, we use 1.10V as the minimal step is 25mV. For i.MX6sx SDB RevB boards, the VDDARM and VDDSOC use the same supply, so the DSM voltage for VDDARM also need to be updated. " Signed-off-by: -
Peng Fan authored
is_mx6dqp should be only applied for MX6 Signed-off-by: -
Peng Fan authored
We should print "MX6QP Rev1.0", but not "MX6Q Rev2.0". Signed-off-by: -
Nitin Garg authored
Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: -
Ye.Li authored
The mx7dsabresd uses new LCD TFT43AB which has 480 x 272 pixels. Update panel info for this LCD. Signed-off-by: -
Ye.Li authored
To support lower clock frequency, needs to set post divider and test divider in PLL_VIDEO. So update LCDIF clock settings function to support this feature. Signed-off-by: -
Ye.Li authored
To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7dsabresd.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Since the EPDC has pinmux conflicts with ENET and QSPI. These two modules can't work at same time. Signed-off-by: -
Ye.Li authored
To enable the EPDC feature: 1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings in mx7d_12x12_lpddr3_arm2.h 2. cd <kernel_dir>/firmware/imx 3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin 4. cp epdc_splash.bin to [FAT partition on SD card] Signed-off-by: -
Ye.Li authored
To support EPDC V2 on mx7d, update the mxc_epdc_fb.h for new registers layout. Signed-off-by: -
Ye.Li authored
Ungate the EPDC clock at system up if the EPDC is enabled Signed-off-by: -
Ye.Li authored
Add the QoS settings function which is used for EPDC Signed-off-by: -
Ye.Li authored
Change to load EPDC waveform from FAT partition and allocate waveform buffer, framebuffer and working buffer in dynamic manner not static. So many EPDC configurations are removed. To enable the EPDC feature, must define CONFIG_MXC_EPDC and CONFIG_SPLASH_SCREEN. Signed-off-by: -
Peng Fan authored
Add targets for building u-boot to support QSPI booting and NAND booting. NAND booting can't work on mx7d TO1.0 Signed-off-by: -
Ye.Li authored
Should write the bits to SDI in reverse order because of the bits will be shifted. Signed-off-by:
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Peng Fan authored
Update video settings Signed-off-by: -
Peng Fan authored
This commit 155fa9af "spi: mxc: fix sf probe when using mxc_spi" introduces "board_spi_cs_gpio" function to discard gpio in CONFIG_SF_DEFAULT_CS for spi flash. Follow this rule to make imx boards work fine. Signed-off-by:
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Peng Fan authored
This patch is to add atmel AT45DB021E spi flash support. Since this flash is different from the spi flash that we previous use such as m25p32 and spanion spi nor flashes, pieces of code are added. 1. The default page size is 264 bytes, but the mtd/spi framework can not handle such page. So we need to configure the page size from 264 to 256 bytes. Page Size command seq “Power of 2” binary page size (256 bytes)| 3Dh 2Ah 80h A6h DataFlash page size (264 bytes) | 3Dh 2Ah 80h A7h And when probe the flash, configure the flash to 256 bytes page size, if the page size is already 256bytes, just return and do not configure it again. The page size configuration times is only about 10000, so to avoid configuring it each time. 2. Add the flash params in sf_params.c. 3. This flash support 2K block erase, add this flag. 4. The status command is 0xD7, different from others. It's polling status bit is Bit 7 -> 0 Device is busy with an internal operation. -> 1 Device is ready. This patch has been tested on mx7d 19x19 ddr3 arm2 board. And tested on mx7d 12x12 lpddr3 board. All works fine. Note: Since this flash is only 256KB, we can not test spi boot on mx7d 19x19 arm2 board. If want to test this flash, open CONFIG_SYS_USE_SPINOR. Signed-off-by:
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guoyin.chen authored
boot.img includes kernel image, ramdisk img, dtb, and bootargs. All are critical for android security. Protect the whole boot.img with HAB. Signed-off-by:guoyin.chen <guoyin.chen@freescale.com> (cherry picked from commit 8a49e53c5b518677b46cada5df153306161f29ac)
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Peng Fan authored
This commit ca4113da25b42bce44a2e7998966a47352f11613 "mmc: fix OCR Polling" does not consider cmd structure, and may leave it in uninitialized state. We can directly use op_cond_response here, since until here, op_cond_response already get the OCR value from chip. Signed-off-by:
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Peng Fan authored
Add CONFIG_DEFAULT_FDT_FILE macro and PHYS_SDRAM_SIZE. Signed-off-by: -
Ye.Li authored
1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Signed-off-by:
Fugang Duan <B38611@freescale.com> Signed-off-by:
Robin Gong <b38343@freescale.com> Signed-off-by:
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Ye.Li authored
The i.MX6QP has a PRG module, need to enable its clock for using IPU. Signed-off-by:
Brown Oliver <B37094@freescale.com> Signed-off-by:
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Ye.Li authored
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: -
Ye.Li authored
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP. Signed-off-by: -
Ye.Li authored
Since i.MX6DQP has fixed the L2 cache issue, enable the double line fill feature to provide better performance. Signed-off-by: -
Ye.Li authored
Add new cpu type for i.MX6DQP and providing a dynamical detecting function. Signed-off-by:
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Fabio Estevam authored
Enable 1.8V on PHY control, so that Gigabit PHY operation can be functional. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
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Peng Fan authored
We should use CONFIG_FSL_QSPI, but not CONFIG_QSPI Signed-off-by: -
Peng Fan authored
Need to check value of spi_setup_slave and spi_setup_slave_fdt. If their return value 'bus' is NULL, there is no need to pass it to following spi_flash_probe_tail. If 'bus' is null, the original function flow is as following: spi_flash_probe |->spi_setup_slave |->spi_probe_bus_tail |->spi_flash_probe_slave |->spi_free_slave Alougth check the pointer in spi_free_slave is ok, checking the return value of spi_setup_slave and spi_setup_slave_fdt is better. Before this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! SF: Failed to set up slave data abort pc : [<fff66dcc>] lr : [<fff7628c>] reloc pc : [<87814dcc>] lr : [<8782428c>] sp : fdf4fcf0 ip : e630396c fp : fe0d0888 r10: fffa2538 r9 : fdf4feb8 r8 : 02625a00 r7 : 00000002 r6 : fff94ec0 r5 : 00000000 r4 : 9355553c r3 : 1af0593c r2 : cb3fe030 r1 : fff94eb8 r0 : e59ff018 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... " After this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! Failed to initialize SPI flash at 0:2 " No data abort using this patch. Signed-off-by: -
Peng Fan authored
Upgrade to upstream way, using power_init_board. Add pfuze300 support. Signed-off-by: -
Peng Fan authored
Add CONFIG_CMD_FASTBOOT Signed-off-by: -
Peng Fan authored
If in mmc_send_op_cond, OCR_BUSY is set in CMD1's response, then state is transfered to Ready state, and there is no need to send CMD1 again. Otherwise following CMD1 will recieve no response, or timeour error from driver such as fsl_esdhc.c. If not into Ready state in previous CMD1, then continue CMD1 command. In mmc_complete_op_cond, we use the value mmc->op_cond_response from mmc_send_op_cond, since there should be no CMD1 command between mmc_send_op_cond and mmc_complete_op_cond Before fixing this, uboot log shows: " CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:8 ARG 0x000001AA MMC_RSP_R1,5,6,7 0x18EC1504 CMD_SEND:55 ARG 0x00000000 MMC_RSP_R1,5,6,7 0x18EC1504 CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:1 ARG 0x00000000 MMC_RSP_R3,4 0x00FF8080 CMD_SEND:1 ARG 0x40300000 MMC_RSP_R3,4 0xC0FF8080 --> Already OCR_BUSY set CMD_SEND:1 ARG 0x40300000 MMC_RSP_R3,4 0x0096850A --> Failed CMD1 MMC init failed " Using this patch, this issue is fixed, emmc can be detected correctly. This issue exists on mx7dsabresd and mx7d_12x12_lpddr3_arm2 board. Upstream Patchwork: https://patchwork.ozlabs.org/patch/451775/ Signed-off-by: -
Ye.Li authored
Change QSPI FLASH vendor config from to MACRONIX, otherwise the flash device can't be recognized. Also change default sf probe parameter to 0:0 which means bus 0, cs 0. Signed-off-by:
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Ye.Li authored
Update board codes to support GPMI NAND flash. Since the GPMI NAND needs board rework, it is disabled at default. Two ways to enable GPMI NAND: 1. Define CONFIG_SYS_BOOT_NAND for NAND boot case 2. Modify the line 306 in mx7dsabresd.h from QSPI to NAND. #define CONFIG_SYS_USE_QSPI /* Enable the QSPI flash at default */ to #define CONFIG_SYS_USE_NAND /* Enable the NAND flash at default */ Signed-off-by: -
Ye.Li authored
For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init. Signed-off-by:
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Ye.Li authored
Update GPMI NAND driver and BCH head file with definitions for CONFIG_MX7 Signed-off-by:
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