diff --git a/.gitignore b/.gitignore
index 67d2cd62c06b2ad84cb13bcd98e54444e7482a54..e71f6ac474d565c2e56299e7fec62a4ddfabc996 100644
--- a/.gitignore
+++ b/.gitignore
@@ -40,6 +40,9 @@
 /errlog
 /reloc_off
 
+/include/generated/
+/lib/asm-offsets.s
+
 # stgit generated dirs
 patches-*
 .stgit-edit.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f61776e911388b77112805af43aefab55c099f6..9258cb12732f23cfa8de54ea7d02a79f7c359be8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -144,6 +144,8 @@ Dirk Eibach <eibach@gdsys.de>
 	dlvision        PPC405EP
 	gdppc440etx	PPC440EP/GR
 	intip		PPC460EX
+	io		PPC405EP
+	iocon		PPC405EP
 	neo		PPC405EP
 
 Dave Ellis <DGE@sixnetio.com>
@@ -462,10 +464,11 @@ Rune Torgersen <runet@innovsys.com>
 
 Peter Tyser <ptyser@xes-inc.com>
 
-	XPEDITE1000	PPC440GX
-	XPEDITE5170	MPC8640
-	XPEDITE5200	MPC8548
-	XPEDITE5370	MPC8572
+	xpedite1000	PPC440GX
+	xpedite5170	MPC8640
+	xpedite5200	MPC8548
+	xpedite5370	MPC8572
+	xpedite5500	P2020
 
 David Updegraff <dave@cray.com>
 
diff --git a/MAKEALL b/MAKEALL
index 51312dd5e3c87b0d0f0cb49feb00cfcd087f1fdf..c54c6e8cf95eb3bbba05fa0881d4454347309550 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -56,7 +56,7 @@ LONG_OPTS="arch:,cpu:,vendor:,soc:"
 
 # Option processing based on util-linux-2.13/getopt-parse.bash
 
-# Note that we use `"$@"' to let each command-line parameter expand to a 
+# Note that we use `"$@"' to let each command-line parameter expand to a
 # separate word. The quotes around `$@' are essential!
 # We need TEMP as the `eval set --' would nuke the return value of
 # getopt.
@@ -554,9 +554,7 @@ LIST_mips_el="			\
 ## i386 Systems
 #########################################################################
 
-LIST_x86="$(boards_by_arch i386)
-	sc520_eNET	\
-"
+LIST_x86="$(boards_by_arch i386)"
 
 #########################################################################
 ## Nios-II Systems
@@ -601,39 +599,17 @@ LIST_avr32="$(boards_by_arch avr32)"
 ## Blackfin Systems
 #########################################################################
 
-LIST_blackfin="$(boards_by_arch blackfin)
-	bf527-ezkit-v2
-"
+LIST_blackfin="$(boards_by_arch blackfin)"
 
 #########################################################################
 ## SH Systems
 #########################################################################
 
-LIST_sh2="		\
-	rsk7203		\
-"
-LIST_sh3="		\
-	mpr2		\
-	ms7720se	\
-"
+LIST_sh2="$(boards_by_cpu sh2)"
+LIST_sh3="$(boards_by_cpu sh3)"
+LIST_sh4="$(boards_by_cpu sh4)"
 
-LIST_sh4="		\
-	ms7750se	\
-	ms7722se	\
-	MigoR		\
-	r7780mp		\
-	r2dplus		\
-	sh7763rdp	\
-	sh7785lcr	\
-	ap325rxa	\
-	espt		\
-"
-
-LIST_sh="		\
-	${LIST_sh2}	\
-	${LIST_sh3}	\
-	${LIST_sh4}	\
-"
+LIST_sh="$(boards_by_arch sh)"
 
 #########################################################################
 ## SPARC Systems
diff --git a/Makefile b/Makefile
index 06c71a2db86a4bf5c9713af4c9bd780b793264f1..f0c270307c389950b34d40dd554d176e5921b82b 100644
--- a/Makefile
+++ b/Makefile
@@ -22,9 +22,9 @@
 #
 
 VERSION = 2010
-PATCHLEVEL = 09
+PATCHLEVEL = 12
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -357,7 +357,7 @@ $(obj)u-boot.imx:       $(obj)u-boot.bin
 		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
 
 $(obj)u-boot.kwb:       $(obj)u-boot.bin
-		$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
+		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
 		-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
 
 $(obj)u-boot.sha1:	$(obj)u-boot.bin
@@ -372,7 +372,8 @@ GEN_UBOOT = \
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
-$(obj)u-boot:	depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
+$(obj)u-boot:	depend \
+		$(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
 		$(GEN_UBOOT)
 ifeq ($(CONFIG_KALLSYMS),y)
 		smap=`$(call SYSTEM_MAP,u-boot) | \
@@ -400,7 +401,7 @@ $(LDSCRIPT):	depend
 $(obj)u-boot.lds: $(LDSCRIPT)
 		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
 
-$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
+$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
 $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin
@@ -426,7 +427,9 @@ updater:
 
 # Explicitly make _depend in subdirs containing multiple targets to prevent
 # parallel sub-makes creating .depend files simultaneously.
-depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
+depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
+		$(obj)include/autoconf.mk \
+		$(obj)include/generated/generic-asm-offsets.h
 		for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
 			$(MAKE) -C $$dir _depend ; done
 
@@ -473,6 +476,18 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
 		sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
 	mv $@.tmp $@
 
+$(obj)include/generated/generic-asm-offsets.h:	$(obj)include/autoconf.mk.dep \
+	$(obj)lib/asm-offsets.s
+	@$(XECHO) Generating $@
+	tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@
+
+$(obj)lib/asm-offsets.s:	$(obj)include/autoconf.mk.dep \
+	$(src)lib/asm-offsets.c
+	@mkdir -p $(obj)lib
+	$(CC) -DDO_DEPS_ONLY \
+		$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+		-o $@ $(src)lib/asm-offsets.c -c -S
+
 #########################################################################
 else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
@@ -1052,7 +1067,6 @@ mx31pdk_nand_config	: unconfig
 		echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h;		\
 	else										\
 		echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h;	\
-		echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h;	\
 	fi
 	@$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31
 
@@ -1176,96 +1190,6 @@ NIOS2_GENERIC = nios2-generic
 $(NIOS2_GENERIC:%=%_config) : unconfig
 	@$(MKCONFIG) $@ nios2 nios2 nios2-generic altera
 
-#========================================================================
-# Blackfin
-#========================================================================
-
-bf527-ezkit-v2_config	: unconfig
-	@$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \
-		bf527-ezkit blackfin blackfin bf527-ezkit
-
-#========================================================================
-# SH3 (SuperH)
-#========================================================================
-
-#########################################################################
-## sh2 (Renesas SuperH)
-#########################################################################
-rsk7203_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_RSK7203 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh2 rsk7203 renesas
-
-#########################################################################
-## sh3 (Renesas SuperH)
-#########################################################################
-
-mpr2_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MPR2 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh3 mpr2
-
-ms7720se_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh3 ms7720se
-
-#########################################################################
-## sh4 (Renesas SuperH)
-#########################################################################
-
-MigoR_config :       unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 MigoR renesas
-
-ms7750se_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 ms7750se
-
-ms7722se_config :	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 ms7722se
-
-r2dplus_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 r2dplus renesas
-
-r7780mp_config: unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 r7780mp renesas
-
-sh7763rdp_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 sh7763rdp renesas
-
-sh7785lcr_32bit_config \
-sh7785lcr_config  :   unconfig
-	@mkdir -p $(obj)include
-	@mkdir -p $(obj)board/renesas/sh7785lcr
-	@echo "#define CONFIG_SH7785LCR 1" > $(obj)include/config.h
-	@if [ "$(findstring 32bit, $@)" ] ; then \
-		echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
-		echo "CONFIG_SYS_TEXT_BASE = 0x8ff80000" > \
-			$(obj)board/renesas/sh7785lcr/config.tmp ; \
-	fi
-	@$(MKCONFIG) -n $@ -a sh7785lcr sh sh4 sh7785lcr renesas
-
-ap325rxa_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 ap325rxa renesas
-
-espt_config  :   unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $@ sh sh4 espt
-
 #########################################################################
 #########################################################################
 
@@ -1296,6 +1220,7 @@ clean:
 	       $(obj)u-boot.lds						  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
 	@rm -f $(obj)include/bmp_logo.h
+	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
 	@rm -f $(ONENAND_BIN)
@@ -1319,6 +1244,7 @@ clobber:	clean
 	@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
 	@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+	@rm -fr $(obj)include/generated
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
 	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
 
diff --git a/README b/README
index a507a1f434b5e9e54f445fa05cdeeeb64098c8aa..1acf9a37eea34fe2db045b06f211c8130f654802 100644
--- a/README
+++ b/README
@@ -2364,11 +2364,11 @@ Configuration Settings:
 
 - CONFIG_ENV_MAX_ENTRIES
 
-        Maximum number of entries in the hash table that is used
-        internally to store the environment settings. The default
-        setting is supposed to be generous and should work in most
-        cases. This setting can be used to tune behaviour; see
-        lib/hashtable.c for details.
+	Maximum number of entries in the hash table that is used
+	internally to store the environment settings. The default
+	setting is supposed to be generous and should work in most
+	cases. This setting can be used to tune behaviour; see
+	lib/hashtable.c for details.
 
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
@@ -2686,7 +2686,7 @@ Low Level (hardware related) configuration options:
 		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
-		(sometimes written as (CONFIG_SYS_INIT_RAM_END -
+		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
 		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
@@ -2836,19 +2836,17 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-- CONFIG_SKIP_RELOCATE_UBOOT
+                [ARM only] If this variable is defined, then certain
+                low level initializations (like setting up the memory
+                controller) are omitted and/or U-Boot does not
+                relocate itself into RAM.
 
-		[ARM only] If these variables are defined, then
-		certain low level initializations (like setting up
-		the memory controller) are omitted and/or U-Boot does
-		not relocate itself into RAM.
-		Normally these variables MUST NOT be defined. The
-		only exception is when U-Boot is loaded (to RAM) by
-		some other boot loader or by a debugger which
-		performs these initializations itself.
+                Normally this variable MUST NOT be defined. The only
+                exception is when U-Boot is loaded (to RAM) by some
+                other boot loader or by a debugger which performs
+                these initializations itself.
 
 - CONFIG_PRELOADER
-
 		Modifies the behaviour of start.S when compiling a loader
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 21c1e33e6743be469febfdc66925e6d2e45d2904..4e165bfda4e389c9613bbfa6ac0d1ed414775420 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -33,9 +33,6 @@ STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif
 
-ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
-endif
 PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
 
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
@@ -68,9 +65,7 @@ endif
 endif
 LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
 
-ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
 # needed for relocation
 ifndef CONFIG_NAND_SPL
 PLATFORM_LDFLAGS += -pie
 endif
-endif
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 29ed065c011f8d3c972d2ad6ed8733c89de85c27..aecc943c8e980be314a38bd0582fa790da87b674 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -28,6 +28,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 .globl _start
@@ -131,14 +132,11 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
-#endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /*
  * the actual reset code
  */
@@ -217,7 +215,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -237,13 +234,13 @@ copy_loop:
 	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
 	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
 	ldr	r1, [r2, #4]
 	and	r8, r1, #0xff
-	cmp	r8, #23		/* relative fixup? */
+	cmp	r8, #23			/* relative fixup? */
 	beq	fixrel
-	cmp	r8, #2		/* absolute fixup? */
+	cmp	r8, #2			/* absolute fixup? */
 	beq	fixabs
 	/* ignore unknown type of fixup */
 	b	fixnext
@@ -260,11 +257,10 @@ fixrel:
 	add	r1, r1, r9
 fixnext:
 	str	r1, [r0]
-	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
-	ble	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -296,8 +292,8 @@ _nand_boot_ofs
 jump_2_ram:
 	ldr	r0, _board_init_r_ofs
 	adr	r1, _start
-	add	r0, r0, r1
-	add	lr, r0, r9
+	add	lr, r0, r1
+	add	lr, lr, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
@@ -315,112 +311,6 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-#ifdef CONFIG_OMAP2420H4
-       /* Copy vectors to mask ROM indirect addr */
-	adr	r0, _start		/* r0 <- current position of code   */
-		add     r0, r0, #4				/* skip reset vector			*/
-	mov	r2, #64			/* r2 <- size to copy  */
-	add	r2, r0, r2		/* r2 <- source end address	    */
-	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	bne	next			/* loop until equal */
-	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
-#endif
-	/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl  cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp	r0, r1			/* don't reloc during debug	    */
-#ifndef CONFIG_PRELOADER
-	beq	stack_setup
-#endif	/* CONFIG_PRELOADER */
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-#ifdef CONFIG_PRELOADER
-	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
-#else
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area			    */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo			    */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-#endif	/* CONFIG_PRELOADER */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	adr	r2, _start
-	ldr	r0, _bss_start_ofs	/* find start of bss segment        */
-	add	r0, r0, r2
-	ldr	r1, _bss_end_ofs	/* stop here                        */
-	add	r1, r1, r2
-	mov	r2, #0x00000000		/* clear			    */
-
-#ifndef CONFIG_PRELOADER
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-#endif
-
-	ldr	r0, _start_armboot_ofs
-	adr	r1, _start
-	add	r0, r0, r1
-	ldr	pc, r0
-
-_start_armboot_ofs:
-#ifdef CONFIG_NAND_SPL
-	.word nand_boot - _start
-#else
-#ifdef CONFIG_ONENAND_IPL
-	.word start_oneboot - _start
-#else
-	.word start_armboot - _start
-#endif /* CONFIG_ONENAND_IPL */
-#endif /* CONFIG_NAND_SPL */
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -505,13 +395,7 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
-#else
-	adr	r2, _start
-	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort stack
-#endif
 	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 
@@ -542,13 +426,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
-#else
-	adr	r13, _start			@ setup our mode stack (enter in banked mode)
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
-#endif
 
 	str	lr, [r13]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr			@ get the spsr
@@ -564,13 +442,7 @@ cpu_init_crit:
 	.macro get_bad_stack_swi
 	sub	r13, r13, #4			@ space on current stack for scratch reg.
 	str	r0, [r13]			@ save R0's value.
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
-#else
-	ldr	r0, _armboot_start		@ get data regions start
-	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
-	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ move past gbl and a couple spots for abort stack
-#endif
 	str	lr, [r0]			@ save caller lr in position 0 of saved stack
 	mrs	r0, spsr			@ get the spsr
 	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 24e5bf4fff5a4597de8e667845be905a67053f3c..f04d2688814e238bf460f5a56bef9c11a4a9b24e 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -30,6 +30,7 @@
  * Base codes by scsuh (sc.suh)
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #ifdef CONFIG_ENABLE_MMU
@@ -107,52 +108,53 @@ _TEXT_BASE:
 _TEXT_PHY_BASE:
 	.word	CONFIG_SYS_PHY_UBOOT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
  */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
 
-.globl _bss_end
-_bss_end:
-	.word _end
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
 
-.globl _datarel_start
-_datarel_start:
-	.word __datarel_start
+.globl _datarel_start_ofs
+_datarel_start_ofs:
+	.word __datarel_start - _start
 
-.globl _datarelrolocal_start
-_datarelrolocal_start:
-	.word __datarelrolocal_start
+.globl _datarelrolocal_start_ofs
+_datarelrolocal_start_ofs:
+	.word __datarelrolocal_start - _start
 
-.globl _datarellocal_start
-_datarellocal_start:
-	.word __datarellocal_start
+.globl _datarellocal_start_ofs
+_datarellocal_start_ofs:
+	.word __datarellocal_start - _start
 
-.globl _datarelro_start
-_datarelro_start:
-	.word __datarelro_start
+.globl _datarelro_start_ofs
+_datarelro_start_ofs:
+	.word __datarelro_start - _start
 
-.globl _got_start
-_got_start:
-	.word __got_start
+.globl _rel_dyn_start_ofs
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
 
-.globl _got_end
-_got_end:
-	.word __got_end
+.globl _rel_dyn_end_ofs
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+
+.globl _dynsym_start_ofs
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
 
 /*
  * the actual reset code
@@ -274,13 +276,11 @@ stack_setup:
 
 	adr	r0, _start
 	ldr	r2, _TEXT_BASE
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -288,26 +288,45 @@ copy_loop:
 	blo	copy_loop
 
 #ifndef CONFIG_PRELOADER
-	/* fix got entries */
-	ldr	r1, _TEXT_BASE		/* Text base */
-	mov	r0, r7			/* reloc addr */
-	ldr	r2, _got_start		/* addr in Flash */
-	ldr	r3, _got_end		/* addr in Flash */
-	sub	r3, r3, r1
-	add	r3, r3, r0
-	sub	r2, r2, r1
-	add	r2, r2, r0
-
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r4, [r2]
-	sub	r4, r4, r1
-	add	r4, r4, r0
-	str	r4, [r2]
-	add	r2, r2, #4
+	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9	/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23		/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2		/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r1, r9		/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 #ifdef CONFIG_ENABLE_MMU
 enable_mmu:
@@ -349,13 +368,11 @@ skip_hw_init:
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start
-	ldr	r1, _bss_end
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
 	ldr	r3, _TEXT_BASE		/* Text base */
 	mov	r4, r7			/* reloc addr */
-	sub	r0, r0, r3
 	add	r0, r0, r4
-	sub	r1, r1, r3
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
@@ -377,202 +394,20 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 _nand_boot: .word nand_boot
 #else
-	ldr	r0, _TEXT_BASE
-	ldr	r2, _board_init_r
-	sub	r2, r2, r0
-	add	r2, r2, r7	/* position from board_init_r in RAM */
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	lr, r0, r1
+	add     lr, lr, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
 	/* jump to it ... */
-	mov	lr, r2
 	mov	pc, lr
 
-_board_init_r: .word board_init_r
-#endif
-
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x3f
-	orr	r0, r0, #0xd3
-	msr	cpsr, r0
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-cpu_init_crit:
-	/*
-	 * When booting from NAND - it has definitely been a reset, so, no need
-	 * to flush caches and disable the MMU
-	 */
-#ifndef CONFIG_NAND_SPL
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-
-	/* Prepare to disable the MMU */
-	adr	r2, mmu_disable_phys
-	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
-	b	mmu_disable
-
-	.align 5
-	/* Run in a single cache-line */
-mmu_disable:
-	mcr	p15, 0, r0, c1, c0, 0
-	nop
-	nop
-	mov	pc, r2
-mmu_disable_phys:
-
-#ifdef CONFIG_DISABLE_TCM
-	/*
-	 * Disable the TCMs
-	 */
-	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
-	cmp	r0, #0
-	beq	skip_tcmdisable
-	mov	r1, #0
-	mov	r2, #1
-	tst	r0, r2
-	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
-	tst	r0, r2, LSL #16
-	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
-	/* Peri port setup */
-	ldr	r0, =CONFIG_PERIPORT_BASE
-	orr	r0, r0, #CONFIG_PERIPORT_SIZE
-	mcr	p15,0,r0,c15,c2,4
-#endif
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 */
-	bl	lowlevel_init		/* go setup pll,mux,memory */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-#ifdef CONFIG_ENABLE_MMU
-enable_mmu:
-	/* enable domain access */
-	ldr	r5, =0x0000ffff
-	mcr	p15, 0, r5, c3, c0, 0	/* load domain access register */
-
-	/* Set the TTB register */
-	ldr	r0, _mmu_table_base
-	ldr	r1, =CONFIG_SYS_PHY_UBOOT_BASE
-	ldr	r2, =0xfff00000
-	bic	r0, r0, r2
-	orr	r1, r0, r1
-	mcr	p15, 0, r1, c2, c0, 0
-
-	/* Enable the MMU */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #1		/* Set CR_M to enable MMU */
-
-	/* Prepare to enable the MMU */
-	adr	r1, skip_hw_init
-	and	r1, r1, #0x3fc
-	ldr	r2, _TEXT_BASE
-	ldr	r3, =0xfff00000
-	and	r2, r2, r3
-	orr	r2, r2, r1
-	b	mmu_enable
-
-	.align 5
-	/* Run in a single cache-line */
-mmu_enable:
-
-	mcr	p15, 0, r0, c1, c0, 0
-	nop
-	nop
-	mov	pc, r2
-skip_hw_init:
+_board_init_r_ofs:
+	.word board_init_r - _start
 #endif
 
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, =CONFIG_SYS_UBOOT_BASE	/* base of copy in DRAM	    */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0			/* clear                            */
-
-clbss_l:
-	str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-#ifndef CONFIG_NAND_SPL
-	ldr	pc, _start_armboot
-
-_start_armboot:
-	.word start_armboot
-#else
-	b	nand_boot
-/*	.word nand_boot*/
-#endif
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 #ifdef CONFIG_ENABLE_MMU
 _mmu_table_base:
 	.word mmu_table
@@ -659,14 +494,7 @@ phy_last_jump:
 	/* Save user registers (now in svc mode) r0-r12 */
 	stmia	sp, {r0 - r12}
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
-	/* set base 2 words into abort stack */
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	/* get values for "aborted" pc and cpsr (into parm regs) */
 	ldmia	r2, {r2 - r3}
 	/* grab pointer to old stack */
@@ -681,16 +509,7 @@ phy_last_jump:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	/* setup our mode stack (enter in banked mode) */
-	ldr	r13, _armboot_start
-	/* move past malloc pool */
-	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)
-	/* move to reserved a couple spots for abort stack */
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	/* save caller lr in position 0 of saved stack */
 	str	lr, [r13]
@@ -715,16 +534,7 @@ phy_last_jump:
 	sub	r13, r13, #4
 	/* save R0's value. */
 	str	r0, [r13]
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	/* get data regions start */
-	ldr	r0, _armboot_start
-	/* move past malloc pool */
-	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)
-	/* move past gbl and a couple spots for abort stack */
-	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 	/* save caller lr in position 0 of saved stack */
 	str	lr, [r0]
 	/* get the spsr */
diff --git a/arch/arm/cpu/arm1176/u-boot.lds b/arch/arm/cpu/arm1176/u-boot.lds
index fa640eec200648fb81f42942b2a6961fb87483df..d9ed95405d848784b6e50eadcb51bfba0e08f36e 100644
--- a/arch/arm/cpu/arm1176/u-boot.lds
+++ b/arch/arm/cpu/arm1176/u-boot.lds
@@ -51,11 +51,14 @@ SECTIONS
 		*(.data.rel.ro)
 	}
 
-	__got_start = .;
 	. = ALIGN(4);
-	.got : { *(.got) }
+	__rel_dyn_start = .;
+	.rel.dyn : { *(.rel.dyn) }
+	__rel_dyn_end = .;
+
+	__dynsym_start = .;
+	.dynsym : { *(.dynsym) }
 
-	__got_end = .;
 	. = .;
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
@@ -65,4 +68,10 @@ SECTIONS
 	__bss_start = .;
 	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
 	_end = .;
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index d93911f566b04060c76c04889dcd540a01c4d8b6..8cd267b352a215bfcad139d75d40802066c599cc 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -23,7 +23,7 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #include <asm/hardware.h>
@@ -79,12 +79,6 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -108,7 +102,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -197,7 +190,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -222,9 +214,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -264,92 +255,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 _board_init_r: .word board_init_r
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifdef CONFIG_LPC2292
-	bl	lowlevel_init
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp	r0, r1			/* don't reloc during debug	    */
-	beq	stack_setup
-
-#if CONFIG_SYS_TEXT_BASE
-#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
-	ldr	r2, =0x0		/* Relocate the exception vectors   */
-	cmp	r1, r2			/* and associated data to address   */
-	ldmneia r0!, {r3-r10}		/* 0x0. Do nothing if CONFIG_SYS_TEXT_BASE is  */
-	stmneia r2!, {r3-r10}		/* 0x0. Copy the first 15 words.    */
-	ldmneia r0, {r3-r9}
-	stmneia r2, {r3-r9}
-	adrne	r0, _start		/* restore r0			    */
-#endif	/* !CONFIG_LPC2292 */
-#endif
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area			    */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo			    */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment	    */
-	ldr	r1, _bss_end		/* stop here			    */
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:str	r2, [r0]		/* clear loop...		    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot: .word start_armboot
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -606,13 +511,7 @@ lock_loop:
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add	r8, sp, #S_PC
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -643,13 +542,7 @@ lock_loop:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c
index b13283a798e884ec141d846278966ea69077c395..3ae558dd62804b0e8166864d43ddd6ac3cb82a7f 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c
@@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg)
 	ulong r, m, p, s;
 
 	if (pllreg == MPLL)
-		r = readl(&clk_power->MPLLCON);
+		r = readl(&clk_power->mpllcon);
 	else if (pllreg == UPLL)
-		r = readl(&clk_power->UPLLCON);
+		r = readl(&clk_power->upllcon);
 	else
 		hang();
 
@@ -64,7 +64,12 @@ static ulong get_PLLCLK(int pllreg)
 	p = ((r & 0x003F0) >> 4) + 2;
 	s = r & 0x3;
 
+#if defined(CONFIG_S3C2440)
+	if (pllreg == MPLL)
+		return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
+#endif
 	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+
 }
 
 /* return FCLK frequency */
@@ -77,8 +82,23 @@ ulong get_FCLK(void)
 ulong get_HCLK(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-	return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+#ifdef CONFIG_S3C2440
+	switch (readl(&clk_power->clkdivn) & 0x6) {
+	default:
+	case 0:
+		return get_FCLK();
+	case 2:
+		return get_FCLK() / 2;
+	case 4:
+		return (readl(&clk_power->camdivn) & (1 << 9)) ?
+			get_FCLK() / 8 : get_FCLK() / 4;
+	case 6:
+		return (readl(&clk_power->camdivn) & (1 << 8)) ?
+			get_FCLK() / 6 : get_FCLK() / 3;
+	}
+#else
+	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
 }
 
 /* return PCLK frequency */
@@ -86,7 +106,7 @@ ulong get_PCLK(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 
-	return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
 }
 
 /* return UCLK frequency */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c
index 7d47354381c0a68c5ff9491b8bec5244b75f9789..8cf9ff6be0082356f776fd3f76a72fe9fffab70f 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void)
 {
 	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
 
-	return readl(&timers->TCNTO4) & 0xffff;
+	return readl(&timers->tcnto4) & 0xffff;
 }
 
 static ulong timestamp;
@@ -56,7 +56,7 @@ int timer_init(void)
 
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
-	writel(0x0f00, &timers->TCFG0);
+	writel(0x0f00, &timers->tcfg0);
 	if (timer_load_val == 0) {
 		/*
 		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
@@ -68,13 +68,13 @@ int timer_init(void)
 	}
 	/* load value for 10 ms timeout */
 	lastdec = timer_load_val;
-	writel(timer_load_val, &timers->TCNTB4);
-	/* auto load, manual update of Timer 4 */
-	tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
-	writel(tmr, &timers->TCON);
-	/* auto load, start Timer 4 */
+	writel(timer_load_val, &timers->tcntb4);
+	/* auto load, manual update of timer 4 */
+	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+	writel(tmr, &timers->tcon);
+	/* auto load, start timer 4 */
 	tmr = (tmr & ~0x0700000) | 0x0500000;
-	writel(tmr, &timers->TCON);
+	writel(tmr, &timers->tcon);
 	timestamp = 0;
 
 	return (0);
@@ -181,6 +181,7 @@ ulong get_tbclk(void)
 	tbclk = timer_load_val * 100;
 #elif defined(CONFIG_SBC2410X) || \
       defined(CONFIG_SMDK2410) || \
+	defined(CONFIG_S3C2440) || \
       defined(CONFIG_VCMA9)
 	tbclk = CONFIG_SYS_HZ;
 #else
@@ -206,13 +207,13 @@ void reset_cpu(ulong ignored)
 	watchdog = s3c24x0_get_base_watchdog();
 
 	/* Disable watchdog */
-	writel(0x0000, &watchdog->WTCON);
+	writel(0x0000, &watchdog->wtcon);
 
 	/* Initialize watchdog timer count register */
-	writel(0x0001, &watchdog->WTCNT);
+	writel(0x0001, &watchdog->wtcnt);
 
 	/* Enable watchdog timer; assert reset at timer timeout */
-	writel(0x0021, &watchdog->WTCON);
+	writel(0x0021, &watchdog->wtcon);
 
 	while (1)
 		/* loop forever and wait for reset to happen */;
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c
index e468ed08fc4d22bf9a3341f50400fa111e79ca38..226a3f6c90cbb73c9a34313fd8657d06b108bf78 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/usb.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb.c
@@ -39,14 +39,14 @@ int usb_cpu_init(void)
 	 * Set the 48 MHz UPLL clocking. Values are taken from
 	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
 	 */
-	writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+	writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
 	/* 1 = use pads related USB for USB host */
-	writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
+	writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
 
 	/*
 	 * Enable USB host clock.
 	 */
-	writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
 	return 0;
 }
@@ -55,14 +55,14 @@ int usb_cpu_stop(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
 	/* may not want to do this */
-	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
 	return 0;
 }
 
 int usb_cpu_init_fail(void)
 {
 	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
 	return 0;
 }
 
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
index 5aa8d64a55cfddeea11014c2256be3a1f6240824..ccc97384f33dc5eea517e42cbca433c996d9cd2d 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void)
 	 * Set the 48 MHz UPLL clocking. Values are taken from
 	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
 	 */
-	clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
-	gpio->MISCCR |= 0x8;	/* 1 = use pads related USB for USB host */
+	clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
+	gpio->misccr |= 0x8;	/* 1 = use pads related USB for USB host */
 
 	/*
 	 * Enable USB host clock.
 	 */
-	clk_power->CLKCON |= (1 << 4);
+	clk_power->clkcon |= (1 << 4);
 
 	memset(&gohci, 0, sizeof(struct ohci));
 	memset(&urb_priv, 0, sizeof(struct urb_priv));
@@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void)
 	if (hc_reset(&gohci) < 0) {
 		hc_release_ohci(&gohci);
 		/* Initialization failed */
-		clk_power->CLKCON &= ~(1 << 4);
+		clk_power->clkcon &= ~(1 << 4);
 		return -1;
 	}
 
@@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void)
 		err("can't start usb-%s", gohci.slot_name);
 		hc_release_ohci(&gohci);
 		/* Initialization failed */
-		clk_power->CLKCON &= ~(1 << 4);
+		clk_power->clkcon &= ~(1 << 4);
 		return -1;
 	}
 #ifdef	DEBUG
@@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void)
 	/* call hc_release_ohci() here ? */
 	hc_reset(&gohci);
 	/* may not want to do this */
-	clk_power->CLKCON &= ~(1 << 4);
+	clk_power->clkcon &= ~(1 << 4);
 	return 0;
 }
 
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 343a760df411f0d3d0b935ed537240647e0e8cec..d4edde797b7b24327f1db896b374e59eddf071d5 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -24,6 +24,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <common.h>
 #include <config.h>
 
@@ -74,12 +75,6 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -103,7 +98,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -242,7 +236,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -267,9 +260,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -315,127 +307,6 @@ _nand_boot: .word nand_boot
 _board_init_r: .word board_init_r
 #endif
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual start code
- */
-
-start_code:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x1f
-	orr	r0, r0, #0xd3
-	msr	cpsr, r0
-
-	bl	coloured_LED_init
-	bl	red_LED_on
-
-#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
-	/*
-	 * relocate exception table
-	 */
-	ldr	r0, =_start
-	ldr	r1, =0x0
-	mov	r2, #16
-copyex:
-	subs	r2, r2, #1
-	ldr	r3, [r0], #4
-	str	r3, [r1], #4
-	bne	copyex
-#endif
-
-#ifdef CONFIG_S3C24X0
-	/* turn off the watchdog */
-
-# if defined(CONFIG_S3C2400)
-#  define pWTCON	0x15300000
-#  define INTMSK	0x14400008	/* Interupt-Controller base addresses */
-#  define CLKDIVN	0x14800014	/* clock divisor register */
-#else
-#  define pWTCON	0x53000000
-#  define INTMSK	0x4A000008	/* Interupt-Controller base addresses */
-#  define INTSUBMSK	0x4A00001C
-#  define CLKDIVN	0x4C000014	/* clock divisor register */
-# endif
-
-	ldr	r0, =pWTCON
-	mov	r1, #0x0
-	str	r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =INTMSK
-	str	r1, [r0]
-# if defined(CONFIG_S3C2410)
-	ldr	r1, =0x3ff
-	ldr	r0, =INTSUBMSK
-	str	r1, [r0]
-# endif
-
-	/* FCLK:HCLK:PCLK = 1:2:4 */
-	/* default FCLK is 120 MHz ! */
-	ldr	r0, =CLKDIVN
-	mov	r1, #3
-	str	r1, [r0]
-#endif	/* CONFIG_S3C24X0 */
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp	r0, r1			/* don't reloc during debug         */
-	beq	stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area              */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                 */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot:	.word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -524,15 +395,7 @@ cpu_init_crit:
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE)
-	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
-	/* set base 2 words into abort stack */
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	ldmia	r2, {r2 - r3}			@ get pc, cpsr
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -564,15 +427,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE)
-	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)
-	/* reserve a couple spots in abort stack */
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S
index cf18a01664099ad9b12cc6ec947f67e8061228f1..51229c61544383f58a1e84295f2f6971e5fc202f 100644
--- a/arch/arm/cpu/arm925t/start.S
+++ b/arch/arm/cpu/arm925t/start.S
@@ -30,7 +30,7 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
@@ -85,12 +85,6 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -114,7 +108,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -234,7 +227,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -259,9 +251,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -305,108 +296,6 @@ _nand_boot: .word nand_boot
 _board_init_r: .word board_init_r
 #endif
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * Set up 925T mode
-	 */
-	mov r1, #0x81               /* Set ARM925T configuration. */
-	mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
-
-	/*
-	 * turn off the watchdog, unlock/diable sequence
-	 */
-	mov  r1, #0xF5
-	ldr  r0, =WDTIM_MODE
-	strh r1, [r0]
-	mov  r1, #0xA0
-	strh r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov r1, #0xffffffff
-	ldr r0, =REG_IHL1_MIR
-	str r1, [r0]
-	ldr r0, =REG_IHL2_MIR
-	str r1, [r0]
-
-	/*
-	 * wait for dpll to lock
-	 */
-	ldr  r0, =CK_DPLL1
-	mov  r1, #0x10
-	strh r1, [r0]
-poll1:
-	ldrh r1, [r0]
-	ands r1, r1, #0x01
-	beq poll1
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl  cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot:	.word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -489,13 +378,7 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 
@@ -526,13 +409,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN
-#endif
 
 	str	lr, [r13]			@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr                        @ get the spsr
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
index 7439c87f681070cb3ab24c615afcf8642bbb6ca7..2441554ae3c011c1ae062734dc8369544adf431d 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
@@ -81,6 +81,16 @@ int dram_init(void)
 		gd->ram_size += gd->bd->bi_dram[i].size;
 
 	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
 	return 0;
 }
 
@@ -93,4 +103,3 @@ void dram_init_banksize(void)
 	dram_init();
 }
 #endif /* CONFIG_SYS_BOARD_DRAM_INIT */
-
diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c
index 1e33150eb9ff4a8730b382b0550cb96c71ff6206..1a4368308104b964272f4c3b3244433817a0540e 100644
--- a/arch/arm/cpu/arm926ejs/mx25/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx25/reset.c
@@ -43,14 +43,14 @@ void reset_cpu (ulong ignored)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */
-	writel (0x00000000, &regs->wcr);
+	writew(0, &regs->wcr);
 
 	/* Write Service Sequence */
-	writel (0x00005555, &regs->wsr);
-	writel (0x0000AAAA, &regs->wsr);
+	writew(WSR_UNLOCK1, &regs->wsr);
+	writew(WSR_UNLOCK2, &regs->wsr);
 
 	/* Enable watchdog */
-	writel (WCR_WDE, &regs->wcr);
+	writew(WCR_WDE, &regs->wcr);
 
 	while (1) ;
 }
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
index c5c8ab7e4d88f74e677f0eeb3d5d82c9016920fc..b749282099061f0210bf71fdcc5c2adac90e5b11 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
@@ -49,20 +49,6 @@ u32 orion5x_sdram_bar(enum memory_bank bank)
 	result = winregs[bank].base;
 	return result;
 }
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
-		gd->bd->bi_dram[i].size = get_ram_size(
-			(volatile long *) (gd->bd->bi_dram[i].start),
-			CONFIG_MAX_RAM_BANK_SIZE);
-	}
-	return 0;
-}
-#else
 int dram_init (void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -83,4 +69,3 @@ void dram_init_banksize (void)
 			CONFIG_MAX_RAM_BANK_SIZE);
 	}
 }
-#endif
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 863de3ba0fc64cea888911ed1c49208749993aa2..6dcc9b4d6749455382ebb122a67334a950c4c9b8 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -31,7 +31,7 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
 #include <version.h>
@@ -145,7 +145,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -205,7 +204,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -225,13 +223,13 @@ copy_loop:
 	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
 	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
 	ldr	r1, [r2, #4]
 	and	r8, r1, #0xff
-	cmp	r8, #23		/* relative fixup? */
+	cmp	r8, #23			/* relative fixup? */
 	beq	fixrel
-	cmp	r8, #2		/* absolute fixup? */
+	cmp	r8, #2			/* absolute fixup? */
 	beq	fixabs
 	/* ignore unknown type of fixup */
 	b	fixnext
@@ -248,11 +246,10 @@ fixrel:
 	add	r1, r1, r9
 fixnext:
 	str	r1, [r0]
-	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -286,8 +283,8 @@ _nand_boot_ofs:
 #else
 	ldr	r0, _board_init_r_ofs
 	adr	r1, _start
-	add	r0, r0, r1
-	add	lr, r0, r9
+	add	lr, r0, r1
+	add	lr, lr, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
@@ -305,89 +302,6 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-	ldr	r3, _bss_start_ofs	/* r3 <- _bss_start - _start	    */
-	add	r2, r0, r3		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
-#ifndef CONFIG_PRELOADER
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-#endif /* CONFIG_PRELOADER */
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	adr	r2, _start
-	ldr	r0, _bss_start_ofs	/* find start of bss segment        */
-	add	r0, r0, r2
-	ldr	r1, _bss_end_ofs	/* stop here                        */
-	add	r1, r1, r2
-	mov	r2, #0x00000000		/* clear                            */
-
-#ifndef CONFIG_PRELOADER
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	bl coloured_LED_init
-	bl red_LED_on
-#endif /* CONFIG_PRELOADER */
-
-	ldr	r0, _start_armboot_ofs
-	adr	r1, _start
-	add	r0, r0, r1
-	ldr	pc, r0
-
-_start_armboot_ofs:
-#ifdef CONFIG_NAND_SPL
-	.word nand_boot - _start
-#else
-	.word start_armboot - _start
-#endif /* CONFIG_NAND_SPL */
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -472,13 +386,7 @@ cpu_init_crit:
 	@ carve out a frame on current user stack
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	adr	r2, _start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
@@ -510,13 +418,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	adr	r13, _start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr
diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 077886f36f4b954ca2f6f6c041032a1415bf8843..cad43ba0485631762b8edafa9cfafd3c2a8349ad 100644
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -30,7 +30,7 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
@@ -89,12 +89,6 @@ _fiq:
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -118,7 +112,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -203,7 +196,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -228,9 +220,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -273,72 +264,6 @@ _nand_boot: .word nand_boot
 _board_init_r: .word board_init_r
 #endif
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot:
-	.word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -424,13 +349,7 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
@@ -462,13 +381,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr
diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S
index 07356cb5fd018983d5fd98a0382c1caf6b9f5467..957ca34766c333baaf943c8018fa552ce64ce97d 100644
--- a/arch/arm/cpu/arm_intcm/start.S
+++ b/arch/arm/cpu/arm_intcm/start.S
@@ -30,7 +30,7 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
@@ -87,12 +87,6 @@ _fiq:
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -116,7 +110,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -201,7 +194,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -226,9 +218,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -268,74 +259,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 _board_init_r: .word board_init_r
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-.globl reset
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* pc relative  address of label    */
-	ldr	r1, _TEXT_BASE		/* linked image address of label    */
-	cmp	r0, r1                  /* test if we run from flash or RAM */
-	beq	stack_setup             /* ifeq we are in the RAM copy      */
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot:
-	.word start_armboot
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -400,13 +323,7 @@ cpu_init_crit:
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	@ get values for "aborted" pc and cpsr (into parm regs)
 	ldmia	r2, {r2 - r3}
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
@@ -438,13 +355,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]	@ save caller lr in position 0 of saved stack
 	mrs	lr, spsr	@ get the spsr
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 00f649cf487dfb2295f9e94fd7d44e3da7404f33..0b04a8819a4740068d9b28b7a9ee2127ea99e70b 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -269,7 +269,7 @@ u32 imx_get_fecclk(void)
 /*
  * Dump some core clockes.
  */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	u32 freq;
 
diff --git a/arch/arm/cpu/armv7/mx5/u-boot.lds b/arch/arm/cpu/armv7/mx5/u-boot.lds
deleted file mode 100644
index 55d6599b41c6cb20d636fc3e3a5faf4863f285c0..0000000000000000000000000000000000000000
--- a/arch/arm/cpu/armv7/mx5/u-boot.lds
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text	   :
-	{
-	  arch/arm/cpu/armv7/start.o
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	__datarel_start = .;
-		*(.data.rel)
-	__datarelrolocal_start = .;
-		*(.data.rel.ro.local)
-	__datarellocal_start = .;
-		*(.data.rel.local)
-	__datarelro_start = .;
-		*(.data.rel.ro)
-	}
-
-	__got_start = .;
-	. = ALIGN(4);
-	.got : { *(.got) }
-	__got_end = .;
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss : { *(.bss) }
-	_end = .;
-}
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
index da2cd9001303c1c23e3e7c4ab613dc8bc17a4391..0870857ede4eddd9d63a9783e5aff180ede84dbf 100644
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ b/arch/arm/cpu/armv7/omap3/emif4.c
@@ -136,29 +136,6 @@ void do_emif4_init(void)
  * dram_init -
  *  - Sets uboots idea of sdram size
  */
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
-		size1 = get_sdr_cs_size(CS1);
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-#else
 int dram_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
@@ -190,7 +167,6 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
 }
-#endif
 
 /*
  * mem_init() -
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 6c419f5b93dcc8dc7281c868ff600f67e8a8d118..c75aa1d11ca69b44573345b93a7599e284242e10 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -163,33 +163,6 @@ void do_sdrc_init(u32 cs, u32 early)
  * dram_init -
  *  - Sets uboots idea of sdram size
  */
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-
-		size1 = get_sdr_cs_size(CS1);
-	}
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-#else
 int dram_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
@@ -225,7 +198,6 @@ void dram_init_banksize (void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 	gd->bd->bi_dram[1].size = size1;
 }
-#endif
 
 /*
  * mem_init -
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 24a66f5b94637e8d00e81b0ac601c6db74b06be0..e7651d2dd5b5007aa27c95677d8b070b71b5038d 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -102,12 +102,7 @@ int dram_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	gd->bd->bi_dram[0].start = 0x80000000;
-	gd->bd->bi_dram[0].size = sdram_size();
-#else
 	gd->ram_size = sdram_size();
-#endif
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 64c86e97690c00b55076b5a588a4a19a00f2a3be..bb3948d401cc30f34c9e748e53bdbda99ad5cbba 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -29,6 +29,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
@@ -69,12 +70,6 @@ _end_vect:
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -98,7 +93,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -195,7 +189,6 @@ relocate_code:
 stack_setup:
 	mov	sp, r4
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 	adr	r0, _start
 	ldr	r2, _TEXT_BASE
 	ldr	r3, _bss_start_ofs
@@ -224,13 +217,13 @@ copy_loop:
 	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
 	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
 	ldr	r1, [r2, #4]
 	and	r8, r1, #0xff
-	cmp	r8, #23		/* relative fixup? */
+	cmp	r8, #23			/* relative fixup? */
 	beq	fixrel
-	cmp	r8, #2		/* absolute fixup? */
+	cmp	r8, #2			/* absolute fixup? */
 	beq	fixabs
 	/* ignore unknown type of fixup */
 	b	fixnext
@@ -247,7 +240,7 @@ fixrel:
 	add	r1, r1, r9
 fixnext:
 	str	r1, [r0]
-	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
 
@@ -265,7 +258,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	cmp	r0, r1
 	bne	clbss_l
 #endif	/* #ifndef CONFIG_PRELOADER */
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -274,8 +266,8 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 jump_2_ram:
 	ldr	r0, _board_init_r_ofs
 	adr	r1, _start
-	add	r0, r0, r1
-	add	lr, r0, r9
+	add	lr, r0, r1
+	add	lr, lr, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
@@ -292,94 +284,6 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0, cpsr
-	bic	r0, r0, #0x1f
-	orr	r0, r0, #0xd3
-	msr	cpsr,r0
-
-#if (CONFIG_OMAP34XX)
-	/* Copy vectors to mask ROM indirect addr */
-	adr	r0, _start		@ r0 <- current position of code
-	add	r0, r0, #4		@ skip reset vector
-	mov	r2, #64			@ r2 <- size to copy
-	add	r2, r0, r2		@ r2 <- source end address
-	mov	r1, #SRAM_OFFSET0	@ build vect addr
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
-	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
-	cmp	r0, r2			@ until source end address [r2]
-	bne	next			@ loop until equal */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
-	/* No need to copy/exec the clock code - DPLL adjust already done
-	 * in NAND/oneNAND Boot.
-	 */
-	bl	cpy_clk_code		@ put dpll adjust code behind vectors
-#endif /* NAND Boot */
-#endif
-	/* the mask ROM code should have PLL and others stable */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				@ relocate U-Boot to RAM
-	adr	r0, _start		@ r0 <- current position of code
-	ldr	r1, _TEXT_BASE		@ test if we run from flash or RAM
-	cmp	r0, r1			@ don't reloc during debug
-	beq	stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		@ r2 <- size of armboot
-	add	r2, r0, r2		@ r2 <- source end address
-
-copy_loop:				@ copy 32 bytes at a time
-	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
-	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
-	cmp	r0, r2			@ until source end address [r2]
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack */
-stack_setup:
-	ldr	r0, _TEXT_BASE		@ upper 128 KiB: relocated uboot
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		@ leave 3 words for abort-stack
-	bic	sp, sp, #7		@ 8-byte alignment for ABI compliance
-
-	/* Clear BSS (if any). Is below tx (watch load addr - need space) */
-clear_bss:
-	ldr	r0, _bss_start		@ find start of bss segment
-	ldr	r1, _bss_end		@ stop here
-	mov	r2, #0x00000000		@ clear value
-clbss_l:
-	str	r2, [r0]		@ clear BSS location
-	cmp	r0, r1			@ are we at the end yet
-	add	r0, r0, #4		@ increment clear index pointer
-	bne	clbss_l			@ keep clearing till at end
-
-	ldr	pc, _start_armboot	@ jump to C code
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*************************************************************************
  *
  * CPU_init_critical registers
@@ -461,14 +365,8 @@ cpu_init_crit:
 						@ user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in
 						@ svc mode) r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8)	@ set base 2 words into abort
-#else
 	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
 						@ stack
-#endif
 	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
 						@ and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
@@ -504,14 +402,8 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack (enter
-	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
 						@ in banked mode)
-#endif
 
 	str	lr, [r13]			@ save caller lr in position 0
 						@ of saved stack
@@ -532,14 +424,8 @@ cpu_init_crit:
 	sub	r13, r13, #4			@ space on current stack for
 						@ scratch reg.
 	str	r0, [r13]			@ save R0's value.
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r0, _armboot_start		@ get data regions start
-	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
-	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)	@ move past gbl and a couple
-#else
 	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
 						@ spots for abort stack
-#endif
 	str	lr, [r0]			@ save caller lr in position 0
 						@ of saved stack
 	mrs	r0, spsr			@ get the spsr
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
index 836c33ba8b2e48e72dfb311e006672bee4592136..8d1aebc7199892cbdb53af18a2f4e98fe3c69f33 100644
--- a/arch/arm/cpu/ixp/start.S
+++ b/arch/arm/cpu/ixp/start.S
@@ -27,6 +27,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #include <asm/arch/ixp425.h>
@@ -97,12 +98,6 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -126,7 +121,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -326,7 +320,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -351,9 +344,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -393,190 +385,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 _board_init_r: .word board_init_r
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/****************************************************************************/
-/*									    */
-/* the actual reset code						    */
-/*									    */
-/****************************************************************************/
-
-reset:
-	/* disable mmu, set big-endian */
-	mov	r0, #0xf8
-	mcr	p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* disable write buffer coalescing */
-	mrc	p15, 0, r0, c1, c0, 1
-	orr	r0, r0, #1
-	mcr	p15, 0, r0, c1, c0, 1
-	CPWAIT	r0
-
-	/* set EXP CS0 to the optimum timing */
-	ldr	r1, =CONFIG_SYS_EXP_CS0
-	ldr     r2, =IXP425_EXP_CS0
-	str     r1, [r2]
-
-	/* make sure flash is visible at 0 */
-#if 0
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	orr     r1, r1, #0x80000000
-	str     r1, [r2]
-#endif
-	mov	r1, #CONFIG_SYS_SDR_CONFIG
-	ldr     r2, =IXP425_SDR_CONFIG
-	str     r1, [r2]
-
-	/* disable refresh cycles */
-	mov	r1, #0
-	ldr     r3, =IXP425_SDR_REFRESH
-	str	r1, [r3]
-
-	/* send nop command */
-	mov	r1, #3
-	ldr	r4, =IXP425_SDR_IR
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* set SDRAM internal refresh val */
-	ldr	r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
-	str     r1, [r3]
-	DELAY_FOR 0x4000, r0
-
-	/* send precharge-all command to close all open banks */
-	mov     r1, #2
-	str     r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* provide 8 auto-refresh cycles */
-	mov     r1, #4
-	mov     r5, #8
-111:    str	r1, [r4]
-	DELAY_FOR 0x100, r0
-	subs	r5, r5, #1
-	bne	111b
-
-	/* set mode register in sdram */
-	mov	r1, #CONFIG_SYS_SDR_MODE_CONFIG
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* send normal operation command */
-	mov	r1, #6
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* copy */
-	mov     r0, #0
-	mov     r4, r0
-	add     r2, r0, #CONFIG_SYS_MONITOR_LEN
-	mov     r1, #0x10000000
-	mov     r5, r1
-
-    30:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r0, r2
-	bne     30b
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* move flash to 0x50000000 */
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	bic     r1, r1, #0x80000000
-	str     r1, [r2]
-
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* enable I cache */
-	mrc     p15, 0, r0, c1, c0, 0
-	orr     r0, r0, #MMU_Control_I
-	mcr     p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
-	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot: .word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 
 /****************************************************************************/
 /*									    */
@@ -617,13 +425,7 @@ _start_armboot: .word start_armboot
 	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
 	add	r8, sp, #S_PC
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
 	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
 
@@ -658,13 +460,7 @@ _start_armboot: .word start_armboot
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
index d944860fca7ba04513f6d2cbbd9e526f8c991c88..fd8a40b8aa4a2aea201be7cf6d1d4c2d07658164 100644
--- a/arch/arm/cpu/lh7a40x/start.S
+++ b/arch/arm/cpu/lh7a40x/start.S
@@ -24,11 +24,10 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
-
 /*
  *************************************************************************
  *
@@ -76,12 +75,6 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -105,7 +98,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -215,7 +207,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -240,9 +231,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -279,100 +269,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 _board_init_r: .word board_init_r
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-#define pWDTCTL		0x80001400  /* Watchdog Timer control register */
-#define pINTENC		0x8000050C  /* Interupt-Controller enable clear register */
-#define pCLKSET		0x80000420  /* clock divisor register */
-
-	/* disable watchdog, set watchdog control register to
-	 * all zeros (default reset)
-	 */
-	ldr     r0, =pWDTCTL
-	mov     r1, #0x0
-	str     r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTENC register (default)
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =pINTENC
-	str	r1, [r0]
-
-	/* FCLK:HCLK:PCLK = 1:2:2 */
-	/* default FCLK is 200 MHz, using 14.7456 MHz fin */
-	ldr	r0, =pCLKSET
-	ldr r1, =0x0004ee39
-@	ldr r1, =0x0005ee39	@ 1: 2: 4
-	str	r1, [r0]
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	@add	r0, r0, #4		/* start at first byte of bss       */
-					/*   why inc. 4 bytes past then?    */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot:	.word start_armboot
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -461,13 +357,7 @@ cpu_init_crit:
 	.macro	bad_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	ldmia	r2, {r2 - r3}			@ get pc, cpsr
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -498,13 +388,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
index 3ea34582e7a34a04a0ccef372b5c95be3c81279d..7d49cbb4fd9af1a33e425e33267213fc497addc2 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/cpu.c
@@ -312,7 +312,7 @@ void pxa_wakeup(void)
 int arch_cpu_init(void)
 {
 	pxa_gpio_setup();
-//	pxa_wait_ticks(0x8000);
+/*	pxa_wait_ticks(0x8000); */
 	pxa_wakeup();
 	pxa_interrupt_setup();
 	pxa_clock_setup();
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 684e44e8389508c1fd27c461afe064f2bb27f882..ae358a56e61f816d4c87930a022f07c5e7ba48e8 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -8,6 +8,7 @@
  *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
  *  Copyright (C) 2003	Robert Schwebel <r.schwebel@pengutronix.de>
  *  Copyright (C) 2003	Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ *  Copyright (c) 2010	Marek Vasut <marek.vasut@gmail.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -28,10 +29,10 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
 
 /* takes care the CP15 update has taken place */
 .macro CPWAIT reg
@@ -94,20 +95,16 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-.globl _armboot_start
-_armboot_start:
-	.word _start
-
 /*
  * These are defined in the board-specific linker script.
  */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
 
-.globl _bss_end
-_bss_end:
-	.word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
 
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
@@ -127,30 +124,6 @@ FIQ_STACK_START:
 IRQ_STACK_START_IN:
 	.word	0x0badc0de
 
-.globl _datarel_start
-_datarel_start:
-	.word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
-	.word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
-	.word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
-	.word __datarelro_start
-
-.globl _got_start
-_got_start:
-	.word __got_start
-
-.globl _got_end
-_got_end:
-	.word __got_end
-
 /*
  * the actual reset code
  */
@@ -272,13 +245,11 @@ stack_setup:
 
 	adr	r0, _start
 	ldr	r2, _TEXT_BASE
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot	    */
-	add	r2, r0, r2		/* r2 <- source end address	    */
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 	stmfd sp!, {r0-r12}
 copy_loop:
 	ldmia	r0!, {r3-r5, r7-r11}	/* copy from source address [r0]    */
@@ -288,36 +259,53 @@ copy_loop:
 	ldmfd sp!, {r0-r12}
 
 #ifndef CONFIG_PRELOADER
-	/* fix got entries */
-	ldr	r1, _TEXT_BASE		/* Text base */
-	mov	r0, r7			/* reloc addr */
-	ldr	r2, _got_start		/* addr in Flash */
-	ldr	r3, _got_end		/* addr in Flash */
-	sub	r3, r3, r1
-	add	r3, r3, r0
-	sub	r2, r2, r1
-	add	r2, r2, r0
-
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
 fixloop:
-	ldr	r4, [r2]
-	sub	r4, r4, r1
-	add	r4, r4, r0
-	str	r4, [r2]
-	add	r2, r2, #4
+	ldr	r0, [r2]	/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23		/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2		/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8	/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
-	bne	fixloop
-#endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
+	blo	fixloop
+#endif	/* #ifndef CONFIG_PRELOADER */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
-	ldr	r0, _bss_start
-	ldr	r1, _bss_end
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
 	ldr	r3, _TEXT_BASE		/* Text base */
 	mov	r4, r7			/* reloc addr */
-	sub	r0, r0, r3
 	add	r0, r0, r4
-	sub	r1, r1, r3
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
@@ -325,32 +313,41 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
-#endif
+#endif	/* #ifndef CONFIG_PRELOADER */
 
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 #ifdef CONFIG_ONENAND_IPL
-	ldr     pc, _start_oneboot
+	ldr     r0, _start_oneboot_ofs
+	mov	pc, r0
 
-_start_oneboot: .word start_oneboot
+_start_oneboot_ofs
+	: .word start_oneboot
 #else
-	ldr	r0, _TEXT_BASE
-	ldr	r2, _board_init_r
-	sub	r2, r2, r0
-	add	r2, r2, r7	/* position from board_init_r in RAM */
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	lr, r0, r1
+	add	lr, lr, r9
 	/* setup parameters for board_init_r */
 	mov	r0, r5		/* gd_t */
 	mov	r1, r7		/* dest_addr */
 	/* jump to it ... */
-	mov	lr, r2
 	mov	pc, lr
 
-_board_init_r: .word board_init_r
-#endif
+_board_init_r_ofs:
+	.word board_init_r - _start
+#endif	/* CONFIG_ONENAND_IPL */
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
+#else /* CONFIG_PRELOADER */
 
 /****************************************************************************/
 /*									    */
@@ -375,7 +372,7 @@ reset:
 	/* Start OneNAND IPL */
 	ldr	pc, =start_oneboot
 
-#endif /* #if !defined(CONFIG_ONENAND_IPL) */
+#endif /* CONFIG_PRELOADER */
 
 #ifndef CONFIG_PRELOADER
 /****************************************************************************/
@@ -417,13 +414,7 @@ reset:
 	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
 	add	r8, sp, #S_PC
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
 	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
 
@@ -458,13 +449,7 @@ reset:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
@@ -483,7 +468,7 @@ reset:
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
-#endif	/* CONFIG_PRELOADER */
+#endif	/* CONFIG_PRELOADER
 
 
 /****************************************************************************/
@@ -497,7 +482,7 @@ reset:
 do_hang:
 	ldr	sp, _TEXT_BASE			/* use 32 words abort stack */
 	bl	hang				/* hang and never return */
-#else	/* !CONFIG_PRELOADER */
+#else
 	.align	5
 undefined_instruction:
 	get_bad_stack
@@ -567,13 +552,7 @@ fiq:
 /*									    */
 /****************************************************************************/
 /* Operating System Timer */
-OSTIMER_BASE:	.word	0x40a00000
-#define OSMR3	0x0C
-#define OSCR	0x10
-#define OWER	0x18
-#define OIER	0x1C
-
-	.align	5
+.align	5
 .globl reset_cpu
 
 	/* FIXME: this code is PXA250 specific. How is this handled on	    */
@@ -583,18 +562,20 @@ reset_cpu:
 
 	/* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 
-	ldr	r0, OSTIMER_BASE
-	ldr	r1, [r0, #OWER]
+	ldr	r0, =OWER
+	ldr	r1, [r0]
 	orr	r1, r1, #0x0001			/* bit0: WME		    */
-	str	r1, [r0, #OWER]
+	str	r1, [r0]
 
 	/* OS timer does only wrap every 1165 seconds, so we have to set    */
 	/* the match register as well.					    */
 
-	ldr	r1, [r0, #OSCR]			/* read OS timer	    */
+	ldr	r0, =OSCR
+	ldr	r1, [r0]			/* read OS timer	    */
 	add	r1, r1, #0x800			/* let OSMR3 match after    */
 	add	r1, r1, #0x800			/* 4096*(1/3.6864MHz)=1ms   */
-	str	r1, [r0, #OSMR3]
+	ldr	r0, =OSMR3
+	str	r1, [r0]
 
 reset_endless:
 
@@ -620,4 +601,4 @@ mmu_table:
 	.word	(__base << 20) | 0xc12
 	.set	__base, __base + 1
 	.endr
-#endif
+#endif	/* CONFIG_PRELOADER */
diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds
index 74a4c6e90c984c8f312c47afffa4cf1e459718da..d6643f9529b2f95473a2dca4643f00dbfa04c66b 100644
--- a/arch/arm/cpu/pxa/u-boot.lds
+++ b/arch/arm/cpu/pxa/u-boot.lds
@@ -41,21 +41,18 @@ SECTIONS
 	. = ALIGN(4);
 	.data : {
 		*(.data)
-	__datarel_start = .;
-		*(.data.rel)
-	__datarelrolocal_start = .;
-		*(.data.rel.ro.local)
-	__datarellocal_start = .;
-		*(.data.rel.local)
-	__datarelro_start = .;
-		*(.data.rel.ro)
 	}
 
-	__got_start = .;
 	. = ALIGN(4);
-	.got : { *(.got) }
+	__rel_dyn_start = .;
+	.rel.dyn : { *(.rel.dyn) }
+	__rel_dyn_end = .;
+
+	__dynsym_start = .;
+	.dynsym : { *(.dynsym) }
+
+	. = ALIGN(4);
 
-	__got_end = .;
 	. = .;
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
index 20091b24c0eb2ae3cd8deb299f1750e0fe100c6c..67b2c6a695576701d72fee325be1da8f2d3f78ee 100644
--- a/arch/arm/cpu/s3c44b0/start.S
+++ b/arch/arm/cpu/s3c44b0/start.S
@@ -27,11 +27,10 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
-
 /*
  * Jump vector table
  */
@@ -67,12 +66,6 @@ _start:	b       reset
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -96,7 +89,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -187,7 +179,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -212,7 +203,7 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
 /*
 	now copy to sram the interrupt vector
@@ -226,7 +217,6 @@ vector_copy_loop:
 	stmia	r1!, {r3-r10}
 	cmp	r0, r2
 	blo	vector_copy_loop
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -266,84 +256,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 _board_init_r: .word board_init_r
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	bl	lowlevel_init
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-/*
-	now copy to sram the interrupt vector
-*/
-	adr	r0, real_vectors
-	add	r2, r0, #1024
-	ldr	r1, =0x0c000000
-	add	r1, r1, #0x08
-vector_copy_loop:
-	ldmia	r0!, {r3-r10}
-	stmia	r1!, {r3-r10}
-	cmp	r0, r2
-	blo	vector_copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-	ldr	pc, _start_armboot
-
-_start_armboot:	.word start_armboot
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 8eabb66cabaa3eb5473dbe6c66e28f39e8fd5f83..ace0c074df77f409f2e7f64d04eb648d04615948 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -25,11 +25,10 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
-
 /*
  *************************************************************************
  *
@@ -77,12 +76,6 @@ _fiq:			.word fiq
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
-	.word _start
-#endif
-
 /*
  * These are defined in the board-specific linker script.
  */
@@ -106,7 +99,6 @@ FIQ_STACK_START:
 	.word 0x0badc0de
 #endif
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 .globl IRQ_STACK_START_IN
 IRQ_STACK_START_IN:
@@ -191,7 +183,6 @@ stack_setup:
 	cmp	r0, r6
 	beq	clear_bss
 
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 copy_loop:
 	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
 	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
@@ -216,9 +207,8 @@ fixloop:
 	str	r4, [r2]
 	add	r2, r2, #4
 	cmp	r2, r3
-	bne	fixloop
+	blo	fixloop
 #endif
-#endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
 
 clear_bss:
 #ifndef CONFIG_PRELOADER
@@ -255,75 +245,6 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 
 _board_init_r: .word board_init_r
 
-#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
-
-	ldr	pc, _start_armboot
-
-_start_armboot:	.word start_armboot
-
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 /*
  *************************************************************************
  *
@@ -442,13 +363,7 @@ cpu_init_crit:
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
 	add     r8, sp, #S_PC
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-#else
 	ldr	r2, IRQ_STACK_START_IN
-#endif
 	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -479,13 +394,7 @@ cpu_init_crit:
 	.endm
 
 	.macro get_bad_stack
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-#else
 	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-#endif
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index f709bd8e0e6e7c3bfdedeb0b187014c2f7e845de..f5a2929e2209bf522fe156328232d67329393a23 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -108,11 +108,11 @@ struct gpt_regs {
 
 /* Watchdog Timer (WDOG) registers */
 struct wdog_regs {
-	u32 wcr;	/* Control */
-	u32 wsr;	/* Service */
-	u32 wrsr;	/* Reset Status */
-	u32 wicr;	/* Interrupt Control */
-	u32 wmcr;	/* Misc Control */
+	u16 wcr;	/* Control */
+	u16 wsr;	/* Service */
+	u16 wrsr;	/* Reset Status */
+	u16 wicr;	/* Interrupt Control */
+	u16 wmcr;	/* Misc Control */
 };
 
 /* IIM control registers */
@@ -308,7 +308,9 @@ struct iim_regs {
 #define GPT_CTRL_TEN		1		/* Timer enable	*/
 
 /* WDOG enable */
-#define WCR_WDE 0x04
+#define WCR_WDE 		0x04
+#define WSR_UNLOCK1		0x5555
+#define WSR_UNLOCK2		0xAAAA
 
 /* FUSE bank offsets */
 #define IIM0_MAC		0x1a
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 14aa231a5b0b9f7a2f1a15d29fcb84dce59f5099..4ed8eb31c8a283ed6d46ff2fdb66b8dddcfd171c 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -189,4 +189,15 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
 
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
+
+/* Define the bits in register CCGRx */
+#define MXC_CCM_CCGR_CG_MASK				0x3
+
+#define MXC_CCM_CCGR5_CG5_OFFSET			10
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
+
 #endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 3ddda401f318372b44c730c5894959e90930bcfe..0b6249a9b8bbbf024fe1923b6061340a8360a05d 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -26,7 +26,8 @@
 /*
  * IRAM
  */
-#define IRAM_BASE_ADDR		0x1FFE8000	/* internal ram */
+#define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
+#define IRAM_SIZE		0x00020000	/* 128 KB */
 /*
  * Graphics Memory of GPU
  */
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
deleted file mode 100644
index 85958dd32d5cfd8bcd80a25af8b111c958e0c9a1..0000000000000000000000000000000000000000
--- a/arch/arm/include/asm/arch-pxa/macro.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/include/asm/arch-pxa/macro.h
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_PXA_MACRO_H__
-#define __ASM_ARCH_PXA_MACRO_H__
-#ifdef __ASSEMBLY__
-
-#include <asm/macro.h>
-#include <asm/arch/pxa-regs.h>
-
-/*
- * This macro performs a 32bit write to a memory location and makes sure the
- * write operation really happened by performing a read back.
- *
- * Clobbered regs: r4, r5
- */
-.macro	write32rb addr, data
-	ldr	r4, =\addr
-	ldr	r5, =\data
-	str	r5, [r4]
-	ldr	r5, [r4]
-.endm
-
-/*
- * This macro waits according to OSCR incrementation
- *
- * Clobbered regs: r4, r5, r6
- */
-.macro	pxa_wait_ticks ticks
-	ldr	r4, =OSCR
-	mov	r5, #0
-	str	r5, [r4]
-	ldr	r5, =\ticks
-1:
-	ldr	r6, [r4]
-	cmp	r5, r6
-	bgt	1b
-.endm
-
-/*
- * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro	pxa_gpio_setup
-	write32	GPSR0, CONFIG_SYS_GPSR0_VAL
-	write32	GPSR1, CONFIG_SYS_GPSR1_VAL
-	write32	GPSR2, CONFIG_SYS_GPSR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	write32	GPSR3, CONFIG_SYS_GPSR3_VAL
-#endif
-
-	write32	GPCR0, CONFIG_SYS_GPCR0_VAL
-	write32	GPCR1, CONFIG_SYS_GPCR1_VAL
-	write32	GPCR2, CONFIG_SYS_GPCR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	write32	GPCR3, CONFIG_SYS_GPCR3_VAL
-#endif
-
-	write32	GPDR0, CONFIG_SYS_GPDR0_VAL
-	write32	GPDR1, CONFIG_SYS_GPDR1_VAL
-	write32	GPDR2, CONFIG_SYS_GPDR2_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	write32	GPDR3, CONFIG_SYS_GPDR3_VAL
-#endif
-
-	write32	GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
-	write32	GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
-	write32	GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
-	write32	GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
-	write32	GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
-	write32	GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	write32	GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
-	write32	GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
-#endif
-
-	write32	PSSR, CONFIG_SYS_PSSR_VAL
-.endm
-
-/*
- * This macro sets up the Memory controller of the PXA2xx CPU
- *
- * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
- *          and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
- *          use this regs for other purpose inside this macro.
- *
- * Clobbered regs: r3, r4, r5, r6, r7
- */
-.macro	pxa_mem_setup
-	/* This comes handy when setting MDREFR */
-	ldr	r3, =MEMC_BASE
-
-	/*
-	 * 1) Initialize Asynchronous static memory controller
-	 */
-
-	/* MSC0: nCS(0,1) */
-	write32rb	(MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
-	/* MSC1: nCS(2,3) */
-	write32rb	(MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
-	/* MSC2: nCS(4,5) */
-	write32rb	(MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
-
-	/*
-	 * 2) Initialize Card Interface
-	 */
-
-	/* MECR: Memory Expansion Card Register */
-	write32rb	(MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
-	/* MCMEM0: Card Interface slot 0 timing */
-	write32rb	(MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
-	/* MCMEM1: Card Interface slot 1 timing */
-	write32rb	(MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
-	write32rb	(MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
-	write32rb	(MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
-	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
-	write32rb	(MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
-	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
-	write32rb	(MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
-
-	/*
-	 * 3) Configure Fly-By DMA register
-	 */
-
-	write32rb	(MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
-
-	/*
-	 * 4) Initialize Timing for Sync Memory (SDCLK0)
-	 */
-
-	/*
-	 * Before accessing MDREFR we need a valid DRI field, so we set
-	 * this to power on defaults + DRI field.
-	 */
-	ldr	r5, [r3, #MDREFR_OFFSET]
-	bic	r5, r5, #0x0ff
-	bic	r5, r5, #0xf00	/* MDREFR user config with zeroed DRI */
-
-	ldr	r4, =CONFIG_SYS_MDREFR_VAL
-	mov	r7, r4
-	lsl	r4, #20
-	lsr	r4, #20		/* Get a valid DRI field */
-
-	orr	r5, r5, r4	/* MDREFR user config with correct DRI */
-
-	orr	r5, #MDREFR_K0RUN
-	orr	r5, #MDREFR_SLFRSH
-	bic	r5, #MDREFR_APD
-	bic	r5, #MDREFR_E1PIN
-
-	str	r5, [r3, #MDREFR_OFFSET]
-	ldr	r4, [r3, #MDREFR_OFFSET]
-
-	/*
-	 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
-	 */
-
-	/* Initialize SXCNFG register. Assert the enable bits.
-	 *
-	 * Write SXMRS to cause an MRS command to all enabled banks of
-	 * synchronous static memory. Note that SXLCR need not be written
-	 * at this time.
-	 */
-	write32rb	(MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
-
-	/*
-	 * 6) Initialize SDRAM
-	 */
-
-	bic	r7, #MDREFR_SLFRSH
-	str	r7, [r3, #MDREFR_OFFSET]
-	ldr	r4, [r3, #MDREFR_OFFSET]
-
-	orr	r7, #MDREFR_E1PIN
-	str	r7, [r3, #MDREFR_OFFSET]
-	ldr	r4, [r3, #MDREFR_OFFSET]
-
-	/*
-	 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
-	 *    but not enable each SDRAM partition pair.
-	 */
-
-	/* Fetch platform value of MDCNFG */
-	ldr	r4, =CONFIG_SYS_MDCNFG_VAL
-	/* Disable all sdram banks */
-	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-	/* Write initial value of MDCNFG, w/o enabling sdram banks */
-	str	r4, [r3, #MDCNFG_OFFSET]
-	ldr	r4, [r3, #MDCNFG_OFFSET]
-
-	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
-	pxa_wait_ticks	0x300
-
-	/*
-	 * 8) Trigger a number (usually 8) refresh cycles by attempting
-	 *    non-burst read or write accesses to disabled SDRAM, as commonly
-	 *    specified in the power up sequence documented in SDRAM data
-	 *    sheets. The address(es) used for this purpose must not be
-	 *    cacheable.
-	 */
-
-	ldr	r4, =CONFIG_SYS_DRAM_BASE
-.rept 9
-	str	r5, [r4]
-.endr
-
-	/*
-	 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
-	 */
-
-	ldr	r5, =CONFIG_SYS_MDCNFG_VAL
-	ldr	r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
-	and	r5, r5, r4
-	ldr     r4, [r3, #MDCNFG_OFFSET]
-	orr	r4, r4, r5
-	str     r4, [r3, #MDCNFG_OFFSET]
-	ldr     r4, [r3, #MDCNFG_OFFSET]
-
-	/*
-	 * 10) Write MDMRS.
-	 */
-
-	ldr     r4, =CONFIG_SYS_MDMRS_VAL
-	str     r4, [r3, #MDMRS_OFFSET]
-	ldr     r4, [r3, #MDMRS_OFFSET]
-
-	/*
-	 * 11) Enable APD
-	 */
-
-	ldr	r4, [r3, #MDREFR_OFFSET]
-	and	r7, r7, #MDREFR_APD
-	orr	r4, r4, r7
-	str	r4, [r3, #MDREFR_OFFSET]
-	ldr	r4, [r3, #MDREFR_OFFSET]
-.endm
-
-/*
- * This macro tests if the CPU woke up from sleep and eventually resumes
- *
- * Clobbered regs: r4, r5
- */
-.macro	pxa_wakeup
-	ldr	r4, =RCSR
-	ldr	r5, [r4]
-	and	r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
-	str	r5, [r4]
-	teq	r5, #RCSR_SMR
-
-	bne	pxa_wakeup_exit
-
-	ldr	r4, =PSSR
-	mov	r5, #PSSR_PH
-	str	r5, [r4]
-
-	ldr	r4, =PSPR
-	ldr	pc, [r4]
-pxa_wakeup_exit:
-.endm
-
-/*
- * This macro disables all interupts on PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro	pxa_intr_setup
-	write32	ICLR, 0
-	write32	ICMR, 0
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-	write32	ICLR2, 0
-	write32	ICMR2, 0
-#endif
-.endm
-
-/*
- * This macro configures clock on PXA2xx/PXA3xx CPU
- *
- * Clobbered regs: r4, r5
- */
-.macro	pxa_clock_setup
-	/* Disable the peripheral clocks, and set the core clock frequency */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration */
-	write32	CKEN, CONFIG_SYS_CKEN
-
-	/* Write CCCR */
-	write32	CCCR, CONFIG_SYS_CCCR
-
-#ifdef CONFIG_RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager */
-	write32	OSCC, #OSCC_OON
-	ldr	r4, =OSCC
-
-	/* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
-2:
-	ldr	r5, [r4]
-	ands	r5, r5, #1
-	beq	2b
-#endif
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_PXA_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
new file mode 100644
index 0000000000000000000000000000000000000000..8c606e3995abf2c3fced89c03a80cfb26e4ddc0a
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2003
+ * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME	    : s3c2440.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2440 User's manual Rev x.x
+ ************************************************/
+
+#ifndef __S3C2440_H__
+#define __S3C2440_H__
+
+#define S3C24X0_UART_CHANNELS	3
+#define S3C24X0_SPI_CHANNELS	2
+
+/* S3C2440 only supports 512 Byte HW ECC */
+#define S3C2440_ECCSIZE		512
+#define S3C2440_ECCBYTES	3
+
+enum s3c24x0_uarts_nr {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+	S3C24X0_UART2
+};
+
+/* S3C2440 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x48000000
+#define S3C24X0_USB_HOST_BASE		0x49000000
+#define S3C24X0_INTERRUPT_BASE		0x4A000000
+#define S3C24X0_DMA_BASE		0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
+#define S3C24X0_LCD_BASE		0x4D000000
+#define S3C2440_NAND_BASE		0x4E000000
+#define S3C24X0_UART_BASE		0x50000000
+#define S3C24X0_TIMER_BASE		0x51000000
+#define S3C24X0_USB_DEVICE_BASE		0x52000140
+#define S3C24X0_WATCHDOG_BASE		0x53000000
+#define S3C24X0_I2C_BASE		0x54000000
+#define S3C24X0_I2S_BASE		0x55000000
+#define S3C24X0_GPIO_BASE		0x56000000
+#define S3C24X0_RTC_BASE		0x57000000
+#define S3C2440_ADC_BASE		0x58000000
+#define S3C24X0_SPI_BASE		0x59000000
+#define S3C2440_SDI_BASE		0x5A000000
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
+{
+	return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+}
+
+static inline struct s3c24x0_uart
+	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
+{
+	return (struct s3c2440_adc *)S3C2440_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
+{
+	return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+}
+
+#endif /*__S3C2440_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index 15f53dd35bee3baeb48f59a11f300e7a648745c1..f634d112964354b957c6d2a0bd5f19f00908135d 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -33,12 +33,12 @@
 
 /* Memory controller (see manual chapter 5) */
 struct s3c24x0_memctl {
-	u32	BWSCON;
-	u32	BANKCON[8];
-	u32	REFRESH;
-	u32	BANKSIZE;
-	u32	MRSRB6;
-	u32	MRSRB7;
+	u32	bwscon;
+	u32	bankcon[8];
+	u32	refresh;
+	u32	banksize;
+	u32	mrsrb6;
+	u32	mrsrb7;
 };
 
 
@@ -72,40 +72,38 @@ struct s3c24x0_usb_host {
 
 /* INTERRUPT (see manual chapter 14) */
 struct s3c24x0_interrupt {
-	u32	SRCPND;
-	u32	INTMOD;
-	u32	INTMSK;
-	u32	PRIORITY;
-	u32	INTPND;
-	u32	INTOFFSET;
-#ifdef CONFIG_S3C2410
-	u32	SUBSRCPND;
-	u32	INTSUBMSK;
+	u32	srcpnd;
+	u32	intmod;
+	u32	intmsk;
+	u32	priority;
+	u32	intpnd;
+	u32	intoffset;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	subsrcpnd;
+	u32	intsubmsk;
 #endif
 };
 
 
 /* DMAS (see manual chapter 8) */
 struct s3c24x0_dma {
-	u32	DISRC;
-#ifdef CONFIG_S3C2410
-	u32	DISRCC;
+	u32	disrc;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	disrcc;
 #endif
-	u32	DIDST;
-#ifdef CONFIG_S3C2410
-	u32	DIDSTC;
+	u32	didst;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	didstc;
 #endif
-	u32	DCON;
-	u32	DSTAT;
-	u32	DCSRC;
-	u32	DCDST;
-	u32	DMASKTRIG;
-#ifdef CONFIG_S3C2400
+	u32	dcon;
+	u32	dstat;
+	u32	dcsrc;
+	u32	dcdst;
+	u32	dmasktrig;
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
+		|| defined(CONFIG_S3C2440)
 	u32	res[1];
 #endif
-#ifdef CONFIG_S3C2410
-	u32	res[7];
-#endif
 };
 
 struct s3c24x0_dmas {
@@ -116,90 +114,111 @@ struct s3c24x0_dmas {
 /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
 /*                          (see S3C2410 manual chapter 7) */
 struct s3c24x0_clock_power {
-	u32	LOCKTIME;
-	u32	MPLLCON;
-	u32	UPLLCON;
-	u32	CLKCON;
-	u32	CLKSLOW;
-	u32	CLKDIVN;
+	u32	locktime;
+	u32	mpllcon;
+	u32	upllcon;
+	u32	clkcon;
+	u32	clkslow;
+	u32	clkdivn;
+#if defined(CONFIG_S3C2440)
+	u32	camdivn;
+#endif
 };
 
 
 /* LCD CONTROLLER (see manual chapter 15) */
 struct s3c24x0_lcd {
-	u32	LCDCON1;
-	u32	LCDCON2;
-	u32	LCDCON3;
-	u32	LCDCON4;
-	u32	LCDCON5;
-	u32	LCDSADDR1;
-	u32	LCDSADDR2;
-	u32	LCDSADDR3;
-	u32	REDLUT;
-	u32	GREENLUT;
-	u32	BLUELUT;
+	u32	lcdcon1;
+	u32	lcdcon2;
+	u32	lcdcon3;
+	u32	lcdcon4;
+	u32	lcdcon5;
+	u32	lcdsaddr1;
+	u32	lcdsaddr2;
+	u32	lcdsaddr3;
+	u32	redlut;
+	u32	greenlut;
+	u32	bluelut;
 	u32	res[8];
-	u32	DITHMODE;
-	u32	TPAL;
-#ifdef CONFIG_S3C2410
-	u32	LCDINTPND;
-	u32	LCDSRCPND;
-	u32	LCDINTMSK;
-	u32	LPCSEL;
+	u32	dithmode;
+	u32	tpal;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	lcdintpnd;
+	u32	lcdsrcpnd;
+	u32	lcdintmsk;
+	u32	lpcsel;
 #endif
 };
 
 
+#ifdef CONFIG_S3C2410
 /* NAND FLASH (see S3C2410 manual chapter 6) */
 struct s3c2410_nand {
-	u32	NFCONF;
-	u32	NFCMD;
-	u32	NFADDR;
-	u32	NFDATA;
-	u32	NFSTAT;
-	u32	NFECC;
+	u32	nfconf;
+	u32	nfcmd;
+	u32	nfaddr;
+	u32	nfdata;
+	u32	nfstat;
+	u32	nfecc;
+};
+#endif
+#ifdef CONFIG_S3C2440
+/* NAND FLASH (see S3C2440 manual chapter 6) */
+struct s3c2440_nand {
+	u32	nfconf;
+	u32	nfcont;
+	u32	nfcmd;
+	u32	nfaddr;
+	u32	nfdata;
+	u32	nfeccd0;
+	u32	nfeccd1;
+	u32	nfeccd;
+	u32	nfstat;
+	u32	nfstat0;
+	u32	nfstat1;
 };
+#endif
 
 
 /* UART (see manual chapter 11) */
 struct s3c24x0_uart {
-	u32	ULCON;
-	u32	UCON;
-	u32	UFCON;
-	u32	UMCON;
-	u32	UTRSTAT;
-	u32	UERSTAT;
-	u32	UFSTAT;
-	u32	UMSTAT;
+	u32	ulcon;
+	u32	ucon;
+	u32	ufcon;
+	u32	umcon;
+	u32	utrstat;
+	u32	uerstat;
+	u32	ufstat;
+	u32	umstat;
 #ifdef __BIG_ENDIAN
 	u8	res1[3];
-	u8	UTXH;
+	u8	utxh;
 	u8	res2[3];
-	u8	URXH;
+	u8	urxh;
 #else /* Little Endian */
-	u8	UTXH;
+	u8	utxh;
 	u8	res1[3];
-	u8	URXH;
+	u8	urxh;
 	u8	res2[3];
 #endif
-	u32	UBRDIV;
+	u32	ubrdiv;
 };
 
 
 /* PWM TIMER (see manual chapter 10) */
 struct s3c24x0_timer {
-	u32	TCNTB;
-	u32	TCMPB;
-	u32	TCNTO;
+	u32	tcntb;
+	u32	tcmpb;
+	u32	tcnto;
 };
 
 struct s3c24x0_timers {
-	u32	TCFG0;
-	u32	TCFG1;
-	u32	TCON;
+	u32	tcfg0;
+	u32	tcfg1;
+	u32	tcon;
 	struct s3c24x0_timer	ch[4];
-	u32	TCNTB4;
-	u32	TCNTO4;
+	u32	tcntb4;
+	u32	tcnto4;
 };
 
 
@@ -207,9 +226,9 @@ struct s3c24x0_timers {
 struct s3c24x0_usb_dev_fifos {
 #ifdef __BIG_ENDIAN
 	u8	res[3];
-	u8	EP_FIFO_REG;
+	u8	ep_fifo_reg;
 #else /*  little endian */
-	u8	EP_FIFO_REG;
+	u8	ep_fifo_reg;
 	u8	res[3];
 #endif
 };
@@ -217,29 +236,29 @@ struct s3c24x0_usb_dev_fifos {
 struct s3c24x0_usb_dev_dmas {
 #ifdef __BIG_ENDIAN
 	u8	res1[3];
-	u8	EP_DMA_CON;
+	u8	ep_dma_con;
 	u8	res2[3];
-	u8	EP_DMA_UNIT;
+	u8	ep_dma_unit;
 	u8	res3[3];
-	u8	EP_DMA_FIFO;
+	u8	ep_dma_fifo;
 	u8	res4[3];
-	u8	EP_DMA_TTC_L;
+	u8	ep_dma_ttc_l;
 	u8	res5[3];
-	u8	EP_DMA_TTC_M;
+	u8	ep_dma_ttc_m;
 	u8	res6[3];
-	u8	EP_DMA_TTC_H;
+	u8	ep_dma_ttc_h;
 #else /*  little endian */
-	u8	EP_DMA_CON;
+	u8	ep_dma_con;
 	u8	res1[3];
-	u8	EP_DMA_UNIT;
+	u8	ep_dma_unit;
 	u8	res2[3];
-	u8	EP_DMA_FIFO;
+	u8	ep_dma_fifo;
 	u8	res3[3];
-	u8	EP_DMA_TTC_L;
+	u8	ep_dma_ttc_l;
 	u8	res4[3];
-	u8	EP_DMA_TTC_M;
+	u8	ep_dma_ttc_m;
 	u8	res5[3];
-	u8	EP_DMA_TTC_H;
+	u8	ep_dma_ttc_h;
 	u8	res6[3];
 #endif
 };
@@ -247,69 +266,69 @@ struct s3c24x0_usb_dev_dmas {
 struct s3c24x0_usb_device {
 #ifdef __BIG_ENDIAN
 	u8	res1[3];
-	u8	FUNC_ADDR_REG;
+	u8	func_addr_reg;
 	u8	res2[3];
-	u8	PWR_REG;
+	u8	pwr_reg;
 	u8	res3[3];
-	u8	EP_INT_REG;
+	u8	ep_int_reg;
 	u8	res4[15];
-	u8	USB_INT_REG;
+	u8	usb_int_reg;
 	u8	res5[3];
-	u8	EP_INT_EN_REG;
+	u8	ep_int_en_reg;
 	u8	res6[15];
-	u8	USB_INT_EN_REG;
+	u8	usb_int_en_reg;
 	u8	res7[3];
-	u8	FRAME_NUM1_REG;
+	u8	frame_num1_reg;
 	u8	res8[3];
-	u8	FRAME_NUM2_REG;
+	u8	frame_num2_reg;
 	u8	res9[3];
-	u8	INDEX_REG;
+	u8	index_reg;
 	u8	res10[7];
-	u8	MAXP_REG;
+	u8	maxp_reg;
 	u8	res11[3];
-	u8	EP0_CSR_IN_CSR1_REG;
+	u8	ep0_csr_in_csr1_reg;
 	u8	res12[3];
-	u8	IN_CSR2_REG;
+	u8	in_csr2_reg;
 	u8	res13[7];
-	u8	OUT_CSR1_REG;
+	u8	out_csr1_reg;
 	u8	res14[3];
-	u8	OUT_CSR2_REG;
+	u8	out_csr2_reg;
 	u8	res15[3];
-	u8	OUT_FIFO_CNT1_REG;
+	u8	out_fifo_cnt1_reg;
 	u8	res16[3];
-	u8	OUT_FIFO_CNT2_REG;
+	u8	out_fifo_cnt2_reg;
 #else /*  little endian */
-	u8	FUNC_ADDR_REG;
+	u8	func_addr_reg;
 	u8	res1[3];
-	u8	PWR_REG;
+	u8	pwr_reg;
 	u8	res2[3];
-	u8	EP_INT_REG;
+	u8	ep_int_reg;
 	u8	res3[15];
-	u8	USB_INT_REG;
+	u8	usb_int_reg;
 	u8	res4[3];
-	u8	EP_INT_EN_REG;
+	u8	ep_int_en_reg;
 	u8	res5[15];
-	u8	USB_INT_EN_REG;
+	u8	usb_int_en_reg;
 	u8	res6[3];
-	u8	FRAME_NUM1_REG;
+	u8	frame_num1_reg;
 	u8	res7[3];
-	u8	FRAME_NUM2_REG;
+	u8	frame_num2_reg;
 	u8	res8[3];
-	u8	INDEX_REG;
+	u8	index_reg;
 	u8	res9[7];
-	u8	MAXP_REG;
+	u8	maxp_reg;
 	u8	res10[7];
-	u8	EP0_CSR_IN_CSR1_REG;
+	u8	ep0_csr_in_csr1_reg;
 	u8	res11[3];
-	u8	IN_CSR2_REG;
+	u8	in_csr2_reg;
 	u8	res12[3];
-	u8	OUT_CSR1_REG;
+	u8	out_csr1_reg;
 	u8	res13[7];
-	u8	OUT_CSR2_REG;
+	u8	out_csr2_reg;
 	u8	res14[3];
-	u8	OUT_FIFO_CNT1_REG;
+	u8	out_fifo_cnt1_reg;
 	u8	res15[3];
-	u8	OUT_FIFO_CNT2_REG;
+	u8	out_fifo_cnt2_reg;
 	u8	res16[3];
 #endif /*  __BIG_ENDIAN */
 	struct s3c24x0_usb_dev_fifos	fifo[5];
@@ -319,18 +338,18 @@ struct s3c24x0_usb_device {
 
 /* WATCH DOG TIMER (see manual chapter 18) */
 struct s3c24x0_watchdog {
-	u32	WTCON;
-	u32	WTDAT;
-	u32	WTCNT;
+	u32	wtcon;
+	u32	wtdat;
+	u32	wtcnt;
 };
 
 
 /* IIC (see manual chapter 20) */
 struct s3c24x0_i2c {
-	u32	IICCON;
-	u32	IICSTAT;
-	u32	IICADD;
-	u32	IICDS;
+	u32	iiccon;
+	u32	iicstat;
+	u32	iicadd;
+	u32	iicds;
 };
 
 
@@ -338,25 +357,25 @@ struct s3c24x0_i2c {
 struct s3c24x0_i2s {
 #ifdef __BIG_ENDIAN
 	u16	res1;
-	u16	IISCON;
+	u16	iiscon;
 	u16	res2;
-	u16	IISMOD;
+	u16	iismod;
 	u16	res3;
-	u16	IISPSR;
+	u16	iispsr;
 	u16	res4;
-	u16	IISFCON;
+	u16	iisfcon;
 	u16	res5;
-	u16	IISFIFO;
+	u16	iisfifo;
 #else /*  little endian */
-	u16	IISCON;
+	u16	iiscon;
 	u16	res1;
-	u16	IISMOD;
+	u16	iismod;
 	u16	res2;
-	u16	IISPSR;
+	u16	iispsr;
 	u16	res3;
-	u16	IISFCON;
+	u16	iisfcon;
 	u16	res4;
-	u16	IISFIFO;
+	u16	iisfifo;
 	u16	res5;
 #endif
 };
@@ -365,87 +384,146 @@ struct s3c24x0_i2s {
 /* I/O PORT (see manual chapter 9) */
 struct s3c24x0_gpio {
 #ifdef CONFIG_S3C2400
-	u32	PACON;
-	u32	PADAT;
+	u32	pacon;
+	u32	padat;
 
-	u32	PBCON;
-	u32	PBDAT;
-	u32	PBUP;
+	u32	pbcon;
+	u32	pbdat;
+	u32	pbup;
 
-	u32	PCCON;
-	u32	PCDAT;
-	u32	PCUP;
+	u32	pccon;
+	u32	pcdat;
+	u32	pcup;
 
-	u32	PDCON;
-	u32	PDDAT;
-	u32	PDUP;
+	u32	pdcon;
+	u32	pddat;
+	u32	pdup;
 
-	u32	PECON;
-	u32	PEDAT;
-	u32	PEUP;
+	u32	pecon;
+	u32	pedat;
+	u32	peup;
 
-	u32	PFCON;
-	u32	PFDAT;
-	u32	PFUP;
+	u32	pfcon;
+	u32	pfdat;
+	u32	pfup;
 
-	u32	PGCON;
-	u32	PGDAT;
-	u32	PGUP;
+	u32	pgcon;
+	u32	pgdat;
+	u32	pgup;
 
-	u32	OPENCR;
+	u32	opencr;
 
-	u32	MISCCR;
-	u32	EXTINT;
+	u32	misccr;
+	u32	extint;
 #endif
 #ifdef CONFIG_S3C2410
-	u32	GPACON;
-	u32	GPADAT;
+	u32	gpacon;
+	u32	gpadat;
+	u32	res1[2];
+	u32	gpbcon;
+	u32	gpbdat;
+	u32	gpbup;
+	u32	res2;
+	u32	gpccon;
+	u32	gpcdat;
+	u32	gpcup;
+	u32	res3;
+	u32	gpdcon;
+	u32	gpddat;
+	u32	gpdup;
+	u32	res4;
+	u32	gpecon;
+	u32	gpedat;
+	u32	gpeup;
+	u32	res5;
+	u32	gpfcon;
+	u32	gpfdat;
+	u32	gpfup;
+	u32	res6;
+	u32	gpgcon;
+	u32	gpgdat;
+	u32	gpgup;
+	u32	res7;
+	u32	gphcon;
+	u32	gphdat;
+	u32	gphup;
+	u32	res8;
+
+	u32	misccr;
+	u32	dclkcon;
+	u32	extint0;
+	u32	extint1;
+	u32	extint2;
+	u32	eintflt0;
+	u32	eintflt1;
+	u32	eintflt2;
+	u32	eintflt3;
+	u32	eintmask;
+	u32	eintpend;
+	u32	gstatus0;
+	u32	gstatus1;
+	u32	gstatus2;
+	u32	gstatus3;
+	u32	gstatus4;
+#endif
+#if defined(CONFIG_S3C2440)
+	u32	gpacon;
+	u32	gpadat;
 	u32	res1[2];
-	u32	GPBCON;
-	u32	GPBDAT;
-	u32	GPBUP;
+	u32	gpbcon;
+	u32	gpbdat;
+	u32	gpbup;
 	u32	res2;
-	u32	GPCCON;
-	u32	GPCDAT;
-	u32	GPCUP;
+	u32	gpccon;
+	u32	gpcdat;
+	u32	gpcup;
 	u32	res3;
-	u32	GPDCON;
-	u32	GPDDAT;
-	u32	GPDUP;
+	u32	gpdcon;
+	u32	gpddat;
+	u32	gpdup;
 	u32	res4;
-	u32	GPECON;
-	u32	GPEDAT;
-	u32	GPEUP;
+	u32	gpecon;
+	u32	gpedat;
+	u32	gpeup;
 	u32	res5;
-	u32	GPFCON;
-	u32	GPFDAT;
-	u32	GPFUP;
+	u32	gpfcon;
+	u32	gpfdat;
+	u32	gpfup;
 	u32	res6;
-	u32	GPGCON;
-	u32	GPGDAT;
-	u32	GPGUP;
+	u32	gpgcon;
+	u32	gpgdat;
+	u32	gpgup;
 	u32	res7;
-	u32	GPHCON;
-	u32	GPHDAT;
-	u32	GPHUP;
+	u32	gphcon;
+	u32	gphdat;
+	u32	gphup;
 	u32	res8;
 
-	u32	MISCCR;
-	u32	DCLKCON;
-	u32	EXTINT0;
-	u32	EXTINT1;
-	u32	EXTINT2;
-	u32	EINTFLT0;
-	u32	EINTFLT1;
-	u32	EINTFLT2;
-	u32	EINTFLT3;
-	u32	EINTMASK;
-	u32	EINTPEND;
-	u32	GSTATUS0;
-	u32	GSTATUS1;
-	u32	GSTATUS2;
-	u32	GSTATUS3;
-	u32	GSTATUS4;
+	u32	misccr;
+	u32	dclkcon;
+	u32	extint0;
+	u32	extint1;
+	u32	extint2;
+	u32	eintflt0;
+	u32	eintflt1;
+	u32	eintflt2;
+	u32	eintflt3;
+	u32	eintmask;
+	u32	eintpend;
+	u32	gstatus0;
+	u32	gstatus1;
+	u32	gstatus2;
+	u32	gstatus3;
+	u32	gstatus4;
+
+	u32	res9;
+	u32	dsc0;
+	u32	dsc1;
+	u32	mslcon;
+	u32	gpjcon;
+	u32	gpjdat;
+	u32	gpjup;
+	u32	res10;
 #endif
 };
 
@@ -454,74 +532,74 @@ struct s3c24x0_gpio {
 struct s3c24x0_rtc {
 #ifdef __BIG_ENDIAN
 	u8	res1[67];
-	u8	RTCCON;
+	u8	rtccon;
 	u8	res2[3];
-	u8	TICNT;
+	u8	ticnt;
 	u8	res3[11];
-	u8	RTCALM;
+	u8	rtcalm;
 	u8	res4[3];
-	u8	ALMSEC;
+	u8	almsec;
 	u8	res5[3];
-	u8	ALMMIN;
+	u8	almmin;
 	u8	res6[3];
-	u8	ALMHOUR;
+	u8	almhour;
 	u8	res7[3];
-	u8	ALMDATE;
+	u8	almdate;
 	u8	res8[3];
-	u8	ALMMON;
+	u8	almmon;
 	u8	res9[3];
-	u8	ALMYEAR;
+	u8	almyear;
 	u8	res10[3];
-	u8	RTCRST;
+	u8	rtcrst;
 	u8	res11[3];
-	u8	BCDSEC;
+	u8	bcdsec;
 	u8	res12[3];
-	u8	BCDMIN;
+	u8	bcdmin;
 	u8	res13[3];
-	u8	BCDHOUR;
+	u8	bcdhour;
 	u8	res14[3];
-	u8	BCDDATE;
+	u8	bcddate;
 	u8	res15[3];
-	u8	BCDDAY;
+	u8	bcdday;
 	u8	res16[3];
-	u8	BCDMON;
+	u8	bcdmon;
 	u8	res17[3];
-	u8	BCDYEAR;
+	u8	bcdyear;
 #else /*  little endian */
 	u8	res0[64];
-	u8	RTCCON;
+	u8	rtccon;
 	u8	res1[3];
-	u8	TICNT;
+	u8	ticnt;
 	u8	res2[11];
-	u8	RTCALM;
+	u8	rtcalm;
 	u8	res3[3];
-	u8	ALMSEC;
+	u8	almsec;
 	u8	res4[3];
-	u8	ALMMIN;
+	u8	almmin;
 	u8	res5[3];
-	u8	ALMHOUR;
+	u8	almhour;
 	u8	res6[3];
-	u8	ALMDATE;
+	u8	almdate;
 	u8	res7[3];
-	u8	ALMMON;
+	u8	almmon;
 	u8	res8[3];
-	u8	ALMYEAR;
+	u8	almyear;
 	u8	res9[3];
-	u8	RTCRST;
+	u8	rtcrst;
 	u8	res10[3];
-	u8	BCDSEC;
+	u8	bcdsec;
 	u8	res11[3];
-	u8	BCDMIN;
+	u8	bcdmin;
 	u8	res12[3];
-	u8	BCDHOUR;
+	u8	bcdhour;
 	u8	res13[3];
-	u8	BCDDATE;
+	u8	bcddate;
 	u8	res14[3];
-	u8	BCDDAY;
+	u8	bcdday;
 	u8	res15[3];
-	u8	BCDMON;
+	u8	bcdmon;
 	u8	res16[3];
-	u8	BCDYEAR;
+	u8	bcdyear;
 	u8	res17[3];
 #endif
 };
@@ -529,34 +607,34 @@ struct s3c24x0_rtc {
 
 /* ADC (see manual chapter 16) */
 struct s3c2400_adc {
-	u32	ADCCON;
-	u32	ADCDAT;
+	u32	adccon;
+	u32	adcdat;
 };
 
 
 /* ADC (see manual chapter 16) */
 struct s3c2410_adc {
-	u32	ADCCON;
-	u32	ADCTSC;
-	u32	ADCDLY;
-	u32	ADCDAT0;
-	u32	ADCDAT1;
+	u32	adccon;
+	u32	adctsc;
+	u32	adcdly;
+	u32	adcdat0;
+	u32	adcdat1;
 };
 
 
 /* SPI (see manual chapter 22) */
 struct s3c24x0_spi_channel {
-	u8	SPCON;
+	u8	spcon;
 	u8	res1[3];
-	u8	SPSTA;
+	u8	spsta;
 	u8	res2[3];
-	u8	SPPIN;
+	u8	sppin;
 	u8	res3[3];
-	u8	SPPRE;
+	u8	sppre;
 	u8	res4[3];
-	u8	SPTDAT;
+	u8	sptdat;
 	u8	res5[3];
-	u8	SPRDAT;
+	u8	sprdat;
 	u8	res6[3];
 	u8	res7[16];
 };
@@ -570,53 +648,53 @@ struct s3c24x0_spi {
 struct s3c2400_mmc {
 #ifdef __BIG_ENDIAN
 	u8	res1[3];
-	u8	MMCON;
+	u8	mmcon;
 	u8	res2[3];
-	u8	MMCRR;
+	u8	mmcrr;
 	u8	res3[3];
-	u8	MMFCON;
+	u8	mmfcon;
 	u8	res4[3];
-	u8	MMSTA;
+	u8	mmsta;
 	u16	res5;
-	u16	MMFSTA;
+	u16	mmfsta;
 	u8	res6[3];
-	u8	MMPRE;
+	u8	mmpre;
 	u16	res7;
-	u16	MMLEN;
+	u16	mmlen;
 	u8	res8[3];
-	u8	MMCR7;
-	u32	MMRSP[4];
+	u8	mmcr7;
+	u32	mmrsp[4];
 	u8	res9[3];
-	u8	MMCMD0;
-	u32	MMCMD1;
+	u8	mmcmd0;
+	u32	mmcmd1;
 	u16	res10;
-	u16	MMCR16;
+	u16	mmcr16;
 	u8	res11[3];
-	u8	MMDAT;
+	u8	mmdat;
 #else
-	u8	MMCON;
+	u8	mmcon;
 	u8	res1[3];
-	u8	MMCRR;
+	u8	mmcrr;
 	u8	res2[3];
-	u8	MMFCON;
+	u8	mmfcon;
 	u8	res3[3];
-	u8	MMSTA;
+	u8	mmsta;
 	u8	res4[3];
-	u16	MMFSTA;
+	u16	mmfsta;
 	u16	res5;
-	u8	MMPRE;
+	u8	mmpre;
 	u8	res6[3];
-	u16	MMLEN;
+	u16	mmlen;
 	u16	res7;
-	u8	MMCR7;
+	u8	mmcr7;
 	u8	res8[3];
-	u32	MMRSP[4];
-	u8	MMCMD0;
+	u32	mmrsp[4];
+	u8	mmcmd0;
 	u8	res9[3];
-	u32	MMCMD1;
-	u16	MMCR16;
+	u32	mmcmd1;
+	u16	mmcr16;
 	u16	res10;
-	u8	MMDAT;
+	u8	mmdat;
 	u8	res11[3];
 #endif
 };
@@ -624,29 +702,29 @@ struct s3c2400_mmc {
 
 /* SD INTERFACE (see S3C2410 manual chapter 19) */
 struct s3c2410_sdi {
-	u32	SDICON;
-	u32	SDIPRE;
-	u32	SDICARG;
-	u32	SDICCON;
-	u32	SDICSTA;
-	u32	SDIRSP0;
-	u32	SDIRSP1;
-	u32	SDIRSP2;
-	u32	SDIRSP3;
-	u32	SDIDTIMER;
-	u32	SDIBSIZE;
-	u32	SDIDCON;
-	u32	SDIDCNT;
-	u32	SDIDSTA;
-	u32	SDIFSTA;
+	u32	sdicon;
+	u32	sdipre;
+	u32	sdicarg;
+	u32	sdiccon;
+	u32	sdicsta;
+	u32	sdirsp0;
+	u32	sdirsp1;
+	u32	sdirsp2;
+	u32	sdirsp3;
+	u32	sdidtimer;
+	u32	sdibsize;
+	u32	sdidcon;
+	u32	sdidcnt;
+	u32	sdidsta;
+	u32	sdifsta;
 #ifdef __BIG_ENDIAN
 	u8	res[3];
-	u8	SDIDAT;
+	u8	sdidat;
 #else
-	u8	SDIDAT;
+	u8	sdidat;
 	u8	res[3];
 #endif
-	u32	SDIIMSK;
+	u32	sdiimsk;
 };
 
 #endif /*__S3C24X0_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
index c37d4a108d7ad986cb92b3ae1d2775a1da93d74e..54184c460bb91d55a21d0679be72b53242a08b1a 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
@@ -22,6 +22,8 @@
 	#include <asm/arch/s3c2400.h>
 #elif defined CONFIG_S3C2410
 	#include <asm/arch/s3c2410.h>
+#elif defined CONFIG_S3C2440
+	#include <asm/arch/s3c2440.h>
 #else
 	#error Please define the s3c24x0 cpu type
 #endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index 68c59d13e3406223d73815220a7753153f010696..48de64d9c3532f864cffdcf2d0b0dea32a9c942e 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -65,7 +65,7 @@ struct mmc_host {
 	unsigned int clock;	/* Current clock (MHz) */
 };
 
-int s5p_mmc_init(int dev_index);
+int s5p_mmc_init(int dev_index, int bus_width);
 
 #endif	/* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h
index 2d7ad7ec987ff1f7f900c7ba5a052eae72b50ce9..f6eeab45cdc23f4fe7da73226b72f80f52d37ff5 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/uart.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/uart.h
@@ -24,6 +24,12 @@
 #define __ASM_ARCH_UART_H_
 
 #ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+	unsigned short	slot;		/* udivslot */
+	unsigned char	value;		/* ufracval */
+};
+
 struct s5p_uart {
 	unsigned int	ulcon;
 	unsigned int	ucon;
@@ -38,10 +44,12 @@ struct s5p_uart {
 	unsigned char	urxh;
 	unsigned char	res2[3];
 	unsigned int	ubrdiv;
-	unsigned short	udivslot;
-	unsigned char	res3[2];
-	unsigned char	res4[0x3d0];
+	union br_rest	rest;
+	unsigned char	res3[0x3d0];
 };
+
+static int use_divslot = 1;
+
 #endif	/* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 4124f0a9922e25d0d919e871107648bf859fd4fd..c60dba26bfaf2efdb7d420e01dccd6fa4ddf4b09 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -21,9 +21,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-/* Relocation to SDRAM works on all ARM boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 6dae4328e68e2c12a95dda30f701fd65dd47c396..ada3fbb6415cfe6d5a6d7b032743971c9e5be9c7 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -30,7 +30,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
@@ -61,7 +61,6 @@ typedef	struct	global_data {
 	unsigned long	tbu;
 	unsigned long long	timer_reset_value;
 #endif
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	mon_len;	/* monitor len */
@@ -70,7 +69,6 @@ typedef	struct	global_data {
 	unsigned long	reloc_off;
 #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
 	unsigned long	tlb_addr;
-#endif
 #endif
 	void		**jt;		/* jump table */
 	char		env_buf[32];	/* buffer for getenv() before reloc. */
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index 4ac4f612e940ff5d6d8ffde6b0dc9d77aae43e6d..33973a32e0b029ce61fb201d9cd3ea7e5b801221 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -34,16 +34,12 @@ extern ulong _bss_start_ofs;	/* BSS start relative to _start */
 extern ulong _bss_end_ofs;		/* BSS end relative to _start */
 extern ulong IRQ_STACK_START;	/* top of IRQ stack */
 extern ulong FIQ_STACK_START;	/* top of FIQ stack */
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-extern ulong _armboot_start_ofs;	/* code start */
-#else
 extern ulong _TEXT_BASE;	/* code start */
 extern ulong _datarel_start_ofs;
 extern ulong _datarelrolocal_start_ofs;
 extern ulong _datarellocal_start_ofs;
 extern ulong _datarelro_start_ofs;
 extern ulong IRQ_STACK_START_IN;	/* 8 bytes in IRQ stack */
-#endif
 
 /* cpu/.../cpu.c */
 int	cpu_init(void);
@@ -56,9 +52,7 @@ int	arch_misc_init(void);
 /* board/.../... */
 int	board_init(void);
 int	dram_init (void);
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 void	dram_init_banksize (void);
-#endif
 void	setup_serial_tag (struct tag **params);
 void	setup_revision_tag (struct tag **params);
 
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index ffe261bd4457e0eb9be0e74609c5efd5b09725ad..1fd5f8362f7a3e1a076c44e9f554e6c0297dfdb0 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -127,11 +127,7 @@ static int init_baudrate (void)
 	char tmp[64];	/* long enough for environment variables */
 	int i = getenv_f("baudrate", tmp, sizeof (tmp));
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	gd->baudrate = (i > 0)
-#else
-	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
-#endif
 			? (int) simple_strtoul (tmp, NULL, 10)
 			: CONFIG_BAUDRATE;
 
@@ -142,11 +138,7 @@ static int display_banner (void)
 {
 	printf ("\n\n%s\n\n", version_string);
 	debug ("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	       _TEXT_BASE,
-#else
-	       _armboot_start,
-#endif
 	       _bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
 #ifdef CONFIG_MODEM_SUPPORT
 	debug ("Modem Support enabled\n");
@@ -190,16 +182,6 @@ static int display_dram_config (void)
 	return (0);
 }
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-#ifndef CONFIG_SYS_NO_FLASH
-static void display_flash_config (ulong size)
-{
-	puts ("Flash: ");
-	print_size (size, "\n");
-}
-#endif /* CONFIG_SYS_NO_FLASH */
-#endif
-
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 static int init_func_i2c (void)
 {
@@ -246,214 +228,6 @@ typedef int (init_fnc_t) (void);
 
 int print_cpuinfo (void);
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-init_fnc_t *init_sequence[] = {
-#if defined(CONFIG_ARCH_CPU_INIT)
-	arch_cpu_init,		/* basic arch cpu dependent setup */
-#endif
-	board_init,		/* basic board dependent setup */
-#if defined(CONFIG_USE_IRQ)
-	interrupt_init,		/* set up exceptions */
-#endif
-	timer_init,		/* initialize timer */
-#ifdef CONFIG_FSL_ESDHC
-	get_clocks,
-#endif
-	env_init,		/* initialize environment */
-	init_baudrate,		/* initialze baudrate settings */
-	serial_init,		/* serial communications setup */
-	console_init_f,		/* stage 1 init of console */
-	display_banner,		/* say that we are here */
-#if defined(CONFIG_DISPLAY_CPUINFO)
-	print_cpuinfo,		/* display cpu info (and speed) */
-#endif
-#if defined(CONFIG_DISPLAY_BOARDINFO)
-	checkboard,		/* display board info */
-#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
-	init_func_i2c,
-#endif
-	dram_init,		/* configure available RAM banks */
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
-	arm_pci_init,
-#endif
-	display_dram_config,
-	NULL,
-};
-
-void start_armboot (void)
-{
-	init_fnc_t **init_fnc_ptr;
-	char *s;
-#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
-	unsigned long addr;
-#endif
-
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t*)(_armboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("": : :"memory");
-
-	memset ((void*)gd, 0, sizeof (gd_t));
-	gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
-	memset (gd->bd, 0, sizeof (bd_t));
-
-	gd->flags |= GD_FLG_RELOC;
-
-	monitor_flash_len = _bss_start - _armboot_start;
-
-	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-		if ((*init_fnc_ptr)() != 0) {
-			hang ();
-		}
-	}
-
-	/* armboot_start is defined in the board-specific linker script */
-	mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN,
-			CONFIG_SYS_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
-	/* configure available FLASH banks */
-	display_flash_config (flash_init ());
-#endif /* CONFIG_SYS_NO_FLASH */
-
-#ifdef CONFIG_VFD
-#	ifndef PAGE_SIZE
-#	  define PAGE_SIZE 4096
-#	endif
-	/*
-	 * reserve memory for VFD display (always full pages)
-	 */
-	/* bss_end is defined in the board-specific linker script */
-	addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-	vfd_setmem (addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_VFD */
-
-#ifdef CONFIG_LCD
-	/* board init may have inited fb_base */
-	if (!gd->fb_base) {
-#		ifndef PAGE_SIZE
-#		  define PAGE_SIZE 4096
-#		endif
-		/*
-		 * reserve memory for LCD display (always full pages)
-		 */
-		/* bss_end is defined in the board-specific linker script */
-		addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-		lcd_setmem (addr);
-		gd->fb_base = addr;
-	}
-#endif /* CONFIG_LCD */
-
-#if defined(CONFIG_CMD_NAND)
-	puts ("NAND:  ");
-	nand_init();		/* go init the NAND */
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-	onenand_init();
-#endif
-
-#ifdef CONFIG_HAS_DATAFLASH
-	AT91F_DataflashInit();
-	dataflash_print_info();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-/*
- * MMC initialization is called before relocating env.
- * Thus It is required that operations like pin multiplexer
- * be put in board_init.
- */
-	puts ("MMC:   ");
-	mmc_initialize (gd->bd);
-#endif
-
-	/* initialize environment */
-	env_relocate ();
-
-#ifdef CONFIG_VFD
-	/* must do this after the framebuffer is allocated */
-	drv_vfd_init();
-#endif /* CONFIG_VFD */
-
-#ifdef CONFIG_SERIAL_MULTI
-	serial_initialize();
-#endif
-
-	/* IP Address */
-	gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
-
-	stdio_init ();	/* get the devices list going. */
-
-	jumptable_init ();
-
-#if defined(CONFIG_API)
-	/* Initialize API */
-	api_init ();
-#endif
-
-	console_init_r ();	/* fully init console as a device */
-
-#if defined(CONFIG_ARCH_MISC_INIT)
-	/* miscellaneous arch dependent initialisations */
-	arch_misc_init ();
-#endif
-#if defined(CONFIG_MISC_INIT_R)
-	/* miscellaneous platform dependent initialisations */
-	misc_init_r ();
-#endif
-
-	/* enable exceptions */
-	enable_interrupts ();
-
-	/* Perform network card initialisation if necessary */
-
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
-	/* XXX: this needs to be moved to board init */
-	if (getenv ("ethaddr")) {
-		uchar enetaddr[6];
-		eth_getenv_enetaddr("ethaddr", enetaddr);
-		smc_set_mac_addr(enetaddr);
-	}
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
-	/* Initialize from environment */
-	if ((s = getenv ("loadaddr")) != NULL) {
-		load_addr = simple_strtoul (s, NULL, 16);
-	}
-#if defined(CONFIG_CMD_NET)
-	if ((s = getenv ("bootfile")) != NULL) {
-		copy_filename (BootFile, s, sizeof (BootFile));
-	}
-#endif
-
-#ifdef BOARD_LATE_INIT
-	board_late_init ();
-#endif
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-#if defined(CONFIG_NET_MULTI)
-	puts ("Net:   ");
-#endif
-	eth_initialize(gd->bd);
-#if defined(CONFIG_RESET_PHY_R)
-	debug ("Reset Ethernet PHY\n");
-	reset_phy();
-#endif
-#endif
-	/* main_loop() can return to retry autoboot, if so just run it again. */
-	for (;;) {
-		main_loop ();
-	}
-
-	/* NOTREACHED - no way out of command loop except booting */
-}
-#else
 void __dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
@@ -678,15 +452,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	ulong malloc_start;
 #if !defined(CONFIG_SYS_NO_FLASH)
 	ulong flash_size;
-#endif
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
-	extern void malloc_bin_reloc (void);
-#if defined(CONFIG_CMD_BMP)
-	extern void bmp_reloc(void);
-#endif
-#if defined(CONFIG_CMD_I2C)
-	extern void i2c_reloc(void);
-#endif
 #endif
 
 	gd = id;
@@ -704,36 +469,16 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
-	/*
-	 * We have to relocate the command table manually
-	 */
-	fixup_cmdtable(&__u_boot_cmd_start,
-		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#if defined(CONFIG_CMD_BMP)
-	bmp_reloc();
-#endif
-#if defined(CONFIG_CMD_I2C)
-	i2c_reloc();
-#endif
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
-
 #ifdef CONFIG_LOGBUFFER
 	logbuff_init_ptrs ();
 #endif
 #ifdef CONFIG_POST
 	post_output_backlog ();
-#ifndef CONFIG_RELOC_FIXUP_WORKS
-	post_reloc ();
-#endif
 #endif
 
 	/* The Malloc area is immediately below the monitor copy in DRAM */
 	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
 	mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
-	malloc_bin_reloc ();
-#endif
 
 #if !defined(CONFIG_SYS_NO_FLASH)
 	puts ("FLASH: ");
@@ -897,8 +642,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/* NOTREACHED - no way out of command loop except booting */
 }
 
-#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
 void hang (void)
 {
 	puts ("### ERROR ### Please RESET the board ###\n");
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 2e7b2e1f33f27b472cbf30528301be67ff9733fb..a1649eef0d1a905cf4a4fe6db13da8588e62a63e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -177,8 +177,6 @@ static int fixup_memory_node(void *blob)
 static int bootm_linux_fdt(int machid, bootm_headers_t *images)
 {
 	ulong rd_len;
-	bd_t *bd = gd->bd;
-	char *s;
 	void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
 	ulong bootmap_base = getenv_bootm_low();
 	ulong of_size = images->ft_len;
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index fe6d45987bf32dde88c3e346c3b772c07ba1fae0..d9175f058327fabf4f91ee0d751a043e4b0c0133 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -44,7 +44,6 @@ static void cp_delay (void)
 	asm volatile("" : : : "memory");
 }
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 static inline void dram_bank_mmu_setup(int bank)
 {
 	u32 *page_table = (u32 *)gd->tlb_addr;
@@ -58,18 +57,11 @@ static inline void dram_bank_mmu_setup(int bank)
 		page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
 	}
 }
-#endif
 
 /* to activate the MMU we need to set up virtual memory: use 1M areas */
 static inline void mmu_setup(void)
 {
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	u32 *page_table = (u32 *)gd->tlb_addr;
-#else
-	static u32 __attribute__((aligned(16384))) page_table[4096];
-	bd_t *bd = gd->bd;
-	int j;
-#endif
 	int i;
 	u32 reg;
 
@@ -77,20 +69,9 @@ static inline void mmu_setup(void)
 	for (i = 0; i < 4096; i++)
 		page_table[i] = i << 20 | (3 << 10) | 0x12;
 
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		dram_bank_mmu_setup(i);
 	}
-#else
-	/* Then, enable cacheable and bufferable for RAM only */
-	for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
-		for (i = bd->bi_dram[j].start >> 20;
-			i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
-			i++) {
-			page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
-		}
-	}
-#endif
 
 	/* Copy the page table address to cp15 */
 	asm volatile("mcr p15, 0, %0, c2, c0, 0"
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 9a21e7b40a02629fcffb2a03bef549f074cde954..74ff5ce1c442564303ae09944f543517e5f3ce6e 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -46,12 +46,8 @@ int interrupt_init (void)
 	/*
 	 * setup up stacks if necessary
 	 */
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	IRQ_STACK_START = gd->irq_sp - 4;
 	IRQ_STACK_START_IN = gd->irq_sp + 8;
-#else
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-#endif
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 
 	return arch_interrupt_init();
@@ -86,7 +82,6 @@ int disable_interrupts (void)
 	return (old & 0x80) == 0;
 }
 #else
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 int interrupt_init (void)
 {
 	/*
@@ -96,7 +91,6 @@ int interrupt_init (void)
 
 	return 0;
 }
-#endif
 
 void enable_interrupts (void)
 {
diff --git a/arch/avr32/cpu/start.S b/arch/avr32/cpu/start.S
index 06bf4c692d8e4d848d93d06689bd67a446091242..97140e93ebb8fa2917375e5dbd1585f47764d8c7 100644
--- a/arch/avr32/cpu/start.S
+++ b/arch/avr32/cpu/start.S
@@ -19,6 +19,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/ptrace.h>
 #include <asm/sysreg.h>
diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h
index 049c44eaf84de0ce67d86afcf0cd016d4bd6c407..02fbfb3abfea8ae55e4aef175d3e4e525cef5a79 100644
--- a/arch/avr32/include/asm/config.h
+++ b/arch/avr32/include/asm/config.h
@@ -21,4 +21,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_NEEDS_MANUAL_RELOC
+
 #endif
diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h
index 5a7aed94e1460d34b0fafb2a7bdf90588bb6ef56..4ef8fc570f34524691e59a6f03da60e2dac1fe92 100644
--- a/arch/avr32/include/asm/global_data.h
+++ b/arch/avr32/include/asm/global_data.h
@@ -29,7 +29,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index 96ccc7fa795921ab2acda61805cfccb7e24d79a3..8b56237f1893d705807ad5735c0e0d78664ca9fd 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -272,13 +272,13 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 
 	monitor_flash_len = _edata - _text;
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	/*
 	 * We have to relocate the command table manually
 	 */
 	fixup_cmdtable(&__u_boot_cmd_start,
 		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 	/* there are some other pointer constants we must deal with */
 #ifndef CONFIG_ENV_IS_NOWHERE
diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk
index a3300841a0c3bb4349b3cd58353f94bae0febfe3..ab117ca5ad5227314b4619dc310d7d47413a5847 100644
--- a/arch/blackfin/config.mk
+++ b/arch/blackfin/config.mk
@@ -26,8 +26,6 @@ CROSS_COMPILE ?= bfin-uclinux-
 STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin
 
 CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
-CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET)))
-CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE)))
 
 PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 215e0f29183fbb51e0631b0d9c28d68a6e71e8fb..04372525cc2470f8bb0141945e6675e7863a9d57 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -9,13 +9,13 @@
 #ifndef __ASM_BLACKFIN_CONFIG_POST_H__
 #define __ASM_BLACKFIN_CONFIG_POST_H__
 
+/* Some of our defines use this (like CONFIG_SYS_GBL_DATA_ADDR) */
+#include <asm-offsets.h>
+
 #ifndef CONFIG_BFIN_SCRATCH_REG
 # define CONFIG_BFIN_SCRATCH_REG retn
 #endif
 
-/* Relocation to SDRAM works on all Blackfin boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
 /* Make sure the structure is properly aligned */
 #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
 # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
@@ -101,11 +101,8 @@
 #ifndef CONFIG_SYS_MALLOC_BASE
 # define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
 #endif
-#ifndef CONFIG_SYS_GBL_DATA_SIZE
-# define CONFIG_SYS_GBL_DATA_SIZE (128)
-#endif
 #ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
 #endif
 #ifndef CONFIG_STACKBASE
 # define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index d5514b0dffb17737fa67ccd6545df3bf36bcf8d1..eba5e93e212c0199be859697d3dcc5057cf9b752 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -37,7 +37,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 typedef struct global_data {
 	bd_t *bd;
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index fcfd1746a59f78dd872ae8319f98e4c070c7f57d..8eca7d6fb64d4cd1490c3c1063e16e774ca6c82d 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -237,12 +237,12 @@ void board_init_f(ulong bootflag)
 #endif
 
 #ifdef DEBUG
-	if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd))
+	if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
 		hang();
 #endif
 	serial_early_puts("Init global data\n");
 	gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
-	memset((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
 
 	/* Board data initialization */
 	addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t));
diff --git a/arch/i386/include/asm/config.h b/arch/i386/include/asm/config.h
index 1952de79f8ae121030414d64ffb7c3f919be27d7..049c44eaf84de0ce67d86afcf0cd016d4bd6c407 100644
--- a/arch/i386/include/asm/config.h
+++ b/arch/i386/include/asm/config.h
@@ -21,6 +21,4 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_RELOC_FIXUP_WORKS
-
 #endif
diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h
index 597112318f567d373d2d85df459f66ff8b9df208..e3f8a25efb600352cd139756f0ae51a18f52d289 100644
--- a/arch/i386/include/asm/global_data.h
+++ b/arch/i386/include/asm/global_data.h
@@ -30,7 +30,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 #ifndef __ASSEMBLY__
diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index ac710969bba05b918e7acaace5962f6608f1d2d6..d09d49274ebc188c6e864483c9ff7d3d5357f457 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 20b50e7579e0e79f7525636aac8b5bf122a8570a..a726b59846dc2a16ed6997d5554d38cac50e841e 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index d1f3d83270f71a8a3f5456325830a5796ed3fa86..f0cfa6ffe059ebe28940eb5994d9fca89ec2ea63 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index a80b0a99464bdd4847a1ac076e4f9e5dcd7ef1a0..53ac471a416905352622ed16581eb174d004a516 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -24,6 +24,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index 8b69d1f46b3dff7de70bf356adc7bd1a9e8db691..5255f374d5e6b3ec8977d8b38cd9728dd7982210 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index 84118629e27a7cd349eafc5a73d77f419344e451..e30923fac7f33c24ea3987e50dcdebf064dc60c1 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
index ec2cc16bebaa395d649bfcfaf77dd8cfccf8f0b6..51050a39a3e99b7b4bd03531142a1f7f4b39e11c 100644
--- a/arch/m68k/include/asm/config.h
+++ b/arch/m68k/include/asm/config.h
@@ -21,6 +21,8 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_NEEDS_MANUAL_RELOC
+
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_SYS_BOOT_GET_CMDLINE
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index 3a36f8225486ba992dad65a4ea2399e567b7d12b..fc486fda58ddf52f00f857380f4f8f498b7574b8 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -30,7 +30,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
index 4541e244e12e665541409566e1dbec84463787c7..9a519088582145e338774762f7c24c5c0c001386 100644
--- a/arch/m68k/lib/board.c
+++ b/arch/m68k/lib/board.c
@@ -341,7 +341,7 @@ board_init_f (ulong bootflag)
 	bd->bi_memsize   = gd->ram_size;	/* size  of  DRAM memory in bytes */
 #ifdef CONFIG_SYS_INIT_RAM_ADDR
 	bd->bi_sramstart = CONFIG_SYS_INIT_RAM_ADDR;	/* start of  SRAM memory	*/
-	bd->bi_sramsize  = CONFIG_SYS_INIT_RAM_END;	/* size  of  SRAM memory	*/
+	bd->bi_sramsize  = CONFIG_SYS_INIT_RAM_SIZE;	/* size  of  SRAM memory	*/
 #endif
 	bd->bi_mbar_base = CONFIG_SYS_MBAR;		/* base of internal registers */
 
@@ -420,13 +420,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	monitor_flash_len = (ulong)&__init_end - dest_addr;
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	/*
 	 * We have to relocate the command table manually
 	 */
 	fixup_cmdtable(&__u_boot_cmd_start,
 		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 	/* there are some other pointer constants we must deal with */
 #ifndef CONFIG_ENV_IS_NOWHERE
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 98c248fdb3cfdf07afa1f982d16467522f2cd2ff..93a9efdf1065d72f6cf8f22c2369c0e4b543e609 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -24,6 +24,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 
 	.text
@@ -97,7 +98,7 @@ _start:
 	 * 0xC: 0xB808XXXX
 	 *
 	 * then it is necessary to count address for storing the most significant
-	 * 16bits from _exception_handler address and copy it to 
+	 * 16bits from _exception_handler address and copy it to
 	 * 0xa address. Big endian use offset in r10=0 that's why is it just
 	 * 0xa address. The same is done for the least significant 16 bits
 	 * for 0xe address.
diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h
index 8a9064b3c888565b4ed2492e27139b99cd59fcc7..049c44eaf84de0ce67d86afcf0cd016d4bd6c407 100644
--- a/arch/microblaze/include/asm/config.h
+++ b/arch/microblaze/include/asm/config.h
@@ -21,7 +21,4 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-/* Relocation to SDRAM works on all Microblaze boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
 #endif
diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h
index 03444ef339d707511b67f68a76cb3e94180233f2..557ad27e9d4aec121ea646f8e9baf3875752e102 100644
--- a/arch/microblaze/include/asm/global_data.h
+++ b/arch/microblaze/include/asm/global_data.h
@@ -31,7 +31,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index 84267cd7f5b239127e475d6e7d71bc47de41c1b3..eeef579dcca640e0d5374c7491e7906fd4a9dee1 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -96,7 +96,7 @@ void board_init (void)
 	ulong flash_size = 0;
 #endif
 	asm ("nop");	/* FIXME gd is not initialize - wait */
-	memset ((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
+	memset ((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
 	gd->bd = (bd_t *) (gd + 1);	/* At end of global data */
 	gd->baudrate = CONFIG_BAUDRATE;
 	bd = gd->bd;
diff --git a/arch/mips/cpu/cache.S b/arch/mips/cpu/cache.S
index ff4f11cf7878e9718bb372b1a4dc3c39c0491f67..4b30c89b1481bc1b009cb35d2b5b567c6281916e 100644
--- a/arch/mips/cpu/cache.S
+++ b/arch/mips/cpu/cache.S
@@ -22,6 +22,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/asm.h>
 #include <asm/regdef.h>
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 57db589b94f266e7057ca966a72b6487918cd186..d6bcef6b5624dee914c97bdd39a36021b4967d64 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -22,6 +22,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h
index 049c44eaf84de0ce67d86afcf0cd016d4bd6c407..02fbfb3abfea8ae55e4aef175d3e4e525cef5a79 100644
--- a/arch/mips/include/asm/config.h
+++ b/arch/mips/include/asm/config.h
@@ -21,4 +21,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_NEEDS_MANUAL_RELOC
+
 #endif
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index bf1bfc390f82bc267de60f85e8d8ff8c7ab81608..271a290a51c392926bd41f198997c77c999578d0 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -33,7 +33,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index 4a22f7b41c71c6ce5d6d09c297bf82c5499c068a..f3171241556a9e3ae59eb3b4058d1379cfa00146 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -295,13 +295,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	/*
 	 * We have to relocate the command table manually
 	 */
 	fixup_cmdtable(&__u_boot_cmd_start,
 		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 	/* there are some other pointer constants we must deal with */
 #ifndef CONFIG_ENV_IS_NOWHERE
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S
index 76d3b521547f1d8c793514ea38ea52018dbf9697..9b0f52da566b57594dae96363a99c5487549afba 100644
--- a/arch/nios2/cpu/start.S
+++ b/arch/nios2/cpu/start.S
@@ -21,7 +21,7 @@
  * MA 02111-1307 USA
  */
 
-
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include <version.h>
diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h
index 011d603a4b8342b056e8a1eb249ca585c553dd33..049c44eaf84de0ce67d86afcf0cd016d4bd6c407 100644
--- a/arch/nios2/include/asm/config.h
+++ b/arch/nios2/include/asm/config.h
@@ -21,7 +21,4 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-/* Relocation to SDRAM works on all NIOS2 boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
 #endif
diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
index f83e691a3498219c49e79576b06cbc7f5e7cf391..f6c6bc166b766235059d459b5a2e684e3672fe0f 100644
--- a/arch/nios2/lib/board.c
+++ b/arch/nios2/lib/board.c
@@ -95,7 +95,7 @@ void board_init (void)
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("": : :"memory");
 
-	memset( gd, 0, CONFIG_SYS_GBL_DATA_SIZE );
+	memset( gd, 0, GENERATED_GBL_DATA_SIZE );
 
 	gd->bd = (bd_t *)(gd+1);	/* At end of global data */
 	gd->baudrate = CONFIG_BAUDRATE;
diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S
index 573e6d08219860d51bc5843f8e384e403a50abd3..280781e165d8f669fe1f7bfb8507a99697263493 100644
--- a/arch/powerpc/cpu/74xx_7xx/start.S
+++ b/arch/powerpc/cpu/74xx_7xx/start.S
@@ -32,6 +32,7 @@
  *  board_init lies at a quite high address and when the cpu has
  *  jumped there, everything is ok.
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <74xx_7xx.h>
 #include <timestamp.h>
@@ -819,7 +820,7 @@ lock_ram_in_cache:
 	 */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:
@@ -840,7 +841,7 @@ unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:	icbi	r0, r3
diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S
index 2265c8cc11099ed49e2e34ae76feec0512a4341d..fe35190e796ac4b30f0ff0775e0b0305f00c2385 100644
--- a/arch/powerpc/cpu/mpc512x/start.S
+++ b/arch/powerpc/cpu/mpc512x/start.S
@@ -29,6 +29,7 @@
  *  U-Boot - Startup Code for MPC512x based Embedded Boards
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <timestamp.h>
 #include <version.h>
diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S
index da42557224da101ae06ec6f4cf7f5bd94f56a138..63449c3d4deb5a2f9138cfcee1011eb42e238235 100644
--- a/arch/powerpc/cpu/mpc5xx/start.S
+++ b/arch/powerpc/cpu/mpc5xx/start.S
@@ -30,6 +30,7 @@
  *
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc5xx.h>
 #include <timestamp.h>
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 92858fce3a4e600f91f88632ad4cc27716e44e22..ad546771fa3192f838689b2cde48a8c3ff26207d 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -25,6 +25,7 @@
 /*
  *  U-Boot - Startup Code for MPC5xxx CPUs
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc5xxx.h>
 #include <timestamp.h>
diff --git a/arch/powerpc/cpu/mpc8220/start.S b/arch/powerpc/cpu/mpc8220/start.S
index b5c160b607aae2c81184fbe7d36fbabd6b37824a..b029e84178860cef0a588583e9dd2f9c678e0b4f 100644
--- a/arch/powerpc/cpu/mpc8220/start.S
+++ b/arch/powerpc/cpu/mpc8220/start.S
@@ -25,6 +25,7 @@
 /*
  *  U-Boot - Startup Code for MPC8220 CPUs
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc8220.h>
 #include <timestamp.h>
diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S
index d10231ee9485fc4da9932343f4aa5f7f0b77cd50..616de58fb718ecccee73c7d42865c66570493370 100644
--- a/arch/powerpc/cpu/mpc824x/start.S
+++ b/arch/powerpc/cpu/mpc824x/start.S
@@ -37,6 +37,7 @@
  * board_init will change CS0 to be positioned at the correct
  * address and (s)dram will be positioned at address 0
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc824x.h>
 #include <timestamp.h>
diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S
index 55c64ea60c05ecc72316b877b50abe931590e4bc..521a6399b2be1d146d59c6087af267a9306a1fa5 100644
--- a/arch/powerpc/cpu/mpc8260/start.S
+++ b/arch/powerpc/cpu/mpc8260/start.S
@@ -25,6 +25,7 @@
 /*
  *  U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc8260.h>
 #include <timestamp.h>
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index f01c09a91bf90e7f20cba4d305d1aee0aafb6cc7..7a1cae75da086e8ec443cdf231d75b95e2f50a65 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -329,7 +329,7 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_USB_EHCI_FSL
 #ifndef CONFIG_MPC834x
 	uint32_t temp;
-	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
 
 	/* Configure interface. */
 	setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 536604f46252b586a896ec940d9d8da19cea75d4..a35697da0a73de8c4d1c673f59c1f2790457d792 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -27,6 +27,7 @@
  *  U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc83xx.h>
 #include <timestamp.h>
@@ -1072,7 +1073,7 @@ lock_ram_in_cache:
 	 */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:
@@ -1094,7 +1095,7 @@ unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:	icbi	r0, r3
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 53cefaf002e32c2b22d6913cd7c64019bf427fc0..56a853ee572b70e55ee13731a5f7e8e03cc3cdb9 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc85xx.h>
 #include <version.h>
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 7e5e6b17c019567826efe133d877b4a42586969f..291557d40d4ac9260c98cdbf6811dd392132aed9 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -28,6 +28,7 @@
  *
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc85xx.h>
 #include <timestamp.h>
diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S
index 3817f19d53521e5c96fa7e5a121a031eab83353e..6127115696a437c91fa5ce31b595444a2dbfa753 100644
--- a/arch/powerpc/cpu/mpc86xx/start.S
+++ b/arch/powerpc/cpu/mpc86xx/start.S
@@ -30,6 +30,7 @@
  *  board_init lies at a quite high address and when the cpu has
  *  jumped there, everything is ok.
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc86xx.h>
 #include <timestamp.h>
@@ -870,7 +871,7 @@ lock_ram_in_cache:
 	 */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:
@@ -905,7 +906,7 @@ unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
 	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
-	li	r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
 		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r4
 1:	icbi	r0, r3
diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index 4a8c5d9e48b00ced9c64bb6459cfc9b2f18e76ae..9d022bf5413f91c4899c8e9efad2012685ae155a 100644
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S
@@ -37,6 +37,7 @@
  *  board_init will change CS0 to be positioned at the correct
  *  address and (s)dram will be positioned at address 0
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc8xx.h>
 #include <timestamp.h>
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 87caea19b040308a7c484c55e6240e5021703d54..363becc8071b05984f9db7035d548153ef3bca9f 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -63,6 +63,7 @@
  *  board_init will change CS0 to be positioned at the correct
  *  address and (s)dram will be positioned at address 0
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/ppc4xx.h>
 #include <timestamp.h>
@@ -182,8 +183,8 @@
 # endif
 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
-#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
+#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
+#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
 #endif
 
 /*
@@ -656,8 +657,8 @@ _start:
 	/* Clear Dcache to use as RAM */
 	addis	r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
 	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
-	addis	r4,r0,CONFIG_SYS_INIT_RAM_END@h
-	ori	r4,r4,CONFIG_SYS_INIT_RAM_END@l
+	addis	r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
+	ori	r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
 	rlwinm. r5,r4,0,27,31
 	rlwinm	r5,r4,27,5,31
 	beq	..d_ran
@@ -1091,8 +1092,8 @@ _start:
 	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
 	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-	lis	r4, CONFIG_SYS_INIT_RAM_END@h
-	ori	r4, r4, CONFIG_SYS_INIT_RAM_END@l
+	lis	r4, CONFIG_SYS_INIT_RAM_SIZE@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
 
 	/*
 	 * Convert the size, in bytes, to the number of cache lines/blocks
@@ -1119,12 +1120,12 @@ _start:
 	lis	r1, CONFIG_SYS_INIT_RAM_ADDR@h
 	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 
-	lis	r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
-	ori	r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
+	lis	r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
+	ori	r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
 	mtctr	r4
 
 	lis	r2, CONFIG_SYS_INIT_RAM_ADDR@h
-	ori	r2, r2, CONFIG_SYS_INIT_RAM_END@l
+	ori	r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
 
 	lis	r4, CONFIG_SYS_INIT_RAM_PATTERN@h
 	ori	r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
@@ -1399,7 +1400,7 @@ relocate_code:
 
 	/* Flush initial global data range */
 	mr	r3, r4
-	addi	r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
+	addi	r4, r4, GENERATED_GBL_DATA_SIZE@l
 	bl	flush_dcache_range
 
 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
@@ -1414,8 +1415,8 @@ relocate_code:
 	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
 	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-	lis	r4, CONFIG_SYS_INIT_RAM_END@h
-	ori	r4, r4, CONFIG_SYS_INIT_RAM_END@l
+	lis	r4, CONFIG_SYS_INIT_RAM_SIZE@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
 	add	r4, r4, r3
 
 	bl	invalidate_dcache_range
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index a1942ca2bd900b757dc9a9757b5b1afb7adf51c4..76dedebe67c17c9a2030704e3d23f6687782f16a 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -89,9 +89,6 @@
 #define CONFIG_SYS_NUM_TLBCAMS	16
 #endif
 
-/* Relocation to SDRAM works on all PPC boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
 /* Since so many PPC SOCs have a semi-common LBC, define this here */
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
 	defined(CONFIG_MPC83xx)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2a323e13d08b798eee6f4dfb52449f4150f4abdc..2e218de0b7ec1570091a88aa253c35b2c4bf2a27 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -34,7 +34,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef	struct	global_data {
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index c0c7fd4f6ee0caf89ae2d859e606ce39edc7e35a..2e0749da0a545a3d15300903c9e5def269a8bdac 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -175,6 +175,16 @@ void __board_add_ram_info(int use_default)
 }
 void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
 
+int __board_flash_wp_on(void)
+{
+	/*
+	 * Most flashes can't be detected when write protection is enabled,
+	 * so provide a way to let U-Boot gracefully ignore write protected
+	 * devices.
+	 */
+	return 0;
+}
+int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on")));
 
 static int init_func_ram (void)
 {
@@ -698,7 +708,11 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #if !defined(CONFIG_SYS_NO_FLASH)
 	puts ("FLASH: ");
 
-	if ((flash_size = flash_init ()) > 0) {
+	if (board_flash_wp_on()) {
+		printf("Uninitialized - Write Protect On\n");
+		/* Since WP is on, we can't find real size.  Set to 0 */
+		flash_size = 0;
+	} else if ((flash_size = flash_init ()) > 0) {
 # ifdef CONFIG_SYS_FLASH_CHECKSUM
 		print_size (flash_size, "");
 		/*
diff --git a/arch/sh/config.mk b/arch/sh/config.mk
index 07ba68f19879b1db2c791f02b16d565a80ef112a..415c94979848f6980e6457200b46f05baf271308 100644
--- a/arch/sh/config.mk
+++ b/arch/sh/config.mk
@@ -29,6 +29,6 @@ STANDALONE_LOAD_ADDR += -EB
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
-PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
+PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
 
 LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S
index 0ab867d54d56578401ef14cde8322debbb3758f0..77043f686a0cc394c4c50f515d104e22ab2f0f25 100644
--- a/arch/sh/cpu/sh2/start.S
+++ b/arch/sh/cpu/sh2/start.S
@@ -18,6 +18,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
@@ -73,6 +74,6 @@ loop:
 ._reloc_dst_end:	.long	reloc_dst_end
 ._bss_start:		.long	bss_start
 ._bss_end:		.long	bss_end
-._gd_init:		.long	(_start - CONFIG_SYS_GBL_DATA_SIZE)
-._stack_init:	.long	(_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._gd_init:		.long	(_start - GENERATED_GBL_DATA_SIZE)
+._stack_init:	.long	(_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
 ._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S
index c0f83261d10fd9c1584c316563948b056f3d1b17..9dd23032657b1850c80b9783dfac7407218c5b04 100644
--- a/arch/sh/cpu/sh3/start.S
+++ b/arch/sh/cpu/sh3/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
@@ -72,6 +73,6 @@ loop:
 ._reloc_dst_end:	.long	reloc_dst_end
 ._bss_start:		.long	bss_start
 ._bss_end:		.long	bss_end
-._gd_init:		.long	(_start - CONFIG_SYS_GBL_DATA_SIZE)
-._stack_init:	.long	(_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._gd_init:		.long	(_start - GENERATED_GBL_DATA_SIZE)
+._stack_init:	.long	(_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
 ._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S
index 711ae668d59bc4403e0a1d098f951d3a7a5cbe72..4b5f606fff7d5f5e98f25daebc2ce3f069739aa8 100644
--- a/arch/sh/cpu/sh4/start.S
+++ b/arch/sh/cpu/sh4/start.S
@@ -18,6 +18,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
 
@@ -69,6 +70,6 @@ loop:
 ._reloc_dst_end:	.long	reloc_dst_end
 ._bss_start:		.long	bss_start
 ._bss_end:		.long	bss_end
-._gd_init:		.long	(_start - CONFIG_SYS_GBL_DATA_SIZE)
-._stack_init:		.long	(_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._gd_init:		.long	(_start - GENERATED_GBL_DATA_SIZE)
+._stack_init:		.long	(_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
 ._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index 978cc92f40a1a48fb8fae9a31e21f8e75aefaff4..049c44eaf84de0ce67d86afcf0cd016d4bd6c407 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h
@@ -21,7 +21,4 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-/* Relocation to SDRAM works on all sh boards */
-#define CONFIG_RELOC_FIXUP_WORKS
-
 #endif
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index a302fc2e65808c858817c288aa0f7c463c682546..fe53ab4de9194351a9906a91cb44780220847914 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -89,7 +89,7 @@ static int sh_pci_init(void)
 
 static int sh_mem_env_init(void)
 {
-	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_GBL_DATA_SIZE -
+	mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE -
 			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
 	env_relocate();
 	jumptable_init();
@@ -144,7 +144,7 @@ void sh_generic_init(void)
 	bd_t *bd;
 	init_fnc_t **init_fnc_ptr;
 
-	memset(gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
+	memset(gd, 0, GENERATED_GBL_DATA_SIZE);
 
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c
index 9c58ed7ec8cb2d507321c7c03f650ea1f478725f..19b3a94023c1236390991bca966e52b6e84d395e 100644
--- a/arch/sh/lib/bootm.c
+++ b/arch/sh/lib/bootm.c
@@ -43,6 +43,41 @@ static void hexdump(unsigned char *buf, int len)
 }
 #endif
 
+#define MOUNT_ROOT_RDONLY	0x000
+#define RAMDISK_FLAGS		0x004
+#define ORIG_ROOT_DEV		0x008
+#define LOADER_TYPE			0x00c
+#define INITRD_START		0x010
+#define INITRD_SIZE			0x014
+#define COMMAND_LINE		0x100
+
+#define RD_PROMPT	(1<<15)
+#define RD_DOLOAD	(1<<14)
+#define CMD_ARG_RD_PROMPT	"prompt_ramdisk="
+#define CMD_ARG_RD_DOLOAD	"load_ramdisk="
+
+#ifdef CONFIG_SH_SDRAM_OFFSET
+#define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
+#else
+#define GET_INITRD_START(initrd, linux) (initrd - linux)
+#endif
+
+static void set_sh_linux_param(unsigned long param_addr, unsigned long data)
+{
+	*(unsigned long *)(param_addr) = data;
+}
+
+static unsigned long sh_check_cmd_arg(char *cmdline, char *key, int base)
+{
+	unsigned long val = 0;
+	char *p = strstr(cmdline, key);
+	if (p) {
+		p += strlen(key);
+		val = simple_strtol(p, NULL, base);
+	}
+	return val;
+}
+
 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
 {
 	/* Linux kernel load address */
@@ -51,7 +86,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	unsigned char *param
 		= (unsigned char *)image_get_load(images->legacy_hdr_os);
 	/* Linux kernel command line */
-	char *cmdline = (char *)param + 0x100;
+	char *cmdline = (char *)param + COMMAND_LINE;
 	/* PAGE_SIZE */
 	unsigned long size = images->ep - (unsigned long)param;
 	char *bootargs = getenv("bootargs");
@@ -61,8 +96,37 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 
 	/* Setup parameters */
 	memset(param, 0, size);	/* Clear zero page */
+
+	/* Set commandline */
 	strcpy(cmdline, bootargs);
 
+	sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
+	/* Initrd */
+	if (images->rd_start || images->rd_end) {
+		unsigned long ramdisk_flags = 0;
+		int val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_PROMPT, 10);
+		if (val == 1)
+				ramdisk_flags |= RD_PROMPT;
+		else
+				ramdisk_flags &= ~RD_PROMPT;
+
+		val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
+		if (val == 1)
+				ramdisk_flags |= RD_DOLOAD;
+		else
+				ramdisk_flags &= ~RD_DOLOAD;
+
+		set_sh_linux_param((unsigned long)param + MOUNT_ROOT_RDONLY, 0x0001);
+		set_sh_linux_param((unsigned long)param + RAMDISK_FLAGS, ramdisk_flags);
+		set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
+		set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
+		set_sh_linux_param((unsigned long)param + INITRD_START,
+			GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
+		set_sh_linux_param((unsigned long)param + INITRD_SIZE,
+			images->rd_end - images->rd_start);
+	}
+
+	/* Boot kernel */
 	kernel();
 	/* does not return */
 
diff --git a/arch/sparc/cpu/leon2/start.S b/arch/sparc/cpu/leon2/start.S
index dd58262c2b41392542729e510c30ec7c93c052af..f22fb7eb1b70e90bdfca2aa303547b59fa629dc7 100644
--- a/arch/sparc/cpu/leon2/start.S
+++ b/arch/sparc/cpu/leon2/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/asmmacro.h>
 #include <asm/winmacro.h>
diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S
index 5c0808a2edb08459287347052bd95e81ce8f2dac..56ae88d6492b8d5623921427063c9f6635c30cfb 100644
--- a/arch/sparc/cpu/leon3/start.S
+++ b/arch/sparc/cpu/leon3/start.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/asmmacro.h>
 #include <asm/winmacro.h>
diff --git a/arch/sparc/include/asm/byteorder.h b/arch/sparc/include/asm/byteorder.h
index b9fc65663f82770f71c27f1a930fa439d4c4b99f..e3b3dec91d48f10138422d7566daa0a254bb14cd 100644
--- a/arch/sparc/include/asm/byteorder.h
+++ b/arch/sparc/include/asm/byteorder.h
@@ -32,6 +32,7 @@
 
 #if defined(__GNUC__) && !defined(__STRICT_ANSI__)
 #define __BYTEORDER_HAS_U64__
+#define __SWAB_64_THRU_32__
 #endif
 #include <linux/byteorder/big_endian.h>
 #endif				/* _SPARC_BYTEORDER_H */
diff --git a/arch/sparc/include/asm/config.h b/arch/sparc/include/asm/config.h
index 6ddc3494c6bee9dbaa6d45e1ddb3802c314b97f7..7b6f30bd4a876194e43f427366a2317f23287791 100644
--- a/arch/sparc/include/asm/config.h
+++ b/arch/sparc/include/asm/config.h
@@ -21,6 +21,8 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_NEEDS_MANUAL_RELOC
+
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h
index 7c1ac0dddd4dcede288656fee2cfa64e95c92e04..9b146748d96aaee8e871fc3d10320a254bbaf963 100644
--- a/arch/sparc/include/asm/global_data.h
+++ b/arch/sparc/include/asm/global_data.h
@@ -36,7 +36,7 @@
  * global variables during system initialization (until we have set
  * up the memory controller so that we can use RAM).
  *
- * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
  */
 
 typedef struct global_data {
diff --git a/arch/sparc/include/asm/unaligned.h b/arch/sparc/include/asm/unaligned.h
new file mode 100644
index 0000000000000000000000000000000000000000..0e646f7fa955a9b1242ce1e723416d9346016125
--- /dev/null
+++ b/arch/sparc/include/asm/unaligned.h
@@ -0,0 +1,10 @@
+#ifndef _ASM_SPARC_UNALIGNED_H
+#define _ASM_SPARC_UNALIGNED_H
+
+/*
+ * The SPARC can not do unaligned accesses, it must be split into multiple
+ * byte accesses. The SPARC is in big endian mode.
+ */
+#include <asm-generic/unaligned.h>
+
+#endif	/* _ASM_SPARC_UNALIGNED_H */
diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c
index 09bcdb04813938a40daa81d3fe194c2f84fad823..ab31cfb50addf543729c05c7c1a19d8e98f7a334 100644
--- a/arch/sparc/lib/board.c
+++ b/arch/sparc/lib/board.c
@@ -244,7 +244,7 @@ void board_init_f(ulong bootflag)
 	printf("CONFIG_SYS_PROM_OFFSET:        0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
 	       CONFIG_SYS_PROM_SIZE);
 	printf("CONFIG_SYS_GBL_DATA_OFFSET:    0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
-	       CONFIG_SYS_GBL_DATA_SIZE);
+	       GENERATED_GBL_DATA_SIZE);
 #endif
 
 #ifdef CONFIG_POST
@@ -252,13 +252,13 @@ void board_init_f(ulong bootflag)
 	post_run(NULL, POST_ROM | post_bootmode_get(0));
 #endif
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	/*
 	 * We have to relocate the command table manually
 	 */
 	fixup_cmdtable(&__u_boot_cmd_start,
 		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
-#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 #if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
 	puts("AMBA:\n");
diff --git a/board/Marvell/guruplug/config.mk b/board/Marvell/guruplug/config.mk
deleted file mode 100644
index 12d7737bec415bf721c44b52ab013f5425ae98be..0000000000000000000000000000000000000000
--- a/board/Marvell/guruplug/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Siddarth Gore <gores@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index 4df4e9b260482f49caab002473a2ea24713c3219..1f0e67a7fe7c2db8ef619e8e387be76210555750 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -30,7 +30,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init(void)
+int board_early_init_f(void)
 {
 	/*
 	 * default gpio configuration
@@ -96,7 +96,11 @@ int board_init(void)
 		0
 	};
 	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
 
+int board_init(void)
+{
 	/*
 	 * arch number of board
 	 */
diff --git a/board/Marvell/mv88f6281gtw_ge/config.mk b/board/Marvell/mv88f6281gtw_ge/config.mk
deleted file mode 100644
index 761c2bb741331b72014123e9da3adc16a4393595..0000000000000000000000000000000000000000
--- a/board/Marvell/mv88f6281gtw_ge/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
index 93d1400be49d469fbdb04248617cf0523fa44ef9..80fd20b7f4b03027faeb519e13d047133fa79130 100644
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -32,7 +32,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init(void)
+int board_early_init_f(void)
 {
 	/*
 	 * default gpio configuration
@@ -98,7 +98,11 @@ int board_init(void)
 		0
 	};
 	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
 
+int board_init(void)
+{
 	/*
 	 * arch number of board
 	 */
diff --git a/board/Marvell/openrd_base/config.mk b/board/Marvell/openrd_base/config.mk
deleted file mode 100644
index 5a49280e774494833972c1c00ad3371fa6a005b1..0000000000000000000000000000000000000000
--- a/board/Marvell/openrd_base/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# Net Insight <www.netinsight.net>
-# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
-#
-# Based on sheevaplug:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c
index d006b2ddf7d3abece1524b7e94b99ed6555fed12..10109c1322a496b241469bb248b68e2337deecff 100644
--- a/board/Marvell/openrd_base/openrd_base.c
+++ b/board/Marvell/openrd_base/openrd_base.c
@@ -35,7 +35,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init(void)
+int board_early_init_f(void)
 {
 	/*
 	 * default gpio configuration
@@ -102,7 +102,11 @@ int board_init(void)
 	};
 
 	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
 
+int board_init(void)
+{
 	/*
 	 * arch number of board
 	 */
diff --git a/board/Marvell/rd6281a/config.mk b/board/Marvell/rd6281a/config.mk
deleted file mode 100644
index 761c2bb741331b72014123e9da3adc16a4393595..0000000000000000000000000000000000000000
--- a/board/Marvell/rd6281a/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
index 0d76146b658069e44e54ec98a64057ac9421bf6c..e69e035308bdbcec164e788f14b58968764e6f51 100644
--- a/board/Marvell/rd6281a/rd6281a.c
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -31,7 +31,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init(void)
+int board_early_init_f(void)
 {
 	/*
 	 * default gpio configuration
@@ -97,7 +97,11 @@ int board_init(void)
 		0
 	};
 	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
 
+int board_init(void)
+{
 	/*
 	 * arch number of board
 	 */
diff --git a/board/Marvell/sheevaplug/config.mk b/board/Marvell/sheevaplug/config.mk
deleted file mode 100644
index 761c2bb741331b72014123e9da3adc16a4393595..0000000000000000000000000000000000000000
--- a/board/Marvell/sheevaplug/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 173a7b809df33f9b2072e5d9e43597f30548db9a..d7dc80c1ba2980792cc1a720ab36c22d7d752422 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -30,7 +30,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init(void)
+int board_early_init_f(void)
 {
 	/*
 	 * default gpio configuration
@@ -96,7 +96,11 @@ int board_init(void)
 		0
 	};
 	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
 
+int board_init(void)
+{
 	/*
 	 * arch number of board
 	 */
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index ae7ccbb4e9dbbaff1daac139a06301b3da663c56..09a5a5183bf9e4e6fa91ab5c79a230f0638be338 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -270,8 +270,6 @@ static u8 display_buf[DISPLAY_BUF_SIZE];
 static u8 display_putc_pos;
 static u8 display_out_pos;
 
-static u8 display_dot_enable;
-
 void display_set(int cmd) {
 
 	if (cmd & DISPLAY_CLEAR) {
@@ -281,12 +279,6 @@ void display_set(int cmd) {
 	if (cmd & DISPLAY_HOME) {
 		display_putc_pos = 0;
 	}
-
-	if (cmd & DISPLAY_MARK) {
-		display_dot_enable = 1;
-	} else {
-		display_dot_enable = 0;
-	}
 }
 
 #define SEG_A    (1<<0)
@@ -314,10 +306,12 @@ void display_set(int cmd) {
  * A..Z		index 10..35
  * -		index 36
  * _		index 37
+ * .		index 38
  */
 
 #define SYMBOL_DASH		(36)
 #define SYMBOL_UNDERLINE	(37)
+#define SYMBOL_DOT		(38)
 
 static u8 display_char2seg7_tbl[]=
 {
@@ -337,28 +331,29 @@ static u8 display_char2seg7_tbl[]=
 	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
 	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
 	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* g */
+	0,					/* g - not displayed */
 	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
-	SEG_E | SEG_F,						/* I */
-	SEG_B | SEG_C | SEG_D | SEG_E,				/* J */
-	SEG_A,						/* K - special 1 */
+	SEG_B | SEG_C,						/* I */
+	0,					/* J - not displayed */
+	0,					/* K - not displayed */
 	SEG_D | SEG_E | SEG_F,					/* L */
-	SEG_B,						/* m - special 2 */
-	SEG_C | SEG_E | SEG_G,					/* n */
-	SEG_C | SEG_D | SEG_E | SEG_G,				/* o */
+	0,					/* m - not displayed */
+	0,					/* n - not displayed */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
 	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
-	SEG_A | SEG_B | SEG_C | SEG_F | SEG_G,			/* q */
-	SEG_E | SEG_G,						/* r */
+	0,					/* q - not displayed */
+	0,					/* r - not displayed */
 	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
 	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
 	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
-	SEG_C | SEG_D | SEG_E | SEG_F,				/* V */
-	SEG_C,						/* w - special 3 */
-	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* X */
+	0,					/* V - not displayed */
+	0,					/* w - not displayed */
+	0,					/* X - not displayed */
 	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
-	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* Z */
+	0,					/* Z - not displayed */
 	SEG_G,							/* - */
-	SEG_D							/* _ */
+	SEG_D,							/* _ */
+	SEG_P							/* . */
 };
 
 /* Convert char to the LED segments representation */
@@ -374,23 +369,20 @@ static u8 display_char2seg7(char c)
 		c -= 'A' - 10;
 	else if (c == '-')
 		c = SYMBOL_DASH;
-	else if ((c == '_') || (c == '.'))
+	else if (c == '_')
 		c = SYMBOL_UNDERLINE;
+	else if (c == '.')
+		c = SYMBOL_DOT;
 	else
 		c = ' ';	/* display unsupported symbols as space */
 
 	if (c != ' ')
 		val = display_char2seg7_tbl[(int)c];
 
-	/* Handle DP LED here */
-	if (display_dot_enable) {
-		val |= SEG_P;
-	}
-
 	return val;
 }
 
-static inline int display_putc_nomark(char c)
+int display_putc(char c)
 {
 	if (display_putc_pos >= DISPLAY_BUF_SIZE)
 		return -1;
@@ -403,13 +395,6 @@ static inline int display_putc_nomark(char c)
 	return c;
 }
 
-int display_putc(char c)
-{
-	/* Mark the codes from the "display" command with the DP LED */
-	display_set(DISPLAY_MARK);
-	return display_putc_nomark(c);
-}
-
 /*
  * Flush current symbol to the LED display hardware
  */
@@ -493,9 +478,8 @@ void show_boot_progress(int status)
 	if (a4m072_status2code(status, buf) < 0)
 		return;
 
-	display_set(0);	/* Clear DP Led */
-	display_putc_nomark(buf[0]);
-	display_putc_nomark(buf[1]);
+	display_putc(buf[0]);
+	display_putc(buf[1]);
 	display_set(DISPLAY_HOME);
 	display_out_pos = 0;	/* reset output position */
 
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 6925921785ecbbeaecffc661ad4c9ca56b852f73..3d9989d7f1a9a5d85c7c7cfe496a3431348a7236 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -23,6 +23,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 #include <asm/mmu.h>
diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S
index e969fcfd9058560ccca5a610fc2227dd88783c56..4b90c8d0804e5bce05355aa0e32a1e4e5f30edf6 100644
--- a/board/amcc/bluestone/init.S
+++ b/board/amcc/bluestone/init.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 #include <asm/mmu.h>
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 64d5d422935cc8ea3b15a7041c9abc42d7d37d8d..680feaa6a9671707422be623ea0654b79d4a77ff 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 #include <asm/mmu.h>
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 7139aaee4d0e710cba00e231e642ea171c6e9659..419ef4f9942a14df7dca2b2a6e873a4eb5653398 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <asm/mmu.h>
 #include <config.h>
diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S
index ed3741c54a98d54dacb22bbd2bbe32c4e63098ce..d23cdc79d0decd5f1f7a66a465a585c881b8b361 100644
--- a/board/amcc/yosemite/init.S
+++ b/board/amcc/yosemite/init.S
@@ -19,6 +19,7 @@
 * MA 02111-1307 USA
 */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <asm/mmu.h>
 #include <config.h>
diff --git a/board/barco/early_init.S b/board/barco/early_init.S
index 531dcdf4ae22e5dd00c2c6f7718df775394927ea..61b4b55534226357e1f74120baf3f484c2feeec0 100644
--- a/board/barco/early_init.S
+++ b/board/barco/early_init.S
@@ -25,6 +25,7 @@
 #define __ASSEMBLY__	1
 #endif
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/processor.h>
 #include <mpc824x.h>
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
index 9e73c57b8789466ec1802b2444ea3f35d36ede94..dcb91bdffad707e4d0f0e9f3320cbb516e669488 100644
--- a/board/bct-brettl2/cled.c
+++ b/board/bct-brettl2/cled.c
@@ -13,7 +13,7 @@
 
 int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong addr = 0x20000000 + 0x200000; // AMS2
+	ulong addr = 0x20000000 + 0x200000; /* AMS2 */
 	uchar data;
 
 	if (argc < 2)
diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile
index a806b184920d2abff6c5be38bffec1124943029b..b111b519f080d430db49c7ea3e135614f61ab3f6 100644
--- a/board/cerf250/Makefile
+++ b/board/cerf250/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= cerf250.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c
index 59346bc6d45d65ffb742456f5ed59d931900ba44..043afea265f91034002f4fba88a9534e2158304f 100644
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of cerf PXA Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
@@ -58,19 +59,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/cerf250/config.mk b/board/cerf250/config.mk
deleted file mode 100644
index c2d46b2be05ce1645d636e56e1ec11f6e9258c0f..0000000000000000000000000000000000000000
--- a/board/cerf250/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Cerf board with PXA250 cpu
-#
-#
-CONFIG_SYS_TEXT_BASE = 0xa3080000
diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S
deleted file mode 100644
index 5bfe53c728e7472a6484a4a79fd180996a91b2bc..0000000000000000000000000000000000000000
--- a/board/cerf250/lowlevel_init.S
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr	r0, =GPSR0
-	ldr	r1, =CONFIG_SYS_GPSR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPSR1
-	ldr	r1, =CONFIG_SYS_GPSR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPSR2
-	ldr	r1, =CONFIG_SYS_GPSR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR0
-	ldr	r1, =CONFIG_SYS_GPCR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR1
-	ldr	r1, =CONFIG_SYS_GPCR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR2
-	ldr	r1, =CONFIG_SYS_GPCR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR0
-	ldr	r1, =CONFIG_SYS_GPDR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR1
-	ldr	r1, =CONFIG_SYS_GPDR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR2
-	ldr	r1, =CONFIG_SYS_GPDR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR0_L
-	ldr	r1, =CONFIG_SYS_GAFR0_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR0_U
-	ldr	r1, =CONFIG_SYS_GAFR0_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR1_L
-	ldr	r1, =CONFIG_SYS_GAFR1_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR1_U
-	ldr	r1, =CONFIG_SYS_GAFR1_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR2_L
-	ldr	r1, =CONFIG_SYS_GAFR2_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR2_U
-	ldr	r1, =CONFIG_SYS_GAFR2_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =PSSR			/* enable GPIO pins */
-	ldr	r1, =CONFIG_SYS_PSSR_VAL
-	str	r1, [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
-						/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-
-	ldr	r1, =MEMC_BASE			/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC0_VAL
-	str	r2, [r1, #MSC0_OFFSET]
-	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC1_VAL
-	str	r2, [r1, #MSC1_OFFSET]
-	ldr	r2, [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC2_VAL
-	str	r2, [r1, #MSC2_OFFSET]
-	ldr	r2, [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr	r2, =CONFIG_SYS_MECR_VAL
-	str	r2, [r1, #MECR_OFFSET]
-	ldr	r2, [r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr	r2, =CONFIG_SYS_MCMEM0_VAL
-	str	r2, [r1, #MCMEM0_OFFSET]
-	ldr	r2, [r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr	r2, =CONFIG_SYS_MCMEM1_VAL
-	str	r2, [r1, #MCMEM1_OFFSET]
-	ldr	r2, [r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr	r2, =CONFIG_SYS_MCATT0_VAL
-	str	r2, [r1, #MCATT0_OFFSET]
-	ldr	r2, [r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr	r2, =CONFIG_SYS_MCATT1_VAL
-	str	r2, [r1, #MCATT1_OFFSET]
-	ldr	r2, [r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr	r2, =CONFIG_SYS_MCIO0_VAL
-	str	r2, [r1, #MCIO0_OFFSET]
-	ldr	r2, [r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr	r2, =CONFIG_SYS_MCIO1_VAL
-	str	r2, [r1, #MCIO1_OFFSET]
-	ldr	r2, [r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field, set SDRAM clocks free running */
-
-	ldr	r3, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =0xFFF
-	and	r3, r3,  r2
-
-	ldr	r0, [r1, #MDREFR_OFFSET]
-	bic	r0, r0, r2
-	bic	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
-	orr	r0, r0, r3
-
-	str	r0, [r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
-					MDREFR_K2RUN |MDREFR_K2DB2)
-	and	r4, r4, r2
-	bic	r0, r0, r2
-	orr	r0, r0, r4
-
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r0, r0, #(MDREFR_SLFRSH)
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
-
-	ldr     r4, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
-			MDREFR_K1FREE | MDREFR_K2FREE)
-	and	r4, r4, r2
-	orr	r0, r0, r4
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4, =CONFIG_SYS_MDCNFG_VAL
-	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4, [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 �sec.                                          */
-
-	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
-						/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3, =CONFIG_SYS_DRAM_BASE
-.rept 8
-	str	r2, [r3]
-.endr
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3, [r1, #MDCNFG_OFFSET]
-	orr	r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2, =CONFIG_SYS_MDMRS_VAL
-	str     r2, [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2, =ICLR
-	str     r1, [r2]
-
-	ldr     r2, =ICMR	/* mask all interrupts at the controller    */
-	str     r1, [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1, =CKEN
-	mov     r2, #0
-	str     r2, [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1, =CCCR
-	str     r2, [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1, =OSCC
-	mov     r2, #OSCC_OON
-	str     r2, [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-	ldr     r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR /* enable no sources */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov     pc, lr
diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile
index ae570e153c49ef8862df18475cb3e3a3577a2cde..f8b44abee008f064a9a61a377f97813c3e91fe78 100644
--- a/board/colibri_pxa270/Makefile
+++ b/board/colibri_pxa270/Makefile
@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= colibri_pxa270.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
index 8aa7067c732b02cbc2ccefa0e022e5c3d4e52fa2..191fb333e40ff53f9aba9c7c414b16fe2898df4d 100644
--- a/board/colibri_pxa270/colibri_pxa270.c
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -42,8 +42,9 @@ struct serial_device *default_serial_console (void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of vpac270 */
 	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
@@ -54,13 +55,18 @@ int board_init (void)
 	return 0;
 }
 
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
 #ifdef	CONFIG_CMD_USB
diff --git a/board/colibri_pxa270/config.mk b/board/colibri_pxa270/config.mk
deleted file mode 100644
index 0f10662ce3800e83428c6e782a180d91c7492ca2..0000000000000000000000000000000000000000
--- a/board/colibri_pxa270/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000
diff --git a/board/colibri_pxa270/lowlevel_init.S b/board/colibri_pxa270/lowlevel_init.S
deleted file mode 100644
index a43dac2baeeaac9e9c7e24511c88d9503f5b0163..0000000000000000000000000000000000000000
--- a/board/colibri_pxa270/lowlevel_init.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Toradex Colibri PXA270 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr
diff --git a/board/cradle/Makefile b/board/cradle/Makefile
index 1ae785db5fc749aea01fe2c38b850eaaa422d8d4..720593c4825e86a159328f30caac39749ec0535e 100644
--- a/board/cradle/Makefile
+++ b/board/cradle/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= cradle.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/cradle/config.mk b/board/cradle/config.mk
deleted file mode 100644
index 6656bddee12f6a472205f3889f976fbbaef92daa..0000000000000000000000000000000000000000
--- a/board/cradle/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa0f80000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index c4a93f91b76bc2df4c84e0894d49e97f230e7c45..2bbf2d532d43adf05cd1e3195e83ac6da3507f8a 100644
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -185,6 +185,10 @@ int
 board_init (void)
 /**********************************************************/
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	led_code (0xf, YELLOW);
 
 	/* arch number of HHP Cradle */
@@ -206,24 +210,18 @@ board_init (void)
 	return 1;
 }
 
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
-
-	return (PHYS_SDRAM_1_SIZE +
-		PHYS_SDRAM_2_SIZE +
-		PHYS_SDRAM_3_SIZE +
-		PHYS_SDRAM_4_SIZE );
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
deleted file mode 100644
index 39964b6475734b145d008d906f5c34b0844252a4..0000000000000000000000000000000000000000
--- a/board/cradle/lowlevel_init.S
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-   .macro SET_LED val
-   ldr   r6, =GPCR2
-   ldr   r7, =0
-   str   r7, [r6]
-   ldr   r6, =GPSR2
-   ldr   r7, =\val
-   str   r7, [r6]
-   .endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-    /* Set up GPIO pins first */
-
-   ldr      r0,   =GPSR0
-   ldr      r1,   =CONFIG_SYS_GPSR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPSR1
-   ldr      r1,   =CONFIG_SYS_GPSR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPSR2
-   ldr      r1,   =CONFIG_SYS_GPSR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR0
-   ldr      r1,   =CONFIG_SYS_GPCR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR1
-   ldr      r1,   =CONFIG_SYS_GPCR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR2
-   ldr      r1,   =CONFIG_SYS_GPCR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER0
-   ldr      r1,   =CONFIG_SYS_GRER0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER1
-   ldr      r1,   =CONFIG_SYS_GRER1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER2
-   ldr      r1,   =CONFIG_SYS_GRER2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER0
-   ldr      r1,   =CONFIG_SYS_GFER0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER1
-   ldr      r1,   =CONFIG_SYS_GFER1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER2
-   ldr      r1,   =CONFIG_SYS_GFER2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR0
-   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR1
-   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR2
-   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR0_L
-   ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR0_U
-   ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR1_L
-   ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR1_U
-   ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR2_L
-   ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR2_U
-   ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
-   str      r1,   [r0]
-
-   /* enable GPIO pins */
-   ldr      r0,   =PSSR
-   ldr      r1,   =CONFIG_SYS_PSSR_VAL
-   str      r1,   [r0]
-
-   SET_LED 1
-
-   ldr    r3, =MSC1             /* low - bank 2 Lubbock Registers / SRAM */
-   ldr    r2, =CONFIG_SYS_MSC1_VAL     /* high - bank 3 Ethernet Controller */
-   str    r2, [r3]              /* need to set MSC1 before trying to write to the HEX LEDs */
-   ldr    r2, [r3]              /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
-    Initlialize Memory Controller
-
-    See PXA250 Operating System Developer's Guide
-
-    pause for 200 uSecs- allow internal clocks to settle
-    *Note: only need this if hard reset... doing it anyway for now
-*/
-
-    @ Step 1
-   @ ---- Wait 200 usec
-   ldr r3, =OSCR       @ reset the OS Timer Count to zero
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300         @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-   SET_LED 2
-
-mem_init:
-	@ get memory controller base address
-	ldr     r1,  =MEMC_BASE
-
-
-@****************************************************************************
-@  Step 2
-@
-
-   @ Step 2a
-   @ write msc0, read back to ensure data latches
-   @
-   ldr     r2,   =CONFIG_SYS_MSC0_VAL
-   str     r2,   [r1, #MSC0_OFFSET]
-   ldr     r2,   [r1, #MSC0_OFFSET]
-
-   @ write msc1
-   ldr     r2,  =CONFIG_SYS_MSC1_VAL
-   str     r2,  [r1, #MSC1_OFFSET]
-   ldr     r2,  [r1, #MSC1_OFFSET]
-
-   @ write msc2
-   ldr     r2,  =CONFIG_SYS_MSC2_VAL
-   str     r2,  [r1, #MSC2_OFFSET]
-   ldr     r2,  [r1, #MSC2_OFFSET]
-
-   @ Step 2b
-   @ write mecr
-   ldr     r2,  =CONFIG_SYS_MECR_VAL
-   str     r2,  [r1, #MECR_OFFSET]
-
-   @ write mcmem0
-   ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-   str     r2,  [r1, #MCMEM0_OFFSET]
-
-   @ write mcmem1
-   ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-   str     r2,  [r1, #MCMEM1_OFFSET]
-
-   @ write mcatt0
-   ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-   str     r2,  [r1, #MCATT0_OFFSET]
-
-   @ write mcatt1
-   ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-   str     r2,  [r1, #MCATT1_OFFSET]
-
-   @ write mcio0
-   ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-   str     r2,  [r1, #MCIO0_OFFSET]
-
-   @ write mcio1
-   ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-   str     r2,  [r1, #MCIO1_OFFSET]
-
-   /*SET_LED 3 */
-
-   @ Step 2c
-   @ fly-by-dma is defeatured on this part
-   @ write flycnfg
-   @ldr     r2,  =CONFIG_SYS_FLYCNFG_VAL
-   @str     r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-   @ Step 2d
-   @ get the mdrefr settings
-   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
-
-   @ extract DRI field (we need a valid DRI field)
-   @
-   ldr     r2,  =0xFFF
-
-   @ valid DRI field in r3
-   @
-   and     r3,  r3,  r2
-
-   @ get the reset state of MDREFR
-   @
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ clear the DRI field
-   @
-   bic     r4,  r4,  r2
-
-   @ insert the valid DRI field loaded above
-   @
-   orr     r4,  r4,  r3
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ *Note: preserve the mdrefr value in r4 *
-
-   /*SET_LED 4 */
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-   mov   pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-   @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-   @ clear the free-running clock bits
-   @ (clear K0Free, K1Free, K2Free
-   @
-   bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-   @ set K0RUN for CPLD clock
-   @
-   orr   r4,  r4,  #0x00002000
-
-   @ set K1RUN if bank 0 installed
-   @
-   orr   r4,  r4,  #0x00010000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ deassert SLFRSH
-   @
-   bic     r4,  r4,  #0x00400000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ assert E1PIN
-   @
-   orr     r4,  r4,  #0x00008000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-   nop
-   nop
-#else
-   @ Step 2d
-   @ get the mdrefr settings
-   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @  Step 4
-
-   @ set K0RUN for CPLD clock
-   @
-   orr   r4,  r4,  #0x00002000
-
-   @ set K1RUN for bank 0
-   @
-   orr   r4,  r4,  #0x00010000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ deassert SLFRSH
-   @
-   bic     r4,  r4,  #0x00400000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ assert E1PIN
-   @
-   orr     r4,  r4,  #0x00008000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-   nop
-   nop
-#endif
-
-   @ Step 4d
-   @ fetch platform value of mdcnfg
-   @
-   ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-   @ disable all sdram banks
-   @
-   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-   @ program banks 0/1 for bus width
-   @
-   bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
-
-   @ write initial value of mdcnfg, w/o enabling sdram banks
-   @
-   str     r2,  [r1, #MDCNFG_OFFSET]
-
-   @ Step 4e
-   @ pause for 200 uSecs
-   @
-   ldr r3, =OSCR       @ reset the OS Timer Count to zero
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-   /*SET_LED 5 */
-
-   /* Why is this here??? */
-   mov    r0, #0x78                @turn everything off
-   mcr    p15, 0, r0, c1, c0, 0      @(caches off, MMU off, etc.)
-
-   @ Step 4f
-   @ Access memory *not yet enabled* for CBR refresh cycles (8)
-   @ - CBR is generated for all banks
-
-   ldr     r2, =CONFIG_SYS_DRAM_BASE
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-
-   @ Step 4g
-   @get memory controller base address
-   @
-   ldr     r1,  =MEMC_BASE
-
-   @fetch current mdcnfg value
-   @
-   ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-   @enable sdram bank 0 if installed (must do for any populated bank)
-   @
-   orr     r3,  r3,  #MDCNFG_DE0
-
-   @write back mdcnfg, enabling the sdram bank(s)
-   @
-   str     r3,  [r1, #MDCNFG_OFFSET]
-
-   @ Step 4h
-   @ write mdmrs
-   @
-   ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-   str     r2,  [r1, #MDMRS_OFFSET]
-
-   @ Done Memory Init
-
-   /*SET_LED 6 */
-
-   @********************************************************************
-   @ Disable (mask) all interrupts at the interrupt controller
-   @
-
-   @ clear the interrupt level register (use IRQ, not FIQ)
-   @
-   mov     r1, #0
-   ldr     r2,  =ICLR
-   str     r1,  [r2]
-
-   @ Set interrupt mask register
-   @
-   ldr     r1,  =CONFIG_SYS_ICMR_VAL
-   ldr     r2,  =ICMR
-   str     r1,  [r2]
-
-   @ ********************************************************************
-   @ Disable the peripheral clocks, and set the core clock
-   @
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-   ldr     r1,  =CKEN
-   mov     r2,  #0
-   str     r2,  [r1]
-
-   @ set core clocks
-   @
-   ldr     r2,  =CONFIG_SYS_CCCR_VAL
-   ldr     r1,  =CCCR
-   str     r2,  [r1]
-
-#ifdef ENABLE32KHZ
-   @ enable the 32Khz oscillator for RTC and PowerManager
-   @
-   ldr     r1,  =OSCC
-   mov     r2,  #OSCC_OON
-   str     r2,  [r1]
-
-   @ NOTE:  spin here until OSCC.OOK get set,
-   @        meaning the PLL has settled.
-   @
-60:
-   ldr     r2, [r1]
-   ands    r2, r2, #1
-   beq     60b
-#endif
-
-	@ Turn on needed clocks
-	@
-   ldr     r1,  =CKEN
-   ldr     r2,  =CONFIG_SYS_CKEN_VAL
-   str     r2,  [r1]
-
-   /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-   /*Disable software and data breakpoints */
-   mov   r0,#0
-   mcr   p15,0,r0,c14,c8,0  /* ibcr0 */
-   mcr   p15,0,r0,c14,c9,0  /* ibcr1 */
-   mcr   p15,0,r0,c14,c4,0  /* dbcon */
-
-   /*Enable all debug functionality */
-   mov   r0,#0x80000000
-   mcr   p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-   /*SET_LED 8 */
-
-   mov   pc, r10
-
-@ End lowlevel_init
diff --git a/board/csb226/Makefile b/board/csb226/Makefile
index c12dbea9cdd7db3802087cacb8f036da048a6c82..5e1332bae41332b19d2f27bc1c54012efb1dd31d 100644
--- a/board/csb226/Makefile
+++ b/board/csb226/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= csb226.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/csb226/config.mk b/board/csb226/config.mk
deleted file mode 100644
index 9e4655585d7fe4fa0782246ef64017d5cb99f4ff..0000000000000000000000000000000000000000
--- a/board/csb226/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index 6eed9ad676f6593da1aa9f747ae74ab395a48d5a..dd29e626591a83e5ccc6ddd4ad23ea5e41215864 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -69,8 +69,9 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of CSB226 board */
 	gd->bd->bi_arch_number = MACH_TYPE_CSB226;
@@ -82,21 +83,20 @@ int board_init (void)
 }
 
 
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
-
 /**
  * csb226_set_led: - switch LEDs on or off
  *
diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S
deleted file mode 100644
index 55169be45eaf2bb9d085ac8a96186a33e0029731..0000000000000000000000000000000000000000
--- a/board/csb226/lowlevel_init.S
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
-/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
-/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/*	ldr	r1,	=LED_BLANK */
-/*	mov	r0,	#0xFF */
-/*	str	r0,	[r1]		/  turn on hex leds */
-/* */
-/*loop: */
-/* */
-/*   ldr	r0, =0xB0070001 */
-/*   ldr	r1, =_LED */
-/*   str	r0, [r1]		/  hex display */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
-	adr	r3, mem_init		/* r0 <- current position of code   */
-	ldr	r2, =mem_init
-	cmp	r3, r2			/* skip init if in place            */
-	beq	initirqs
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	ldr	r2,	=0xFFF
-	and	r3,	r3, r2
-	ldr	r4,	=0x03ca4000
-	orr	r4,	r4,  r3
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,	[r1, #MDREFR_OFFSET]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* Step 4a: assert MDREFR:K?RUN and configure                       */
-	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
-
-	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4, #(MDREFR_SLFRSH)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
-
-	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 �sec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	/*          There should 9 writes, since the first write doesn't    */
-	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
-	/*          PXA210 Processors Specification Update,                 */
-	/*          Jan 2003, Errata #116, page 30.                         */
-
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr	r3, [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str	r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-/*
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-*/
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size                                                  */
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR			/* enable no sources        */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#ifndef DEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr
diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c
index f865eb422563142a71a692bf83e301d0a69789ee..656d5cde95a4933b81bbbbcd1eee962a92118abf 100644
--- a/board/davedenx/qong/fpga.c
+++ b/board/davedenx/qong/fpga.c
@@ -92,4 +92,3 @@ int qong_fpga_init(void)
 }
 
 #endif
-
diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c
index b60a46e96d2d60b5612f0ef6426420ca8ba84196..fa9dd9fe4d0b830aaf14127ec61cbab1002c9f03 100644
--- a/board/davinci/common/misc.c
+++ b/board/davinci/common/misc.c
@@ -33,15 +33,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return(0);
-}
-#else
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -56,7 +47,6 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
 }
-#endif
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
diff --git a/board/davinci/da8xxevm/config.mk b/board/davinci/da8xxevm/config.mk
deleted file mode 100644
index e176f7d51a57913e86d444a13cd461173e74b464..0000000000000000000000000000000000000000
--- a/board/davinci/da8xxevm/config.mk
+++ /dev/null
@@ -1,43 +0,0 @@
-#
-# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Texas Instruments DA8xx EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips).
-# Physical Address:
-# C000'0000 to C400'0000
-#
-# Linux-Kernel is expected to be at C000'8000, entry C000'8000
-# (mem base + reserved)
-#
-# we load ourself to C108 '0000
-
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0xC1080000
diff --git a/board/delta/config.mk b/board/delta/config.mk
deleted file mode 100644
index 8b2404456997c608cc244bc401246576c441f8c5..0000000000000000000000000000000000000000
--- a/board/delta/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x83008000
diff --git a/board/delta/delta.c b/board/delta/delta.c
deleted file mode 100644
index df23076a64637ade872b392a39e68981195a1b48..0000000000000000000000000000000000000000
--- a/board/delta/delta.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <da9030.h>
-#include <malloc.h>
-#include <command.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static void init_DA9030(void);
-static void keys_init(void);
-static void get_pressed_keys(uchar *s);
-static uchar *key_match(uchar *kbd_data);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
-
-	/* arch number of Lubbock-Board mk@tbd: fix this! */
-	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef DELTA_CHECK_KEYBD
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	char *str;
-	int i;
-#endif /* DELTA_CHECK_KEYBD */
-
-	setenv("stdout", "serial");
-	setenv("stderr", "serial");
-
-#ifdef DELTA_CHECK_KEYBD
-	keys_init();
-
-	memset(kbd_data, '\0', KEYBD_DATALEN);
-
-	/* check for pressed keys and setup keybd_env */
-	get_pressed_keys(kbd_data);
-
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-	}
-	setenv ("keybd", keybd_env);
-
-	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
-
-# ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
-	setenv ("preboot", str);	/* set or delete definition */
-# endif /* CONFIG_PREBOOT */
-	if (str != NULL) {
-		free (str);
-	}
-#endif /* DELTA_CHECK_KEYBD */
-
-	init_DA9030();
-	return 0;
-}
-
-/*
- * Magic Key Handling, mainly copied from board/lwmon/lwmon.c
- */
-#ifdef DELTA_CHECK_KEYBD
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-/*
- * Get pressed keys
- * s is a buffer of size KEYBD_DATALEN-1
- */
-static void get_pressed_keys(uchar *s)
-{
-	unsigned long val;
-	val = readl(GPLR3);
-
-	if(val & (1<<31))
-		*s++ = KEYBD_KP_DKIN0;
-	if(val & (1<<18))
-		*s++ = KEYBD_KP_DKIN1;
-	if(val & (1<<29))
-		*s++ = KEYBD_KP_DKIN2;
-	if(val & (1<<22))
-		*s++ = KEYBD_KP_DKIN5;
-}
-
-static void keys_init()
-{
-	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
-	udelay(100);
-
-	/* Configure GPIOs */
-	writel(0xa840, GPIO127);	/* KP_DKIN0 */
-	writel(0xa840, GPIO114);	/* KP_DKIN1 */
-	writel(0xa840, GPIO125);	/* KP_DKIN2 */
-	writel(0xa840, GPIO118);	/* KP_DKIN5 */
-
-	/* Configure GPIOs as inputs */
-	writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
-	writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
-
-	udelay(100);
-}
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
-	/* uchar compare[KEYBD_DATALEN-1]; */
-	uchar compare[KEYBD_DATALEN];
-	char *nxt;
-	int i;
-
-	/* Don't include modifier byte */
-	/* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */
-	memcpy (compare, kbd_data, KEYBD_DATALEN);
-
-	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
-		uchar c;
-		int k;
-
-		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
-		if (str == (uchar *)nxt) {	/* invalid character */
-			break;
-		}
-
-		/*
-		 * Check if this key matches the input.
-		 * Set matches to zero, so they match only once
-		 * and we can find duplicates or extra keys
-		 */
-		for (k = 0; k < sizeof(compare); ++k) {
-			if (compare[k] == '\0')	/* only non-zero entries */
-				continue;
-			if (c == compare[k]) {	/* found matching key */
-				compare[k] = '\0';
-				break;
-			}
-		}
-		if (k == sizeof(compare)) {
-			return -1;		/* unmatched key */
-		}
-	}
-
-	/*
-	 * A full match leaves no keys in the `compare' array,
-	 */
-	for (i = 0; i < sizeof(compare); ++i) {
-		if (compare[i])
-		{
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-
-static uchar *key_match (uchar *kbd_data)
-{
-	char magic[sizeof (kbd_magic_prefix) + 1];
-	uchar *suffix;
-	char *kbd_magic_keys;
-
-	/*
-	 * The following string defines the characters that can pe appended
-	 * to "key_magic" to form the names of environment variables that
-	 * hold "magic" key codes, i. e. such key codes that can cause
-	 * pre-boot actions. If the string is empty (""), then only
-	 * "key_magic" is checked (old behaviour); the string "125" causes
-	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
-	 */
-	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
-		kbd_magic_keys = "";
-
-	/* loop over all magic keys;
-	 * use '\0' suffix in case of empty string
-	 */
-	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
-		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-#if 0
-		printf ("### Check magic \"%s\"\n", magic);
-#endif
-		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
-			char cmd_name[sizeof (kbd_command_prefix) + 1];
-			char *cmd;
-
-			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
-			cmd = getenv (cmd_name);
-#if 0
-			printf ("### Set PREBOOT to $(%s): \"%s\"\n",
-				cmd_name, cmd ? cmd : "<<NULL>>");
-#endif
-			*kbd_data = *suffix;
-			return ((uchar *)cmd);
-		}
-	}
-#if 0
-	printf ("### Delete PREBOOT\n");
-#endif
-	*kbd_data = '\0';
-	return (NULL);
-}
-
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	int i;
-
-	/* Read keys */
-	get_pressed_keys(kbd_data);
-	puts ("Keys:");
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-		printf (" %02x", kbd_data[i]);
-	}
-	putc ('\n');
-	setenv ("keybd", keybd_env);
-	return 0;
-}
-
-U_BOOT_CMD(
-	   kbd,	1,	1,	do_kbd,
-	   "read keyboard status",
-	   ""
-);
-
-#endif /* DELTA_CHECK_KEYBD */
-
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
-}
-
-void i2c_init_board()
-{
-	writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-
-	/* setup I2C GPIO's */
-	writel(0x801, GPIO32);		/* SCL = Alt. Fkt. 1 */
-	writel(0x801, GPIO33);		/* SDA = Alt. Fkt. 1 */
-}
-
-/* initialize the DA9030 Power Controller */
-static void init_DA9030()
-{
-	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-
-	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
-	udelay(100);
-
-	/* Rising Edge on EXTON to reset DA9030 */
-	writel(0x8800, GPIO17);	/* configure GPIO17, no pullup, -down */
-	writel(readl(GPDR0) | (1<<17), GPDR0);	/* GPIO17 is output */
-	writel((1<<17), GSDR0);
-	writel((1<<17), GPCR0);	/* drive GPIO17 low */
-	writel((1<<17), GPSR0);	/* drive GPIO17 high */
-
-#if CONFIG_SYS_DA9030_EXTON_DELAY
-	udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY);	/* wait for DA9030 */
-#endif
-	writel((1<<17), GPCR0);	/* drive GPIO17 low */
-
-	/* reset the watchdog and go active (0xec) */
-	val = (SYS_CONTROL_A_HWRES_ENABLE |
-	       (0x6<<4) |
-	       SYS_CONTROL_A_WDOG_ACTION |
-	       SYS_CONTROL_A_WATCHDOG);
-	if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
-		printf("Error accessing DA9030 via i2c.\n");
-		return;
-	}
-
-	val = 0x80;
-	if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
-		printf("Error accessing DA9030 via i2c.\n");
-		return;
-	}
-
-	i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
-	i2c_reg_write(addr, LDO2_3, 0xd1);	/* LDO2 =1,9V, LDO3=3,1V */
-	i2c_reg_write(addr, LDO4_5, 0xcc);	/* LDO2 =1,9V, LDO3=3,1V */
-	i2c_reg_write(addr, LDO6_SIMCP, 0x3e);	/* LDO6=3,2V, SIMCP = 5V support */
-	i2c_reg_write(addr, LDO7_8, 0xc9);	/* LDO7=2,7V, LDO8=3,0V */
-	i2c_reg_write(addr, LDO9_12, 0xec);	/* LDO9=3,0V, LDO12=3,2V */
-	i2c_reg_write(addr, BUCK, 0x0c);	/* Buck=1.2V */
-	i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
-	i2c_reg_write(addr, LDO_10_11, 0xcc);	/* LDO10=3.0V  LDO11=3.0V */
-	i2c_reg_write(addr, LDO_15, 0xae);	/* LDO15=1.8V, dislock first 3bit */
-	i2c_reg_write(addr, LDO_14_16, 0x05);	/* LDO14=2.8V, LDO16=NB */
-	i2c_reg_write(addr, LDO_18_19, 0x9c);	/* LDO18=3.0V, LDO19=2.7V */
-	i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
-	i2c_reg_write(addr, BUCK2_DVC1, 0x9a);	/* Buck2=1.5V plus Update support of 520 MHz */
-	i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
-	i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
-	i2c_reg_write(addr, USBPUMP, 0xc1);	/* start pump, ignore HW signals */
-
-	val = i2c_reg_read(addr, STATUS);
-	if(val & STATUS_CHDET)
-		printf("Charger detected, turning on LED.\n");
-	else {
-		printf("No charger detetected.\n");
-		/* undervoltage? print error and power down */
-	}
-}
-
-
-#if 0
-/* reset the DA9030 watchdog */
-void hw_watchdog_reset(void)
-{
-	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-	val = i2c_reg_read(addr, SYS_CONTROL_A);
-	val |= SYS_CONTROL_A_WATCHDOG;
-	i2c_reg_write(addr, SYS_CONTROL_A, val);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
deleted file mode 100644
index 1664f3ba17c3a81baace11be846930c5f0327dbf..0000000000000000000000000000000000000000
--- a/board/delta/lowlevel_init.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-.macro wait time
-	ldr		r2, =OSCR
-	mov		r3, #0
-	str		r3, [r2]
-0:
-	ldr		r3, [r2]
-	cmp		r3, \time
-	bls		0b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Set up GPIO pins first */
-	mov	 r10, lr
-
-	/*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
-	ldr		r0, =GPIO97
-	ldr		r1, =0x801
-	str		r1, [r0]
-
-	ldr		r0, =GPIO98
-	ldr		r1, =0x801
-	str		r1, [r0]
-
-	/* tebrandt - ASCR, clear the RDH bit */
-	ldr		r0, =ASCR
-	ldr		r1, [r0]
-	bic		r1, r1, #0x80000000
-	str		r1, [r0]
-
-mem_init:
-	/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
-	ldr		r0, =ACCR
-	ldr		r1, [r0]
-	orr		r1, r1, #0x3000
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
-	ldr		r0, =MDCNFG
-	ldr		r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
-	/* ldr		r1, =0x80000403 */
-	str		r1, [r0]
-	ldr		r1, [r0]	/* delay until written */
-
-	/* 3. wait nop power up waiting period (200ms)
-	 * optimization: Steps 4+6 can be done during this
-	 */
-	wait #0x300
-
-	/* 4. Perform an initial Rcomp-calibration cycle */
-	ldr		r0, =RCOMP
-	ldr		r1, =0x80000000
-	str		r1, [r0]
-	ldr		r1, [r0]	/* delay until written */
-	/* missing: program for automatic rcomp evaluation cycles */
-
-	/* 5. DDR DRAM strobe delay calibration */
-	ldr		r0, =DDR_HCAL
-	ldr		r1, =0x88000007
-	str		r1, [r0]
-	wait		#5
-	ldr		r1, [r0]	/* delay until written */
-
-	/* Set MDMRS */
-	ldr		r0, =MDMRS
-	ldr		r1, =0x60000033
-	str		r1, [r0]
-	wait	#300
-
-	/* Configure MDREFR */
-	ldr		r0, =MDREFR
-	ldr		r1, =0x00000006
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* Enable the dynamic memory controller */
-	ldr		r0, =MDCNFG
-	ldr		r1, [r0]
-	orr		r1, r1, #MDCNFG_DMCEN
-	str		r1, [r0]
-
-#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
-	/* scrub/init SDRAM if enabled/present */
-	ldr	r8, =CONFIG_SYS_DRAM_BASE	/* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
-	ldr	r9, =CONFIG_SYS_DRAM_SIZE	/* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
-	mov	r0, #0			/* scrub with 0x0000:0000 */
-	mov	r1, #0
-	mov	r2, #0
-	mov	r3, #0
-	mov	r4, #0
-	mov	r5, #0
-	mov	r6, #0
-	mov	r7, #0
-10:	/* fastScrubLoop */
-	subs	r9, r9, #32	/* 8 words/line */
-	stmia	r8!, {r0-r7}
-	beq	15f
-	b	10b
-#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
-
-15:
-	/* Mask all interrupts */
-	mov	r1, #0
-	mcr	p6, 0, r1, c1, c0, 0	@ ICMR
-
-	/* Disable software and data breakpoints */
-	mov	r0, #0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/* Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-endlowlevel_init:
-	mov	pc, lr
diff --git a/board/delta/nand.c b/board/delta/nand.c
deleted file mode 100644
index 119a587a8d222479f2aa6926febafb2378f2fd5e..0000000000000000000000000000000000000000
--- a/board/delta/nand.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_SYS_DFC_DEBUG1
-# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG1(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG2
-# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG2(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG3
-# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG3(fmt, args...)
-#endif
-
-/* These really don't belong here, as they are specific to the NAND Model */
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr delta_bbt_descr = {
-	.options = 0,
-	.offs = 0,
-	.len = 2,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout delta_oob = {
-	.eccbytes = 6,
-	.eccpos = {2, 3, 4, 5, 6, 7},
-	.oobfree = { {8, 2}, {12, 4} }
-};
-
-/*
- * not required for Monahans DFC
- */
-static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	return;
-}
-
-#if 0
-/* read device ready pin */
-static int dfc_device_ready(struct mtd_info *mtdinfo)
-{
-	if(NDSR & NDSR_RDY)
-		return 1;
-	else
-		return 0;
-	return 0;
-}
-#endif
-
-/*
- * Write buf to the DFC Controller Data Buffer
- */
-static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	unsigned long bytes_multi = len & 0xfffffffc;
-	unsigned long rest = len & 0x3;
-	unsigned long *long_buf;
-	int i;
-
-	DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
-	if(bytes_multi) {
-		for(i=0; i<bytes_multi; i+=4) {
-			long_buf = (unsigned long*) &buf[i];
-			writel(*long_buf, NDDB);
-		}
-	}
-	if(rest) {
-		printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
-	}
-	return;
-}
-
-
-static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
-{
-	int i=0, j;
-
-	/* we have to be carefull not to overflow the buffer if len is
-	 * not a multiple of 4 */
-	unsigned long bytes_multi = len & 0xfffffffc;
-	unsigned long rest = len & 0x3;
-	unsigned long *long_buf;
-
-	DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
-	/* if there are any, first copy multiple of 4 bytes */
-	if(bytes_multi) {
-		for(i=0; i<bytes_multi; i+=4) {
-			long_buf = (unsigned long*) &buf[i];
-			*long_buf = readl(NDDB);
-		}
-	}
-
-	/* ...then the rest */
-	if(rest) {
-		unsigned long rest_data = NDDB;
-		for(j=0;j<rest; j++)
-			buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
-	}
-
-	return;
-}
-
-/*
- * read a word. Not implemented as not used in NAND code.
- */
-static u16 dfc_read_word(struct mtd_info *mtd)
-{
-	printf("dfc_read_word: UNIMPLEMENTED.\n");
-	return 0;
-}
-
-/* global var, too bad: mk@tbd: move to ->priv pointer */
-static unsigned long read_buf = 0;
-static int bytes_read = -1;
-
-/*
- * read a byte from NDDB Because we can only read 4 bytes from NDDB at
- * a time, we buffer the remaining bytes. The buffer is reset when a
- * new command is sent to the chip.
- *
- * WARNING:
- * This function is currently only used to read status and id
- * bytes. For these commands always 8 bytes need to be read from
- * NDDB. So we read and discard these bytes right now. In case this
- * function is used for anything else in the future, we must check
- * what was the last command issued and read the appropriate amount of
- * bytes respectively.
- */
-static u_char dfc_read_byte(struct mtd_info *mtd)
-{
-	unsigned char byte;
-	unsigned long dummy;
-
-	if(bytes_read < 0) {
-		read_buf = readl(NDDB);
-		dummy = readl(NDDB);
-		bytes_read = 0;
-	}
-	byte = (unsigned char) (read_buf>>(8 * bytes_read++));
-	if(bytes_read >= 4)
-		bytes_read = -1;
-
-	DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
-	return byte;
-}
-
-/* calculate delta between OSCR values start and now  */
-static unsigned long get_delta(unsigned long start)
-{
-	unsigned long cur = readl(OSCR);
-
-	if(cur < start) /* OSCR overflowed */
-		return (cur + (start^0xffffffff));
-	else
-		return (cur - start);
-}
-
-/* delay function, this doesn't belong here */
-static void wait_us(unsigned long us)
-{
-	unsigned long start = readl(OSCR);
-	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
-
-	while (get_delta(start) < us) {
-		/* do nothing */
-	}
-}
-
-static void dfc_clear_nddb(void)
-{
-	writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
-	wait_us(CONFIG_SYS_NAND_OTHER_TO);
-}
-
-/* wait_event with timeout */
-static unsigned long dfc_wait_event(unsigned long event)
-{
-	unsigned long ndsr, timeout, start = readl(OSCR);
-
-	if(!event)
-		return 0xff000000;
-	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
-					* OSCR_CLK_FREQ, 1000);
-	else
-		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
-					* OSCR_CLK_FREQ, 1000);
-
-	while(1) {
-		ndsr = readl(NDSR);
-		if(ndsr & event) {
-			writel(readl(NDSR) | event, NDSR);
-			break;
-		}
-		if(get_delta(start) > timeout) {
-			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
-			return 0xff000000;
-		}
-
-	}
-	return ndsr;
-}
-
-/* we don't always wan't to do this */
-static void dfc_new_cmd(void)
-{
-	int retry = 0;
-	unsigned long status;
-
-	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
-		/* Clear NDSR */
-		writel(0xfff, NDSR);
-
-		/* set NDCR[NDRUN] */
-		if (!(readl(NDCR) & NDCR_ND_RUN))
-			writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
-
-		status = dfc_wait_event(NDSR_WRCMDREQ);
-
-		if(status & NDSR_WRCMDREQ)
-			return;
-
-		DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
-		dfc_clear_nddb();
-	}
-	DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
-}
-
-/* this function is called after Programm and Erase Operations to
- * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
-{
-	unsigned long ndsr=0, event=0;
-	int state = this->state;
-
-	if(state == FL_WRITING) {
-		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
-	} else if(state == FL_ERASING) {
-		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
-	}
-
-	ndsr = dfc_wait_event(event);
-
-	if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
-		return(0x1); /* Status Read error */
-	return 0;
-}
-
-/* cmdfunc send commands to the DFC */
-static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
-			int column, int page_addr)
-{
-	/* register struct nand_chip *this = mtd->priv; */
-	unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
-
-	/* clear the ugly byte read buffer */
-	bytes_read = -1;
-	read_buf = 0;
-
-	switch (command) {
-	case NAND_CMD_READ0:
-		DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		dfc_new_cmd();
-		ndcb0 = (NAND_CMD_READ0 | (4<<16));
-		column >>= 1; /* adjust for 16 bit bus */
-		ndcb1 = (((column>>1) & 0xff) |
-			 ((page_addr<<8) & 0xff00) |
-			 ((page_addr<<8) & 0xff0000) |
-			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_READ1:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
-		goto end;
-	case NAND_CMD_READOOB:
-		DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
-		goto end;
-	case NAND_CMD_READID:
-		dfc_new_cmd();
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
-		ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_PAGEPROG:
-		/* sent as a multicommand in NAND_CMD_SEQIN */
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
-		goto end;
-	case NAND_CMD_ERASE1:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		dfc_new_cmd();
-		ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
-		ndcb1 = (page_addr & 0x00ffffff);
-		goto write_cmd;
-	case NAND_CMD_ERASE2:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
-		goto end;
-	case NAND_CMD_SEQIN:
-		/* send PAGE_PROG command(0x1080) */
-		dfc_new_cmd();
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
-		column >>= 1; /* adjust for 16 bit bus */
-		ndcb1 = (((column>>1) & 0xff) |
-			 ((page_addr<<8) & 0xff00) |
-			 ((page_addr<<8) & 0xff0000) |
-			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
-		event = NDSR_WRDREQ;
-		goto write_cmd;
-	case NAND_CMD_STATUS:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
-		dfc_new_cmd();
-		ndcb0 = NAND_CMD_STATUS | (4<<21);
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_RESET:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
-		ndcb0 = NAND_CMD_RESET | (5<<21);
-		event = NDSR_CS0_CMDD;
-		goto write_cmd;
-	default:
-		printk("dfc_cmdfunc: error, unsupported command.\n");
-		goto end;
-	}
-
- write_cmd:
-	writel(ndcb0, NDCB0);
-	writel(ndcb1, NDCB0);
-	writel(ndcb2, NDCB0);
-
-	/*  wait_event: */
-	dfc_wait_event(event);
- end:
-	return;
-}
-
-static void dfc_gpio_init(void)
-{
-	DFC_DEBUG2("Setting up DFC GPIO's.\n");
-
-	/* no idea what is done here, see zylonite.c */
-	writel(0x1, GPIO4);
-
-	writel(0x00000001, DF_ALE_nWE1);
-	writel(0x00000001, DF_ALE_nWE2);
-	writel(0x00000001, DF_nCS0);
-	writel(0x00000001, DF_nCS1);
-	writel(0x00000001, DF_nWE);
-	writel(0x00000001, DF_nRE);
-	writel(0x00000001, DF_IO0);
-	writel(0x00000001, DF_IO8);
-	writel(0x00000001, DF_IO1);
-	writel(0x00000001, DF_IO9);
-	writel(0x00000001, DF_IO2);
-	writel(0x00000001, DF_IO10);
-	writel(0x00000001, DF_IO3);
-	writel(0x00000001, DF_IO11);
-	writel(0x00000001, DF_IO4);
-	writel(0x00000001, DF_IO12);
-	writel(0x00000001, DF_IO5);
-	writel(0x00000001, DF_IO13);
-	writel(0x00000001, DF_IO6);
-	writel(0x00000001, DF_IO14);
-	writel(0x00000001, DF_IO7);
-	writel(0x00000001, DF_IO15);
-
-	writel(0x1901, DF_nWE);
-	writel(0x1901, DF_nRE);
-	writel(0x1900, DF_CLE_nOE);
-	writel(0x1901, DF_ALE_nWE1);
-	writel(0x1900, DF_INT_RnB);
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand_new.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for  accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
- *   only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
- * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
-
-	/* set up GPIO Control Registers */
-	dfc_gpio_init();
-
-	/* turn on the NAND Controller Clock (104 MHz @ D0) */
-	writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
-
-#undef CONFIG_SYS_TIMING_TIGHT
-#ifndef CONFIG_SYS_TIMING_TIGHT
-	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tCH);
-	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tCS);
-	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tWH);
-	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tWP);
-	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tRH);
-	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tRP);
-	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
-		 DFC_MAX_tR);
-	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
-		   DFC_MAX_tWHR);
-	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tAR);
-#else /* this is the tight timing */
-
-	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
-		  DFC_MAX_tCH);
-	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
-		  DFC_MAX_tCS);
-	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
-		  DFC_MAX_tWH);
-	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
-		  DFC_MAX_tWP);
-	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
-		  DFC_MAX_tRH);
-	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
-		  DFC_MAX_tRP);
-	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
-		 DFC_MAX_tR);
-	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
-		   DFC_MAX_tWHR);
-	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
-		  DFC_MAX_tAR);
-#endif /* CONFIG_SYS_TIMING_TIGHT */
-
-
-	DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
-
-	/* tRP value is split in the register */
-	if(tRP & (1 << 4)) {
-		tRP_high = 1;
-		tRP &= ~(1 << 4);
-	} else {
-		tRP_high = 0;
-	}
-
-	writel((tCH << 19) |
-		(tCS << 16) |
-		(tWH << 11) |
-		(tWP << 8) |
-		(tRP_high << 6) |
-		(tRH << 3) |
-		(tRP << 0),
-		NDTR0CS0);
-
-	writel((tR << 16) |
-		(tWHR << 4) |
-		(tAR << 0),
-		NDTR1CS0);
-
-	/* If it doesn't work (unlikely) think about:
-	 *  - ecc enable
-	 *  - chip select don't care
-	 *  - read id byte count
-	 *
-	 * Intentionally enabled by not setting bits:
-	 *  - dma (DMA_EN)
-	 *  - page size = 512
-	 *  - cs don't care, see if we can enable later!
-	 *  - row address start position (after second cycle)
-	 *  - pages per block = 32
-	 *  - ND_RDY : clears command buffer
-	 */
-	/* NDCR_NCSX |		/\* Chip select busy don't care *\/ */
-
-	writel(NDCR_SPARE_EN |		/* use the spare area */
-		NDCR_DWIDTH_C |		/* 16bit DFC data bus width  */
-		NDCR_DWIDTH_M |		/* 16 bit Flash device data bus width */
-		(2 << 16) |		/* read id count = 7 ???? mk@tbd */
-		NDCR_ND_ARB_EN |	/* enable bus arbiter */
-		NDCR_RDYM |		/* flash device ready ir masked */
-		NDCR_CS0_PAGEDM |	/* ND_nCSx page done ir masked */
-		NDCR_CS1_PAGEDM |
-		NDCR_CS0_CMDDM |	/* ND_CSx command done ir masked */
-		NDCR_CS1_CMDDM |
-		NDCR_CS0_BBDM |		/* ND_CSx bad block detect ir masked */
-		NDCR_CS1_BBDM |
-		NDCR_DBERRM |		/* double bit error ir masked */
-		NDCR_SBERRM |		/* single bit error ir masked */
-		NDCR_WRDREQM |		/* write data request ir masked */
-		NDCR_RDDREQM |		/* read data request ir masked */
-		NDCR_WRCMDREQM,		/* write command request ir masked */
-		NDCR);
-
-
-	/* wait 10 us due to cmd buffer clear reset */
-	/*	wait(10); */
-
-
-	nand->cmd_ctrl = dfc_hwcontrol;
-/*	nand->dev_ready = dfc_device_ready; */
-	nand->ecc.mode = NAND_ECC_SOFT;
-	nand->ecc.layout = &delta_oob;
-	nand->options = NAND_BUSWIDTH_16;
-	nand->waitfunc = dfc_wait;
-	nand->read_byte = dfc_read_byte;
-	nand->read_word = dfc_read_word;
-	nand->read_buf = dfc_read_buf;
-	nand->write_buf = dfc_write_buf;
-
-	nand->cmdfunc = dfc_cmdfunc;
-	nand->badblock_pattern = &delta_bbt_descr;
-	return 0;
-}
-
-#endif
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
index 351095a48a9299872339d6be8c9e8ca231ba8aa4..88565d91da7ba6a1beeca1a1edf5fc66e730defd 100644
--- a/board/esd/du440/init.S
+++ b/board/esd/du440/init.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <asm/mmu.h>
 #include <config.h>
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index 96f7206b30775d8b5701640d9d39b30bbf5bbc2e..b99a8e9792bfb2e8b4e9835db9a15e27645b0e56 100644
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -19,6 +19,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <asm/mmu.h>
 #include <config.h>
diff --git a/board/fads/fads.h b/board/fads/fads.h
index 38abc70d4aaa5a7366dffc0ff6979eb479069e71..3dc535878df93190c9a41f0f3026b514ebe4972c 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -164,9 +164,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/board/freescale/mx51evk/config.mk b/board/freescale/mx51evk/config.mk
index 716fca9d229166cfde4bb419f9d41ee2222b787f..6e90671d0e8a1e4c268fb094c0d4b2a5f9d1f7c8 100644
--- a/board/freescale/mx51evk/config.mk
+++ b/board/freescale/mx51evk/config.mk
@@ -20,7 +20,6 @@
 # MA 02111-1307 USA
 #
 
-LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
 CONFIG_SYS_TEXT_BASE = 0x97800000
 IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
 ALL += $(obj)u-boot.imx
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index c8d7d3964e3f368ba41e6faa92189c9fca843e88..2160d5a49bfbe03df1cc535d47814e071dc43503 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -52,9 +52,9 @@ u32 get_board_rev(void)
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
-			PHYS_SDRAM_1_SIZE);
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
 	return 0;
 }
 
@@ -188,10 +188,10 @@ static void power_init(void)
 	val &= ~PWGT2SPIEN;
 	pmic_reg_write(REG_POWER_MISC, val);
 
-	/* Write needed to update Charger 0 */
-	pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
-		ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
-		OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
+	/* Externally powered */
+	val = pmic_reg_read(REG_CHARGE);
+	val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+	pmic_reg_write(REG_CHARGE, val);
 
 	/* power up the system first */
 	pmic_reg_write(REG_POWER_MISC, PWUP);
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
new file mode 100644
index 0000000000000000000000000000000000000000..d3bd2330943b573c4d1264e10f3aa8b118b9a4b3
--- /dev/null
+++ b/board/gdsys/405ep/405ep.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+int board_early_init_f(void)
+{
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
+	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
+	 * -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+
+	/*
+	 * setup io-latches for reset
+	 */
+	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+
+	/*
+	 * wait for fpga-done
+	 * fail ungraceful if fpga is not configuring properly
+	 */
+	while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
+		;
+
+	/*
+	 * setup io-latches for boot (stop reset)
+	 */
+	udelay(10);
+	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+	/*
+	 * wait for fpga out of reset
+	 * fail ungraceful if fpga is not working properly
+	 */
+	while (1) {
+		fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
+		if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
+			REFLECTION_TESTPATTERN_INV)
+			break;
+	}
+
+	return 0;
+}
diff --git a/board/delta/Makefile b/board/gdsys/405ep/Makefile
similarity index 86%
rename from board/delta/Makefile
rename to board/gdsys/405ep/Makefile
index 648e00c3146fc37c560a0d1d312cc3a4533b34da..13dff52d77b6b18ef66cc65d818211b8efae15fe 100644
--- a/board/delta/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -1,7 +1,6 @@
-
 #
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -26,14 +25,17 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= delta.o nand.o
-SOBJS	:= lowlevel_init.o
+COBJS-$(CONFIG_IO) += io.o
+COBJS-$(CONFIG_IOCON) += iocon.o
+
+COBJS   := $(BOARD).o $(COBJS-y)
+SOBJS   =
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+$(LIB):	$(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 clean:
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
new file mode 100644
index 0000000000000000000000000000000000000000..80877b61ffa525d0d6c4d068d26f85bbb6618735
--- /dev/null
+++ b/board/gdsys/405ep/io.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <miiphy.h>
+
+#include "../common/fpga.h"
+
+#define PHYREG_CONTROL				0
+#define PHYREG_PAGE_ADDRESS			22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
+
+enum {
+	REG_VERSIONS = 0x0002,
+	REG_FPGA_FEATURES = 0x0004,
+	REG_FPGA_VERSION = 0x0006,
+	REG_QUAD_SERDES_RESET = 0x0012,
+};
+
+enum {
+	UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_121 = 2,
+	HWVER_122 = 3,
+};
+
+int configure_gbit_phy(unsigned char addr)
+{
+	unsigned short value;
+
+	/* select page 2 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0002))
+		goto err_out;
+	/* disable SGMII autonegotiation */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
+		goto err_out;
+	/* select page 0 */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PAGE_ADDRESS, 0x0000))
+		goto err_out;
+	/* switch from powerdown to normal operation */
+	if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
+		goto err_out;
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
+		goto err_out;
+	/* reset phy so settings take effect */
+	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+		PHYREG_CONTROL, 0x9140))
+		goto err_out;
+
+	return 0;
+
+err_out:
+	printf("Error writing to the PHY addr=%02x\n", addr);
+	return -1;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u16 versions = fpga_get_reg(REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_channels;
+	unsigned feature_expansion;
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_channels = fpga_features & 0x007f;
+	feature_expansion = fpga_features & (1<<15);
+
+	printf("Board: ");
+
+	printf("CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (unit_type) {
+	case UNITTYPE_CCD_SWITCH:
+		printf("CCD-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	case HWVER_121:
+		printf(" HW-Ver 1.21\n");
+		break;
+
+	case HWVER_122:
+		printf(" HW-Ver 1.22\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)", feature_channels);
+
+	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+
+	return 0;
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+	unsigned int k;
+
+	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+		bb_miiphy_read, bb_miiphy_write);
+
+	for (k = 0; k < 32; ++k)
+		configure_gbit_phy(k);
+
+	/* take fpga serdes blocks out of reset */
+	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+
+	return 0;
+}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
new file mode 100644
index 0000000000000000000000000000000000000000..ecd6cb2396c08883fbd65297cf2d868c621dd088
--- /dev/null
+++ b/board/gdsys/405ep/iocon.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+#include "../common/osd.h"
+
+enum {
+	REG_VERSIONS = 0x0002,
+	REG_FPGA_VERSION = 0x0004,
+	REG_FPGA_FEATURES = 0x0006,
+};
+
+enum {
+	UNITTYPE_MAIN_SERVER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+	HWVER_100 = 0,
+	HWVER_104 = 1,
+	HWVER_110 = 2,
+};
+
+enum {
+	COMPRESSION_NONE = 0,
+	COMPRESSION_TYPE1_DELTA,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_147456 = 0,
+};
+
+enum {
+	RAM_DDR2_32 = 0,
+};
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	u16 versions = fpga_get_reg(REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_osd;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_compression = (fpga_features & 0xe000) >> 13;
+	feature_osd = fpga_features & (1<<11);
+	feature_audio = (fpga_features & 0x0600) >> 9;
+	feature_sysclock = (fpga_features & 0x0180) >> 7;
+	feature_ramconfig = (fpga_features & 0x0060) >> 5;
+	feature_carriers = (fpga_features & 0x000c) >> 2;
+	feature_video_channels = fpga_features & 0x0003;
+
+	printf("Board: ");
+
+	printf("IoCon");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	puts("\n       ");
+
+	switch (unit_type) {
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel");
+		break;
+
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf(" HW-Ver 1.00\n");
+		break;
+
+	case HWVER_104:
+		printf(" HW-Ver 1.04\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+
+	switch (feature_compression) {
+	case COMPRESSION_NONE:
+		printf(" no compression");
+		break;
+
+	case COMPRESSION_TYPE1_DELTA:
+		printf(" type1-deltacompression");
+		break;
+
+	default:
+		printf(" compression %d(not supported)", feature_compression);
+		break;
+	}
+
+	printf(", %sosd", feature_osd ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_sysclock) {
+	case SYSCLK_147456:
+		printf("clock 147.456 MHz");
+		break;
+
+	default:
+		printf("clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	switch (feature_ramconfig) {
+	case RAM_DDR2_32:
+		printf(", RAM 32 bit DDR2");
+		break;
+
+	default:
+		printf(", RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s)", feature_carriers);
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	return osd_probe();
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ */
+void fpga_gpio_set(int pin)
+{
+	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+}
+
+void fpga_gpio_clear(int pin)
+{
+	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+}
+
+int fpga_gpio_get(int pin)
+{
+	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+}
diff --git a/board/xsengine/Makefile b/board/gdsys/common/Makefile
similarity index 80%
rename from board/xsengine/Makefile
rename to board/gdsys/common/Makefile
index fc239358b2362466b016273eb714f585c1c59c6b..93cde5aa17472807c38ac9dbe1df6964ccada31c 100644
--- a/board/xsengine/Makefile
+++ b/board/gdsys/common/Makefile
@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -23,16 +23,23 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(BOARD).a
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
 
-COBJS	:= xsengine.o flash.o
-SOBJS	:= lowlevel_init.o
+LIB	= $(obj)lib$(VENDOR).a
+
+COBJS-$(CONFIG_IO) += miiphybb.o
+COBJS-$(CONFIG_IOCON) += osd.o
+
+COBJS   := $(COBJS-y)
+SOBJS   =
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+$(LIB):	$(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 clean:
diff --git a/onenand_ipl/board/vpac270/lowlevel_init.S b/board/gdsys/common/fpga.h
similarity index 69%
rename from onenand_ipl/board/vpac270/lowlevel_init.S
rename to board/gdsys/common/fpga.h
index e79d8dd1aba28355d6ae79f0c26bae936e0a6d14..c1434e7ab2eaaee945590983f5c8d6a36cd097ed 100644
--- a/onenand_ipl/board/vpac270/lowlevel_init.S
+++ b/board/gdsys/common/fpga.h
@@ -1,8 +1,6 @@
 /*
- * Voipac PXA270 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,12 +21,17 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+static inline u16 fpga_get_reg(unsigned reg)
+{
+	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
+}
+
+static inline void fpga_set_reg(unsigned reg, u16 val)
+{
+	return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
+}
 
-.globl lowlevel_init
-lowlevel_init:
-	pxa_clock_setup
-	mov	pc, lr
+#endif
diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c
new file mode 100644
index 0000000000000000000000000000000000000000..e56e966509cd62d2a17dc4fffd863bfd91e80efb
--- /dev/null
+++ b/board/gdsys/common/miiphybb.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+static int io_bb_mii_init(struct bb_miiphy_bus *bus)
+{
+	return 0;
+}
+
+static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
+
+	return 0;
+}
+
+static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
+
+	return 0;
+}
+
+static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
+
+	return 0;
+}
+
+static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	*v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
+
+	return 0;
+}
+
+static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
+
+	return 0;
+}
+
+static int io_bb_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = CONFIG_SYS_GBIT_MII_BUSNAME,
+		.init = io_bb_mii_init,
+		.mdio_active = io_bb_mdio_active,
+		.mdio_tristate = io_bb_mdio_tristate,
+		.set_mdio = io_bb_set_mdio,
+		.get_mdio = io_bb_get_mdio,
+		.set_mdc = io_bb_set_mdc,
+		.delay = io_bb_delay,
+	}
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+			  sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
new file mode 100644
index 0000000000000000000000000000000000000000..05800ffba487bb2b895eabc13030b7ce29ccf38d
--- /dev/null
+++ b/board/gdsys/common/osd.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "fpga.h"
+
+#define CH7301_I2C_ADDR 0x75
+
+#define PIXCLK_640_480_60 25180000
+
+#define BASE_WIDTH 32
+#define BASE_HEIGHT 16
+#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
+
+enum {
+	REG_CONTROL = 0x0010,
+	REG_MPC3W_CONTROL = 0x001a,
+	REG_VIDEOCONTROL = 0x0042,
+	REG_OSDVERSION = 0x0100,
+	REG_OSDFEATURES = 0x0102,
+	REG_OSDCONTROL = 0x0104,
+	REG_XY_SIZE = 0x0106,
+	REG_VIDEOMEM = 0x0800,
+};
+
+enum {
+	CH7301_CM = 0x1c,		/* Clock Mode Register */
+	CH7301_IC = 0x1d,		/* Input Clock Register */
+	CH7301_GPIO = 0x1e,		/* GPIO Control Register */
+	CH7301_IDF = 0x1f,		/* Input Data Format Register */
+	CH7301_CD = 0x20,		/* Connection Detect Register */
+	CH7301_DC = 0x21,		/* DAC Control Register */
+	CH7301_HPD = 0x23,		/* Hot Plug Detection Register */
+	CH7301_TCTL = 0x31,		/* DVI Control Input Register */
+	CH7301_TPCP = 0x33,		/* DVI PLL Charge Pump Ctrl Register */
+	CH7301_TPD = 0x34,		/* DVI PLL Divide Register */
+	CH7301_TPVT = 0x35,		/* DVI PLL Supply Control Register */
+	CH7301_TPF = 0x36,		/* DVI PLL Filter Register */
+	CH7301_TCT = 0x37,		/* DVI Clock Test Register */
+	CH7301_TSTP = 0x48,		/* Test Pattern Register */
+	CH7301_PM = 0x49,		/* Power Management register */
+	CH7301_VID = 0x4a,		/* Version ID Register */
+	CH7301_DID = 0x4b,		/* Device ID Register */
+	CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
+};
+
+static void mpc92469ac_calc_parameters(unsigned int fout,
+	unsigned int *post_div, unsigned int *feedback_div)
+{
+	unsigned int n = *post_div;
+	unsigned int m = *feedback_div;
+	unsigned int a;
+	unsigned int b = 14745600 / 16;
+
+	if (fout < 50169600)
+		n = 8;
+	else if (fout < 100339199)
+		n = 4;
+	else if (fout < 200678399)
+		n = 2;
+	else
+		n = 1;
+
+	a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+	m = a / b;
+
+	*post_div = n;
+	*feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned int fout)
+{
+	unsigned int n;
+	unsigned int m;
+	unsigned int bitval = 0;
+	mpc92469ac_calc_parameters(fout, &n, &m);
+
+	switch (n) {
+	case 1:
+		bitval = 0x00;
+		break;
+	case 2:
+		bitval = 0x01;
+		break;
+	case 4:
+		bitval = 0x02;
+		break;
+	case 8:
+		bitval = 0x03;
+		break;
+	}
+
+	fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
+}
+
+static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+{
+	unsigned int k;
+
+	for (k = 0; k < charcount; ++k) {
+		if (offset + k >= BUFSIZE)
+			return -1;
+		fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
+	}
+
+	return charcount;
+}
+
+static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned x;
+	unsigned y;
+	unsigned charcount;
+	unsigned len;
+	u8 color;
+	unsigned int k;
+	u16 buf[BUFSIZE];
+	char *text;
+
+	if (argc < 5) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+	color = simple_strtoul(argv[3], NULL, 16);
+	text = argv[4];
+	charcount = strlen(text);
+	len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+	for (k = 0; k < len; ++k)
+		buf[k] = (text[k] << 8) | color;
+
+	return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
+}
+
+int osd_probe(void)
+{
+	u8 value;
+	u16 version = fpga_get_reg(REG_OSDVERSION);
+	u16 features = fpga_get_reg(REG_OSDFEATURES);
+	unsigned width;
+	unsigned height;
+
+	width = ((features & 0x3f00) >> 8) + 1;
+	height = (features & 0x001f) + 1;
+
+	printf("OSD:   Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+		version/100, version%100, width, height);
+
+	value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+	if (value != 0x17) {
+		printf("       Probing CH7301 failed, DID %02x\n", value);
+		return -1;
+	}
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+
+	mpc92469ac_set(PIXCLK_640_480_60);
+	fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
+	fpga_set_reg(REG_OSDCONTROL, 0x0049);
+
+	fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
+
+	return 0;
+}
+
+int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned x;
+	unsigned y;
+	unsigned k;
+	u16 buffer[BASE_WIDTH];
+	char *rp;
+	u16 *wp = buffer;
+	unsigned count = (argc > 4) ?  simple_strtoul(argv[4], NULL, 16) : 1;
+
+	if ((argc < 4) || (strlen(argv[3]) % 4)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	x = simple_strtoul(argv[1], NULL, 16);
+	y = simple_strtoul(argv[2], NULL, 16);
+	rp = argv[3];
+
+
+	while (*rp) {
+		char substr[5];
+
+		memcpy(substr, rp, 4);
+		substr[4] = 0;
+		*wp = simple_strtoul(substr, NULL, 16);
+
+		rp += 4;
+		wp++;
+		if (wp - buffer > BASE_WIDTH)
+			break;
+	}
+
+	for (k = 0; k < count; ++k) {
+		unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
+		osd_write_videomem(offset, buffer, wp - buffer);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	osdw, 5, 0, osd_write,
+	"write 16-bit hex encoded buffer to osd memory",
+	"pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+	osdp, 5, 0, osd_print,
+	"write ASCII buffer to osd memory",
+	"pos_x pos_y color text\n"
+);
diff --git a/board/trizepsiv/pxavoltage.S b/board/gdsys/common/osd.h
similarity index 84%
rename from board/trizepsiv/pxavoltage.S
rename to board/gdsys/common/osd.h
index 9659c2b0213bf0eee31f632aee17458b3b0e1994..4431cbc091c3e5323bf8df8398324e2cd43d85b1 100644
--- a/board/trizepsiv/pxavoltage.S
+++ b/board/gdsys/common/osd.h
@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,9 +21,9 @@
  * MA 02111-1307 USA
  */
 
-#include <asm/arch/pxa-regs.h>
+#ifndef _OSD_H_
+#define _OSD_H_
 
-		.global	initPXAvoltage
+int osd_probe(void);
 
-initPXAvoltage:
-		mov	pc, lr
+#endif
diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S
index ba750cb538b13ee7722628a9531df1cbcbcf4610..4a40e4b0bb7dff79db849b01e239381a12e3a12c 100644
--- a/board/gdsys/gdppc440etx/init.S
+++ b/board/gdsys/gdppc440etx/init.S
@@ -24,6 +24,7 @@
 * MA 02111-1307 USA
 */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 
diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S
index 5a819c2a30ccbb5c7b1ea579475842a38c9042fb..7513f1d3c3243a93f9767135e87c420f9b0ed91e 100644
--- a/board/gdsys/intip/init.S
+++ b/board/gdsys/intip/init.S
@@ -25,6 +25,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 #include <asm/mmu.h>
diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S
index 531dcdf4ae22e5dd00c2c6f7718df775394927ea..61b4b55534226357e1f74120baf3f484c2feeec0 100644
--- a/board/hidden_dragon/early_init.S
+++ b/board/hidden_dragon/early_init.S
@@ -25,6 +25,7 @@
 #define __ASSEMBLY__	1
 #endif
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/processor.h>
 #include <mpc824x.h>
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 47b2195557920adc8f7a879bef8fb9f5fdebb75d..a9e4448f4d0d157cca8a1c479e3e2859a148648e 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -80,7 +80,7 @@ void lite5200b_wakeup(void)
 	/* jump back to linux kernel code */
 	linux_wakeup = SAVED_ADDR;
 	printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
-			linux_wakeup);
+			(unsigned long)linux_wakeup);
 	linux_wakeup();
 }
 #else
diff --git a/board/innokom/Makefile b/board/innokom/Makefile
index afae217242cd32b590ff385807dd7c1961cbc4e6..ba248c03e73536580b225d59b087254e27851744 100644
--- a/board/innokom/Makefile
+++ b/board/innokom/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= innokom.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/innokom/config.mk b/board/innokom/config.mk
deleted file mode 100644
index 9e4655585d7fe4fa0782246ef64017d5cb99f4ff..0000000000000000000000000000000000000000
--- a/board/innokom/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index 2c5112521be2396c957dd64452b48dfc155a9e7d..e658c3529a8f5690c907fa35dbbecb291e040e47 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -100,8 +100,9 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
 	gd->bd->bi_boot_params = 0xa0000100;
@@ -110,22 +111,20 @@ int board_init (void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
-
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
-
 /**
  * innokom_set_led: - switch LEDs on or off
  *
diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S
deleted file mode 100644
index 55169be45eaf2bb9d085ac8a96186a33e0029731..0000000000000000000000000000000000000000
--- a/board/innokom/lowlevel_init.S
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
-/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
-/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/*	ldr	r1,	=LED_BLANK */
-/*	mov	r0,	#0xFF */
-/*	str	r0,	[r1]		/  turn on hex leds */
-/* */
-/*loop: */
-/* */
-/*   ldr	r0, =0xB0070001 */
-/*   ldr	r1, =_LED */
-/*   str	r0, [r1]		/  hex display */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
-	adr	r3, mem_init		/* r0 <- current position of code   */
-	ldr	r2, =mem_init
-	cmp	r3, r2			/* skip init if in place            */
-	beq	initirqs
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	ldr	r2,	=0xFFF
-	and	r3,	r3, r2
-	ldr	r4,	=0x03ca4000
-	orr	r4,	r4,  r3
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,	[r1, #MDREFR_OFFSET]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* Step 4a: assert MDREFR:K?RUN and configure                       */
-	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
-
-	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4, #(MDREFR_SLFRSH)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
-
-	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 �sec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	/*          There should 9 writes, since the first write doesn't    */
-	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
-	/*          PXA210 Processors Specification Update,                 */
-	/*          Jan 2003, Errata #116, page 30.                         */
-
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr	r3, [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str	r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-/*
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-*/
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size                                                  */
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR			/* enable no sources        */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#ifndef DEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr
diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
index 35865e06a490f2d7be8098738b0bc8e24529d429..019f93f20075c33df663df569d957bd32ee551ea 100644
--- a/board/isee/igep0030/config.mk
+++ b/board/isee/igep0030/config.mk
@@ -31,4 +31,3 @@
 
 # For use with external or internal boots.
 TEXT_BASE = 0x80008000
-
diff --git a/board/keymile/km_arm/config.mk b/board/keymile/km_arm/config.mk
deleted file mode 100644
index df4828cdc9297c71a694402a5b23e1ef170ab8b3..0000000000000000000000000000000000000000
--- a/board/keymile/km_arm/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-CONFIG_SYS_TEXT_BASE = 0x004000000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 7c0b858887397bbe979f060fc3054bb093802167..2e20644fbaff742e5758a46e8b480e7bb33d8556 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -143,7 +143,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-int board_init(void)
+int board_early_init_f(void)
 {
 	u32 tmp;
 
@@ -160,14 +160,6 @@ int board_init(void)
 	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
 	printf("KM: setting NAND mode\n");
 
-	/*
-	 * arch number of board
-	 */
-	gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
 	kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
@@ -179,6 +171,20 @@ int board_init(void)
 	kw_gpio_set_valid(SUEN3_ENV_WP, 38);
 	kw_gpio_direction_output(SUEN3_ENV_WP, 1);
 #endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
 	return 0;
 }
 
@@ -225,20 +231,6 @@ U_BOOT_CMD(
 	);
 #endif
 
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
-						       kw_sdram_bs(i));
-	}
-
-	return 0;
-}
-#else
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -259,7 +251,6 @@ void dram_init_banksize(void)
 						       kw_sdram_bs(i));
 	}
 }
-#endif
 
 /* Configure and enable MV88E1118 PHY */
 void reset_phy(void)
diff --git a/board/korat/init.S b/board/korat/init.S
index bfc6bc15253a982c4ce9ce935a236837044605a3..3741277f60a0f64a1f6a87cdd43c7a1ef713e168 100644
--- a/board/korat/init.S
+++ b/board/korat/init.S
@@ -19,6 +19,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <asm/mmu.h>
 #include <config.h>
diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile
index 65923070c41ae2c1c7883431d0d2ecb36efce3f5..2853bca8d7798ef5ec1dd2409d174f0d3abdff2d 100644
--- a/board/lubbock/Makefile
+++ b/board/lubbock/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= lubbock.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/lubbock/config.mk b/board/lubbock/config.mk
deleted file mode 100644
index f30f695de2b7c51c555c06f430ca6654cddc1cbe..0000000000000000000000000000000000000000
--- a/board/lubbock/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S
deleted file mode 100644
index db6f69d36ea3e7dacb2df067dd1a1a181bd3d093..0000000000000000000000000000000000000000
--- a/board/lubbock/lowlevel_init.S
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
-	ldr     r2,     =0xFFF
-	and     r3,     r3,  r2
-	ldr	r4,	=0x03ca4000
-	orr     r4,     r4,  r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4                            */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	orr	r4,	r4,	#(MDREFR_SLFRSH)
-	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4,	#(MDREFR_SLFRSH)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 �sec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	    str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-    ldr     r1, =DRAM_SIZE
-	 str	   r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-    ldr	r0, =ICMR /* enable no sources */
-	mov r1, #0
-    str r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr
diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c
index d8d6ffbf6174fdfc44318a06fc7fb204cd9568ef..f791c5b904098b38eebb150918353daf6c0199bf 100644
--- a/board/lubbock/lubbock.c
+++ b/board/lubbock/lubbock.c
@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
@@ -55,19 +56,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 8efc8a146e55a2fd65cd100d27608faaec09f709..2014cd7b981125f3ce1baa9ff2c9372ed2c0d9fc 100644
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -23,6 +23,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 #include <asm/mmu.h>
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index eaeec828d70b0407c7cd27b529a73be3b2ef413e..978e6fdeff9d9dae12780f2308dab37ee12851bc 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -78,42 +78,43 @@ int board_init(void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->LOCKTIME = 0xFFFFFF;
+	clk_power->locktime = 0xFFFFFF;
 
 	/* configure MPLL */
-	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (4000);
 
 	/* configure UPLL */
-	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (8000);
 
 	/* set up the I/O ports */
-	gpio->GPACON = 0x007FFFFF;
-	gpio->GPBCON = 0x002AAAAA;
-	gpio->GPBUP = 0x000002BF;
-	gpio->GPCCON = 0xAAAAAAAA;
-	gpio->GPCUP = 0x0000FFFF;
-	gpio->GPDCON = 0xAAAAAAAA;
-	gpio->GPDUP = 0x0000FFFF;
-	gpio->GPECON = 0xAAAAAAAA;
-	gpio->GPEUP = 0x000037F7;
-	gpio->GPFCON = 0x00000000;
-	gpio->GPFUP = 0x00000000;
-	gpio->GPGCON = 0xFFEAFF5A;
-	gpio->GPGUP = 0x0000F0DC;
-	gpio->GPHCON = 0x0028AAAA;
-	gpio->GPHUP = 0x00000656;
+	gpio->gpacon = 0x007FFFFF;
+	gpio->gpbcon = 0x002AAAAA;
+	gpio->gpbup = 0x000002BF;
+	gpio->gpccon = 0xAAAAAAAA;
+	gpio->gpcup = 0x0000FFFF;
+	gpio->gpdcon = 0xAAAAAAAA;
+	gpio->gpdup = 0x0000FFFF;
+	gpio->gpecon = 0xAAAAAAAA;
+	gpio->gpeup = 0x000037F7;
+	gpio->gpfcon = 0x00000000;
+	gpio->gpfup = 0x00000000;
+	gpio->gpgcon = 0xFFEAFF5A;
+	gpio->gpgup = 0x0000F0DC;
+	gpio->gphcon = 0x0028AAAA;
+	gpio->gphup = 0x00000656;
 
 	/* setup correct IRQ modes for NIC */
-	gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+	/* rising edge mode */
+	gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8);
 
 	/* select USB port 2 to be host or device (fix to host for now) */
-	gpio->MISCCR |= 0x08;
+	gpio->misccr |= 0x08;
 
 	/* init serial */
 	gd->baudrate = CONFIG_BAUDRATE;
diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile
index 6722d53927e45f896ed3705fa4874ab435aedecb..cd62642894425f87b0140c7fd330d49697fa37b2 100644
--- a/board/netstal/hcu4/Makefile
+++ b/board/netstal/hcu4/Makefile
@@ -19,24 +19,24 @@
 #
 
 include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-# NOBJS : Netstal common objects
-NOBJS	= fixed_sdram.o nm_bsp.o
-COBJS	= $(BOARD).o
-SOBJS	=
+COBJS	= $(BOARD).o \
+	../common/fixed_sdram.o \
+	../common/nm_bsp.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-NOBJS	:= $(addprefix $(obj)../common/,$(NOBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS) $(NOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $^
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile
index 445677104c8f2d26c294186e06847f60db1ffa54..d037552d709bc481fb5a3e787b93da7bb67c492e 100644
--- a/board/netstal/hcu5/Makefile
+++ b/board/netstal/hcu5/Makefile
@@ -19,22 +19,23 @@
 #
 
 include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-
-# NOBJS : Netstal common objects
-NOBJS	= nm_bsp.o
-COBJS	= $(BOARD).o sdram.o
+COBJS	= $(BOARD).o \
+	sdram.o \
+	../common/nm_bsp.o
 SOBJS	= init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-NOBJS	:= $(addprefix $(obj)../common/,$(NOBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS) $(NOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $^
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
diff --git a/board/netstal/mcu25/Makefile b/board/netstal/mcu25/Makefile
index 6722d53927e45f896ed3705fa4874ab435aedecb..cd62642894425f87b0140c7fd330d49697fa37b2 100644
--- a/board/netstal/mcu25/Makefile
+++ b/board/netstal/mcu25/Makefile
@@ -19,24 +19,24 @@
 #
 
 include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-# NOBJS : Netstal common objects
-NOBJS	= fixed_sdram.o nm_bsp.o
-COBJS	= $(BOARD).o
-SOBJS	=
+COBJS	= $(BOARD).o \
+	../common/fixed_sdram.o \
+	../common/nm_bsp.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-NOBJS	:= $(addprefix $(obj)../common/,$(NOBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS) $(NOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $^
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
index bcb014db62dc94a572428f90a80eed7e9a4a2360..0cca8ab9ec283ad4d3362af978d25dcbb624c422 100644
--- a/board/palmld/Makefile
+++ b/board/palmld/Makefile
@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= palmld.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmld/config.mk b/board/palmld/config.mk
deleted file mode 100644
index 1d650acd993e3818e66b4f7e6812c5e51e53017e..0000000000000000000000000000000000000000
--- a/board/palmld/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000
diff --git a/board/palmld/lowlevel_init.S b/board/palmld/lowlevel_init.S
deleted file mode 100644
index e3382ee2f24f52d4731f5167fa8fee684d467819..0000000000000000000000000000000000000000
--- a/board/palmld/lowlevel_init.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Palm LifeDrive Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-
-	/* Enable GPIO reset */
-	ldr	r0, =PCFR
-	mov	r1, #0x30
-	str	r1, [r0]
-
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
index 4f0087ea27b142c74003a0422311721c918578c9..5588fe732f2c04be019612676c3b1138ef37bc9f 100644
--- a/board/palmld/palmld.c
+++ b/board/palmld/palmld.c
@@ -33,7 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	/* arch number of Lubbock-Board */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of PalmLD */
 	gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
 
 	/* adress of boot parameters */
@@ -52,12 +56,18 @@ struct serial_device *default_serial_console(void)
 	return &serial_ffuart_device;
 }
 
+extern void pxa_dram_init(void);
 int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
diff --git a/board/palmld/u-boot.lds b/board/palmld/u-boot.lds
deleted file mode 100644
index fb4358beeabcc2cdd1aba7fca2796cec25bfbb7f..0000000000000000000000000000000000000000
--- a/board/palmld/u-boot.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  cpu/pxa/start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
index 20ac4e154c13fc3651dbd0f0cf5000f5f554be23..3a12e6617561be60fc53df1e866dd7ac9d310968 100644
--- a/board/palmtc/Makefile
+++ b/board/palmtc/Makefile
@@ -24,17 +24,16 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= palmtc.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmtc/config.mk b/board/palmtc/config.mk
deleted file mode 100644
index 1d650acd993e3818e66b4f7e6812c5e51e53017e..0000000000000000000000000000000000000000
--- a/board/palmtc/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000
diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c
index 04cb33e6a89c3fd58d673be07d2eade3f03edc0d..25186aefa8c1360014e5c3bf90b2e7fee2a85a0f 100644
--- a/board/palmtc/palmtc.c
+++ b/board/palmtc/palmtc.c
@@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	/* Arch number of Palm Tungsten|C */
 	gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
 
@@ -51,9 +55,16 @@ struct serial_device *default_serial_console(void)
 	return &serial_ffuart_device;
 }
 
+extern void pxa_dram_init(void);
 int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	return 0;
 }
diff --git a/board/palmtc/u-boot.lds b/board/palmtc/u-boot.lds
deleted file mode 100644
index fb4358beeabcc2cdd1aba7fca2796cec25bfbb7f..0000000000000000000000000000000000000000
--- a/board/palmtc/u-boot.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  cpu/pxa/start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
index 9745c14e5a462e74bcb7e4ef0a79d4bb36ccf618..6bd8852a66fc554963146fd92760b732e82d16fb 100644
--- a/board/pcs440ep/init.S
+++ b/board/pcs440ep/init.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <asm/mmu.h>
 #include <config.h>
diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile
index faa26911b82374d459e40bf9f0973b30e6602581..cb0c3d7cb9092bfbc1b58e81c6a06587ba12c27e 100644
--- a/board/pleb2/Makefile
+++ b/board/pleb2/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= pleb2.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/pleb2/config.mk b/board/pleb2/config.mk
deleted file mode 100644
index 079f58eb2f5976c56c1471822a3eb51bc8d3d9cc..0000000000000000000000000000000000000000
--- a/board/pleb2/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE =  0xa1F80000
-#CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S
deleted file mode 100644
index b95ff9cf2faf534533639d9c66fa385de7c27c99..0000000000000000000000000000000000000000
--- a/board/pleb2/lowlevel_init.S
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc	p15,0,\reg,c2,c0,0
-	mov	\reg,\reg
-	sub	pc,pc,#4
-	.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-	/* Set up GPIO pins first */
-
-	ldr	r0,   =GPSR0
-	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR1
-	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR2
-	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR0
-	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR1
-	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR2
-	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER0
-	ldr	r1,   =CONFIG_SYS_GRER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER1
-	ldr	r1,   =CONFIG_SYS_GRER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER2
-	ldr	r1,   =CONFIG_SYS_GRER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER0
-	ldr	r1,   =CONFIG_SYS_GFER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER1
-	ldr	r1,   =CONFIG_SYS_GFER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER2
-	ldr	r1,   =CONFIG_SYS_GFER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR0
-	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR1
-	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR2
-	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_L
-	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_U
-	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_L
-	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_U
-	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_L
-	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_U
-	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
-	str	r1,   [r0]
-
-	/* enable GPIO pins */
-	ldr	r0,   =PSSR
-	ldr	r1,   =CONFIG_SYS_PSSR_VAL
-	str	r1,   [r0]
-
-
-/*********************************************************************
-    Initlialize Memory Controller
-
-    See PXA250 Operating System Developer's Guide
-
-    pause for 200 uSecs- allow internal clocks to settle
-    *Note: only need this if hard reset... doing it anyway for now
-*/
-
-	@ Step 1
-	@ ---- Wait 200 usec
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-	@ get memory controller base address
-	ldr	r1,  =MEMC_BASE
-
-@****************************************************************************
-@  Step 2
-@
-
-	@ Step 2a
-	@ write msc0, read back to ensure data latches
-	@
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]
-
-	@ write msc1
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	@ write msc2
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-
-@ Step 2b
-	@ write mecr
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-
-	@ write mcmem0
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-
-	@ write mcmem1
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-
-	@ write mcatt0
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-
-	@ write mcatt1
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-
-	@ write mcio0
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-
-	@ write mcio1
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-
-@ Step 2c
-	@ fly-by-dma is defeatured on this part
-	@ write flycnfg
-	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	@str	r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ extract DRI field (we need a valid DRI field)
-	@
-	ldr	r2,  =0xFFF
-
-	@ valid DRI field in r3
-	@
-	and	r3,  r3,  r2
-
-	@ get the reset state of MDREFR
-	@
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ clear the DRI field
-	@
-	bic	r4,  r4,  r2
-
-	@ insert the valid DRI field loaded above
-	@
-	orr	r4,  r4,  r3
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-	mov	pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-	@ clear the free-running clock bits
-	@ (clear K0Free, K1Free, K2Free
-	@
-	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4,  #0x00002000
-
-	@ set K1RUN if bank 0 installed
-	@
-	orr	r4,  r4,  #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#else
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@  Step 4
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4,  #0x00002000
-
-	@ set K1RUN for bank 0
-	@
-	orr	r4,  r4,  #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#endif
-
-	@ Step 4d
-	@ fetch platform value of mdcnfg
-	@
-	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic	r2,  r2,  #MDCNFG_DWID0	     @0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str	r2,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4e
-	@ pause for 200 uSecs
-	@
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-	1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-	/* Why is this here??? */
-	mov	r0, #0x78		 @turn everything off
-	mcr	p15, 0, r0, c1, c0, 0	   @(caches off, MMU off, etc.)
-
-	@ Step 4f
-	@ Access memory *not yet enabled* for CBR refresh cycles (8)
-	@ - CBR is generated for all banks
-
-	ldr	r2, =CONFIG_SYS_DRAM_BASE
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-
-	@ Step 4g
-	@get memory controller base address
-	@
-	ldr	r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr	r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr	r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str	r3,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4h
-	@ write mdmrs
-	@
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	@ Done Memory Init
-
-	/*SET_LED 6 */
-
-	@********************************************************************
-	@ Disable (mask) all interrupts at the interrupt controller
-	@
-
-	@ clear the interrupt level register (use IRQ, not FIQ)
-	@
-	mov	r1, #0
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	@ Set interrupt mask register
-	@
-	ldr	r1,  =CONFIG_SYS_ICMR_VAL
-	ldr	r2,  =ICMR
-	str	r1,  [r2]
-
-	@ ********************************************************************
-	@ Disable the peripheral clocks, and set the core clock
-	@
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-	ldr	r1,  =CKEN
-	mov	r2,  #0
-	str	r2,  [r1]
-
-	@ set core clocks
-	@
-	ldr	r2,  =CONFIG_SYS_CCCR_VAL
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-	#ifdef ENABLE32KHZ
-	@ enable the 32Khz oscillator for RTC and PowerManager
-	@
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	@ NOTE:	 spin here until OSCC.OOK get set,
-	@	 meaning the PLL has settled.
-	@
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#endif
-
-	@ Turn on needed clocks
-	@
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN_VAL
-	str	r2,  [r1]
-
-	/*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-   /*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	mov	pc, r10
-
-@ End lowlevel_init
diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c
index 97c37eaa3939d88cbc712473ba2f98518fde886b..5a16cc76e81c5fd0a0b15d5cad8d854e65449167 100644
--- a/board/pleb2/pleb2.c
+++ b/board/pleb2/pleb2.c
@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
@@ -55,17 +56,16 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 119bc534e7b8f9916bb9656a4b102cf95de43fe1..d9961dd18636a9a86425888883e576e2e3092747 100644
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <asm/mmu.h>
 #include <config.h>
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
index 4892b42bc156d8d44dd6504d39cdcbe9cb62b399..2835f37554ce0614c223810e0f51b338f9799700 100644
--- a/board/pxa255_idp/Makefile
+++ b/board/pxa255_idp/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= pxa_idp.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk
deleted file mode 100644
index f30f695de2b7c51c555c06f430ca6654cddc1cbe..0000000000000000000000000000000000000000
--- a/board/pxa255_idp/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S
deleted file mode 100644
index a50760fea4016ab8f8b3911712bf452cbbe1e725..0000000000000000000000000000000000000000
--- a/board/pxa255_idp/lowlevel_init.S
+++ /dev/null
@@ -1,496 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-/*
- *	Memory setup
- */
-.globl lowlevel_init
-lowlevel_init:
-
-	mov      r10, lr
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 3rd blink */
-	bl	blink
-#endif
-
-	/* Set up GPIO pins first ----------------------------------------- */
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 4th debug blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 5th blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
-	ldr     r2,     =0xFFF
-	and     r3,     r3,  r2
-	ldr	r4,	=0x03ca4000
-	orr     r4,     r4,  r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4                            */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	orr	r4,	r4,	#(MDREFR_SLFRSH)
-	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4,	#(MDREFR_SLFRSH)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 �sec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	    str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-	/* We are finished with Intel's memory controller initialisation    */
-#if 0
-	/* FIXME turn on serial ports */
-	/* look into moving this to board_init() */
-	ldr	r2, =(PXA_CS5_PHYS + 0x03C0002c)
-	mov	r3, #0x13
-	str	r3, [r2]
-#endif
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 6th blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-#if 0
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#endif
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-	ldr     r1, =DRAM_SIZE
-	str     r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR /* enable no sources */
-	mov r1, #0
-	str r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
-	/* ---------------------------------------------------------------- */
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 7th blink */
-	bl	blink
-#endif
-
-endlowlevel_init:
-
-	mov     pc, r10
-
-
-#ifdef DEBUG_BLINK_ENABLE
-
-/* debug LED code */
-
-/* delay about 200ms */
-delay:
-
-	/* reset OSCR to 0 */
-	ldr	r8, =OSCR
-	mov	r9, #0
-	str	r9, [r8]
-
-	/* make sure new value has stuck */
-1:
-	ldr	r8, =OSCR
-	ldr	r9, [r8]
-	mov	r8, #0x10000
-	cmp	r9, r8
-	bgt	1b
-
-	/* now, wait for delay to expire */
-1:
-	ldr	r8, =OSCR
-	ldr	r9, [r8]
-	mov	r8, #0xd4000
-	cmp	r8, r9
-	bgt	1b
-
-	mov	pc, lr
-
-/* blink code -- trashes r7, r8, r9 */
-
-.globl blink
-blink:
-
-	mov	r7, lr
-
-	/* set GPIO10 as outout */
-	ldr	r8,  =GPDR0
-	ldr	r9,  [r8]
-	orr	r9,  r9, #(1<<10)
-	str	r9,  [r8]
-
-	/* turn LED off */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPCR0
-	str	r9, [r8]
-	bl	delay
-
-	/* turn LED on */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPSR0
-	str	r9, [r8]
-	bl	delay
-
-	/* turn LED off */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPCR0
-	str	r9, [r8]
-
-	mov	pc, r7
-
-#endif
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index 4ab8bd494f6eb8dbf65de8b7311ce0aa20183b4a..804d09c22bd72ad18268763b5c6ba21021323c68 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -43,8 +43,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
@@ -82,22 +83,20 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
-
 #ifdef DEBUG_BLINKC_ENABLE
 
 void delay_c(void)
diff --git a/board/renesas/sh7785lcr/config.mk b/board/renesas/sh7785lcr/config.mk
index 1a9038c75331c4c5054f13fadcb5664173560a12..6853d2b28beaf29a65f89fb73d6da467f70e3615 100644
--- a/board/renesas/sh7785lcr/config.mk
+++ b/board/renesas/sh7785lcr/config.mk
@@ -24,6 +24,8 @@
 #
 sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
-ifndef CONFIG_SYS_TEXT_BASE
+ifdef CONFIG_SH_32BIT
+CONFIG_SYS_TEXT_BASE = 0x8FF80000
+else
 CONFIG_SYS_TEXT_BASE = 0x0ff80000
 endif
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 43367291132f4b86c96e9160fa13e489b7e5d32a..0b09ebaf898b90db4f6c302d155626ef96efe689 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -87,6 +87,6 @@ int board_mmc_init(bd_t *bis)
 		gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
 	}
 
-	return s5p_mmc_init(0);
+	return s5p_mmc_init(0, 4);
 }
 #endif
diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c
index 1294d3f1b1c664d2c2cac1866367ce9db598b0b0..895bd7789ab8fc5d0a50dd742dc4ce25ed4c0162 100644
--- a/board/samsung/smdk2400/smdk2400.c
+++ b/board/samsung/smdk2400/smdk2400.c
@@ -52,30 +52,30 @@ int board_init (void)
 
 	/* memory and cpu-speed are setup before relocation */
 	/* change the clock to be 50 MHz 1:1:1 */
-	clk_power->MPLLCON = 0x5c042;
-	clk_power->CLKDIVN = 0;
+	clk_power->mpllcon = 0x5c042;
+	clk_power->clkdivn = 0;
 	/* set up the I/O ports */
-	gpio->PACON = 0x3ffff;
-	gpio->PBCON = 0xaaaaaaaa;
-	gpio->PBUP = 0xffff;
-	gpio->PECON = 0x0;
-	gpio->PEUP = 0x0;
+	gpio->pacon = 0x3ffff;
+	gpio->pbcon = 0xaaaaaaaa;
+	gpio->pbup = 0xffff;
+	gpio->pecon = 0x0;
+	gpio->peup = 0x0;
 #ifdef CONFIG_HWFLOW
 	/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
 	/*   10,   10,   00,   00,    10,   00,    10 */
-	gpio->PFCON=0xa22;
+	gpio->pfcon = 0xa22;
 	/* Disable pull-up on Rx, Tx, CTS and RTS pins */
-	gpio->PFUP=0x35;
+	gpio->pfup = 0x35;
 #else
 	/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
 	/*   00,   00,   00,   00,    10,   00,    10 */
-	gpio->PFCON = 0x22;
+	gpio->pfcon = 0x22;
 	/* Disable pull-up on Rx and Tx pins */
-	gpio->PFUP = 0x5;
+	gpio->pfup = 0x5;
 #endif	/* CONFIG_HWFLOW */
-	gpio->PGCON = 0x0;
-	gpio->PGUP = 0x0;
-	gpio->OPENCR = 0x0;
+	gpio->pgcon = 0x0;
+	gpio->pgup = 0x0;
+	gpio->opencr = 0x0;
 
 	/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
 	gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
index 5d1a8bb0cf6bfd1b829f0b53582fb61488fd1734..76a24bb939878e00809660a2c13a6c3d22cfd7da 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -73,36 +73,36 @@ int board_init (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->LOCKTIME = 0xFFFFFF;
+	clk_power->locktime = 0xFFFFFF;
 
 	/* configure MPLL */
-	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (4000);
 
 	/* configure UPLL */
-	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (8000);
 
 	/* set up the I/O ports */
-	gpio->GPACON = 0x007FFFFF;
-	gpio->GPBCON = 0x00044555;
-	gpio->GPBUP = 0x000007FF;
-	gpio->GPCCON = 0xAAAAAAAA;
-	gpio->GPCUP = 0x0000FFFF;
-	gpio->GPDCON = 0xAAAAAAAA;
-	gpio->GPDUP = 0x0000FFFF;
-	gpio->GPECON = 0xAAAAAAAA;
-	gpio->GPEUP = 0x0000FFFF;
-	gpio->GPFCON = 0x000055AA;
-	gpio->GPFUP = 0x000000FF;
-	gpio->GPGCON = 0xFF95FFBA;
-	gpio->GPGUP = 0x0000FFFF;
-	gpio->GPHCON = 0x002AFAAA;
-	gpio->GPHUP = 0x000007FF;
+	gpio->gpacon = 0x007FFFFF;
+	gpio->gpbcon = 0x00044555;
+	gpio->gpbup = 0x000007FF;
+	gpio->gpccon = 0xAAAAAAAA;
+	gpio->gpcup = 0x0000FFFF;
+	gpio->gpdcon = 0xAAAAAAAA;
+	gpio->gpdup = 0x0000FFFF;
+	gpio->gpecon = 0xAAAAAAAA;
+	gpio->gpeup = 0x0000FFFF;
+	gpio->gpfcon = 0x000055AA;
+	gpio->gpfup = 0x000000FF;
+	gpio->gpgcon = 0xFF95FFBA;
+	gpio->gpgup = 0x0000FFFF;
+	gpio->gphcon = 0x002AFAAA;
+	gpio->gphup = 0x000007FF;
 
 	/* arch number of SMDK2410-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S
index 531dcdf4ae22e5dd00c2c6f7718df775394927ea..61b4b55534226357e1f74120baf3f484c2feeec0 100644
--- a/board/sandpoint/early_init.S
+++ b/board/sandpoint/early_init.S
@@ -25,6 +25,7 @@
 #define __ASSEMBLY__	1
 #endif
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <asm/processor.h>
 #include <mpc824x.h>
diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c
index 3a936778ec4e65f56d500552848ab7e1f8a34cc3..c82382dc828c6cfb050d9ab5084e5d201eacd695 100644
--- a/board/sbc2410x/sbc2410x.c
+++ b/board/sbc2410x/sbc2410x.c
@@ -80,40 +80,40 @@ int board_init (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->LOCKTIME = 0xFFFFFF;
+	clk_power->locktime = 0xFFFFFF;
 
 	/* configure MPLL */
-	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (4000);
 
 	/* configure UPLL */
-	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
 	/* some delay between MPLL and UPLL */
 	delay (8000);
 
 	/* set up the I/O ports */
-	gpio->GPACON = 0x007FFFFF;
-	gpio->GPBCON = 0x00044556;
-	gpio->GPBUP = 0x000007FF;
-	gpio->GPCCON = 0xAAAAAAAA;
-	gpio->GPCUP = 0x0000FFFF;
-	gpio->GPDCON = 0xAAAAAAAA;
-	gpio->GPDUP = 0x0000FFFF;
-	gpio->GPECON = 0xAAAAAAAA;
-	gpio->GPEUP = 0x0000FFFF;
-	gpio->GPFCON = 0x000055AA;
-	gpio->GPFUP = 0x000000FF;
-	gpio->GPGCON = 0xFF95FF3A;
-	gpio->GPGUP = 0x0000FFFF;
-	gpio->GPHCON = 0x0016FAAA;
-	gpio->GPHUP = 0x000007FF;
-
-	gpio->EXTINT0=0x22222222;
-	gpio->EXTINT1=0x22222222;
-	gpio->EXTINT2=0x22222222;
+	gpio->gpacon = 0x007FFFFF;
+	gpio->gpbcon = 0x00044556;
+	gpio->gpbup = 0x000007FF;
+	gpio->gpccon = 0xAAAAAAAA;
+	gpio->gpcup = 0x0000FFFF;
+	gpio->gpdcon = 0xAAAAAAAA;
+	gpio->gpdup = 0x0000FFFF;
+	gpio->gpecon = 0xAAAAAAAA;
+	gpio->gpeup = 0x0000FFFF;
+	gpio->gpfcon = 0x000055AA;
+	gpio->gpfup = 0x000000FF;
+	gpio->gpgcon = 0xFF95FF3A;
+	gpio->gpgup = 0x0000FFFF;
+	gpio->gphcon = 0x0016FAAA;
+	gpio->gphup = 0x000007FF;
+
+	gpio->extint0 = 0x22222222;
+	gpio->extint1 = 0x22222222;
+	gpio->extint2 = 0x22222222;
 
 	/* arch number of SMDK2410-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
index ecd35ff7b6f08efcc412d2dd579d6d65aa647290..a24d6f3a0fb2e38223d9f58ce86e2c81fd232f0c 100644
--- a/board/t3corp/init.S
+++ b/board/t3corp/init.S
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 #include <asm/mmu.h>
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index ca4415c0b9234716c8e1d5238cc4bfee2e48fd7c..dec3c618279b43345c3a044274125c285f12181d 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -637,28 +637,28 @@ static int adc_read (unsigned int channel)
 
 	adc_init ();
 
-	padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
-	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
-	padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+	padc->adccon &= ~ADC_STDBM; /* select normal mode */
+	padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+	padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
 
 	while (j--) {
-		if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+		if ((padc->adccon & ADC_ENABLE_START) == 0)
 			break;
 		udelay (1);
 	}
 
 	if (j == 0) {
 		printf("%s: ADC timeout\n", __FUNCTION__);
-		padc->ADCCON |= ADC_STDBM; /* select standby mode */
+		padc->adccon |= ADC_STDBM; /* select standby mode */
 		return -1;
 	}
 
-	result = padc->ADCDAT & 0x3FF;
+	result = padc->adcdat & 0x3FF;
 
-	padc->ADCCON |= ADC_STDBM; /* select standby mode */
+	padc->adccon |= ADC_STDBM; /* select standby mode */
 
 	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-	       (padc->ADCCON >> 3) & 0x7, result);
+	       (padc->adccon >> 3) & 0x7, result);
 
 	/*
 	 * Wait for ADC to be ready for next conversion. This delay value was
@@ -676,8 +676,8 @@ static void adc_init (void)
 
 	padc = s3c2400_get_base_adc();
 
-	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
-	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+	padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+	padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
 
 	/*
 	 * Wait some time to avoid problem with very first call of
@@ -699,10 +699,10 @@ static void led_set (unsigned int state)
 
 	switch (state) {
 	case 0: /* turn LED off */
-		gpio->PADAT |= (1 << 12);
+		gpio->padat |= (1 << 12);
 		break;
 	case 1: /* turn LED on */
-		gpio->PADAT &= ~(1 << 12);
+		gpio->padat &= ~(1 << 12);
 		break;
 	default:
 		break;
@@ -729,8 +729,8 @@ static void led_init (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure GPA12 as output and set to High -> LED off */
-	gpio->PACON &= ~(1 << 12);
-	gpio->PADAT |= (1 << 12);
+	gpio->pacon &= ~(1 << 12);
+	gpio->padat |= (1 << 12);
 }
 
 
diff --git a/board/trab/rs485.c b/board/trab/rs485.c
index 6a3a4cda9ce5e56895f30465799a3e5a9a6647ed..30336f262cf8ee6b0ba85c6a285ecdb77ce3d280 100644
--- a/board/trab/rs485.c
+++ b/board/trab/rs485.c
@@ -51,16 +51,16 @@ static void rs485_setbrg (void)
 	reg = (33000000 / (16 * 38400)) - 1;
 
 	/* FIFO enable, Tx/Rx FIFO clear */
-	uart->UFCON = 0x07;
-	uart->UMCON = 0x0;
+	uart->ufcon = 0x07;
+	uart->umcon = 0x0;
 	/* Normal,No parity,1 stop,8 bit */
-	uart->ULCON = 0x3;
+	uart->ulcon = 0x3;
 	/*
 	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal,interrupt or polling
 	 */
-	uart->UCON = 0x245;
-	uart->UBRDIV = reg;
+	uart->ucon = 0x245;
+	uart->ubrdiv = reg;
 
 	for (i = 0; i < 100; i++);
 }
@@ -69,16 +69,16 @@ static void rs485_cfgio (void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PFCON &= ~(0x3 << 2);
-	gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */
+	gpio->pfcon &= ~(0x3 << 2);
+	gpio->pfcon |=  (0x2 << 2); /* configure GPF1 as RXD1 */
 
-	gpio->PFCON &= ~(0x3 << 6);
-	gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */
+	gpio->pfcon &= ~(0x3 << 6);
+	gpio->pfcon |=  (0x2 << 6); /* configure GPF3 as TXD1 */
 
-	gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
-	gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+	gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
+	gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
 
-	gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+	gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
 }
 
 /*
@@ -104,9 +104,10 @@ int rs485_getc (void)
 	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
 	/* wait for character to arrive */
-	while (!(uart->UTRSTAT & 0x1));
+	while (!(uart->utrstat & 0x1))
+		;
 
-	return uart->URXH & 0xff;
+	return uart->urxh & 0xff;
 }
 
 /*
@@ -117,9 +118,10 @@ void rs485_putc (const char c)
 	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
 	/* wait for room in the tx FIFO */
-	while (!(uart->UTRSTAT & 0x2));
+	while (!(uart->utrstat & 0x2))
+		;
 
-	uart->UTXH = c;
+	uart->utxh = c;
 
 	/* If \n, also do \r */
 	if (c == '\n')
@@ -133,7 +135,7 @@ int rs485_tstc (void)
 {
 	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
 
-	return uart->UTRSTAT & 0x1;
+	return uart->utrstat & 0x1;
 }
 
 void rs485_puts (const char *s)
@@ -172,9 +174,9 @@ static void set_rs485de(unsigned char rs485de_state)
 
 	/* This is on PORT A bit 11 */
 	if(rs485de_state)
-		gpio->PADAT |= (1 << 11);
+		gpio->padat |= (1 << 11);
 	else
-		gpio->PADAT &= ~(1 << 11);
+		gpio->padat &= ~(1 << 11);
 }
 
 
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 828facd763e1db4b7aae667b333194c25a431300..0f74e8fa1b708e69723e6331b0cc7e065fba3b89 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -77,36 +77,36 @@ int board_init ()
 #ifdef CONFIG_TRAB_50MHZ
 	/* change the clock to be 50 MHz 1:1:1 */
 	/* MDIV:0x5c PDIV:4 SDIV:2 */
-	clk_power->MPLLCON = 0x5c042;
-	clk_power->CLKDIVN = 0;
+	clk_power->mpllcon = 0x5c042;
+	clk_power->clkdivn = 0;
 #else
 	/* change the clock to be 133 MHz 1:2:4 */
 	/* MDIV:0x7d PDIV:4 SDIV:1 */
-	clk_power->MPLLCON = 0x7d041;
-	clk_power->CLKDIVN = 3;
+	clk_power->mpllcon = 0x7d041;
+	clk_power->clkdivn = 3;
 #endif
 
 	/* set up the I/O ports */
-	gpio->PACON = 0x3ffff;
-	gpio->PBCON = 0xaaaaaaaa;
-	gpio->PBUP  = 0xffff;
+	gpio->pacon = 0x3ffff;
+	gpio->pbcon = 0xaaaaaaaa;
+	gpio->pbup  = 0xffff;
 	/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]	*/
 	/*  00,    10,      10,      10,      10,      10,      10	*/
-	gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+	gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
 #ifdef CONFIG_HWFLOW
 	/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
-	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
 #else
 	/* do not pull up RXD0, RXD1, TXD0, TXD1 */
-	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
 #endif
-	gpio->PGCON = 0x0;
-	gpio->PGUP  = 0x0;
-	gpio->OPENCR= 0x0;
+	gpio->pgcon = 0x0;
+	gpio->pgup  = 0x0;
+	gpio->opencr = 0x0;
 
 	/* suppress flicker of the VFDs */
-	gpio->MISCCR = 0x40;
-	gpio->PFCON |= (2<<12);
+	gpio->misccr = 0x40;
+	gpio->pfcon |= (2<<12);
 
 	gd->bd->bi_arch_number = MACH_TYPE_TRAB;
 
@@ -114,8 +114,8 @@ int board_init ()
 	gd->bd->bi_boot_params = 0x0c000100;
 
 	/* Make sure both buzzers are turned off */
-	gpio->PDCON |= 0x5400;
-	gpio->PDDAT &= ~0xE0;
+	gpio->pdcon |= 0x5400;
+	gpio->pddat &= ~0xE0;
 
 #ifdef CONFIG_VFD
 	vfd_init_clocks();
@@ -132,7 +132,7 @@ int board_init ()
 
 #ifdef CONFIG_DRIVER_S3C24X0_I2C
 	/* Configure I/O ports PG5 und PG6 for I2C */
-	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+	gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00;
 #endif /* CONFIG_DRIVER_S3C24X0_I2C */
 
 	return 0;
@@ -341,14 +341,14 @@ static inline void SET_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT &= 0x5FF;
+	gpio->pddat &= 0x5FF;
 }
 
 static inline void CLR_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT |= 0x200;
+	gpio->pddat |= 0x200;
 }
 
 static void spi_init(void)
@@ -358,20 +358,20 @@ static void spi_init(void)
 	int i;
 
 	/* Configure I/O ports. */
-	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
-	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
-	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
-	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
 
 	CLR_CS_TOUCH();
 
-	spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
-	spi->ch[0].SPPIN = 0x01;  /* SPI-MOSI holds Level after last bit */
-	spi->ch[0].SPCON = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+	spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */
+	spi->ch[0].sppin = 0x01;  /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */
 
 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++) {
-		spi->ch[0].SPTDAT = 0xFF;
+		spi->ch[0].sptdat = 0xFF;
 	}
 	wait_transmit_done();
 }
@@ -380,7 +380,8 @@ static void wait_transmit_done(void)
 {
 	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
 
-	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+		;
 }
 
 static void tsc2000_write(unsigned int page, unsigned int reg,
@@ -394,13 +395,13 @@ static void tsc2000_write(unsigned int page, unsigned int reg,
 	command |= (page << 11);
 	command |= (reg << 5);
 
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
 	wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi->ch[0].sptdat = (command & 0x00FF);
 	wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
 	wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0x00FF);
+	spi->ch[0].sptdat = (data & 0x00FF);
 	wait_transmit_done();
 
 	CLR_CS_TOUCH();
diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c
index 268162e53ae1c9402e0c6ccdb5ae2e724cdc5776..fe3dab351f9d364a212ea170a95725f59f6b67d4 100644
--- a/board/trab/trab_fkt.c
+++ b/board/trab/trab_fkt.c
@@ -411,28 +411,28 @@ static int adc_read (unsigned int channel)
 	padc = s3c2400_get_base_adc();
 	channel &= 0x7;
 
-	padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
-	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
-	padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+	padc->adccon &= ~ADC_STDBM; /* select normal mode */
+	padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
+	padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
 
 	while (j--) {
-		if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+		if ((padc->adccon & ADC_ENABLE_START) == 0)
 			break;
 		udelay (1);
 	}
 
 	if (j == 0) {
 		printf("%s: ADC timeout\n", __FUNCTION__);
-		padc->ADCCON |= ADC_STDBM; /* select standby mode */
+		padc->adccon |= ADC_STDBM; /* select standby mode */
 		return -1;
 	}
 
-	result = padc->ADCDAT & 0x3FF;
+	result = padc->adcdat & 0x3FF;
 
-	padc->ADCCON |= ADC_STDBM; /* select standby mode */
+	padc->adccon |= ADC_STDBM; /* select standby mode */
 
 	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-	       (padc->ADCCON >> 3) & 0x7, result);
+	       (padc->adccon >> 3) & 0x7, result);
 
 	/*
 	 * Wait for ADC to be ready for next conversion. This delay value was
@@ -450,8 +450,8 @@ static void adc_init (void)
 
 	padc = s3c2400_get_base_adc();
 
-	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
-	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+	padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
+	padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
 
 	/*
 	 * Wait some time to avoid problem with very first call of
@@ -493,10 +493,10 @@ int do_power_switch (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure GPE7 as input */
-	gpio->PECON &= ~(0x3 << (2 * 7));
+	gpio->pecon &= ~(0x3 << (2 * 7));
 
 	/* signal GPE7 from power switch is low active: 0=on , 1=off */
-	result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1;
+	result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1;
 
 	print_identifier ();
 	printf("%d\n", result);
@@ -561,17 +561,17 @@ int do_vfd_id (void)
 
 	/* try to red vfd board id from the value defined by pull-ups */
 
-	pcup_old = gpio->PCUP;
-	pccon_old = gpio->PCCON;
+	pcup_old = gpio->pcup;
+	pccon_old = gpio->pccon;
 
-	gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate  GPC0...GPC3 pull-ups */
-	gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as
+	gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 pull-ups */
+	gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as
 						   * inputs */
 	udelay (10);            /* allow signals to settle */
-	vfd_board_id = (~gpio->PCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+	vfd_board_id = (~gpio->pcdat) & 0x000F;	/* read GPC0...GPC3 port pins */
 
-	gpio->PCCON = pccon_old;
-	gpio->PCUP = pcup_old;
+	gpio->pccon = pccon_old;
+	gpio->pcup = pcup_old;
 
 	/* print vfd_board_id to console */
 	print_identifier ();
@@ -593,40 +593,40 @@ int do_buzzer (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* set prescaler for timer 2, 3 and 4 */
-	timers->TCFG0 &= ~0xFF00;
-	timers->TCFG0 |=  0x0F00;
+	timers->tcfg0 &= ~0xFF00;
+	timers->tcfg0 |=  0x0F00;
 
 	/* set divider for timer 2 */
-	timers->TCFG1 &= ~0xF00;
-	timers->TCFG1 |=  0x300;
+	timers->tcfg1 &= ~0xF00;
+	timers->tcfg1 |=  0x300;
 
 	/* set frequency */
 	counter = (PCLK / BUZZER_FREQ) >> 9;
-	timers->ch[2].TCNTB = counter;
-	timers->ch[2].TCMPB = counter / 2;
+	timers->ch[2].tcntb = counter;
+	timers->ch[2].tcmpb = counter / 2;
 
 	if (strcmp (argv[2], "on") == 0) {
 		debug ("%s: frequency: %d\n", __FUNCTION__,
 		       BUZZER_FREQ);
 
 		/* configure pin GPD7 as TOUT2 */
-		gpio->PDCON &= ~0xC000;
-		gpio->PDCON |= 0x8000;
+		gpio->pdcon &= ~0xC000;
+		gpio->pdcon |= 0x8000;
 
 		/* start */
-		timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) &
+		timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) &
 				~INVERT2;
-		timers->TCON = (timers->TCON | START2) & ~UPDATE2;
+		timers->tcon = (timers->tcon | START2) & ~UPDATE2;
 		return (0);
 	}
 	else if (strcmp (argv[2], "off") == 0) {
 		/* stop */
-		timers->TCON &= ~(START2 | RELOAD2);
+		timers->tcon &= ~(START2 | RELOAD2);
 
 		/* configure GPD7 as output and set to low */
-		gpio->PDCON &= ~0xC000;
-		gpio->PDCON |= 0x4000;
-		gpio->PDDAT &= ~0x80;
+		gpio->pdcon &= ~0xC000;
+		gpio->pdcon |= 0x4000;
+		gpio->pddat &= ~0x80;
 		return (0);
 	}
 
@@ -640,12 +640,12 @@ int do_led (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure PC14 and PC15 as output */
-	gpio->PCCON &= ~(0xF << 28);
-	gpio->PCCON |= (0x5 << 28);
+	gpio->pccon &= ~(0xF << 28);
+	gpio->pccon |= (0x5 << 28);
 
 	/* configure PD0 and PD4 as output */
-	gpio->PDCON &= ~((0x3 << 8) | 0x3);
-	gpio->PDCON |= ((0x1 << 8) | 0x1);
+	gpio->pdcon &= ~((0x3 << 8) | 0x3);
+	gpio->pdcon |= ((0x1 << 8) | 0x1);
 
 	switch (simple_strtoul(argv[2], NULL, 10)) {
 
@@ -655,30 +655,30 @@ int do_led (char * const *argv)
 
 	case 2:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PCDAT |= (1 << 14);
+			gpio->pcdat |= (1 << 14);
 		else
-			gpio->PCDAT &= ~(1 << 14);
+			gpio->pcdat &= ~(1 << 14);
 		return 0;
 
 	case 3:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PCDAT |= (1 << 15);
+			gpio->pcdat |= (1 << 15);
 		else
-			gpio->PCDAT &= ~(1 << 15);
+			gpio->pcdat &= ~(1 << 15);
 		return 0;
 
 	case 4:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PDDAT |= (1 << 0);
+			gpio->pddat |= (1 << 0);
 		else
-			gpio->PDDAT &= ~(1 << 0);
+			gpio->pddat &= ~(1 << 0);
 		return 0;
 
 	case 5:
 		if (strcmp (argv[3], "on") == 0)
-			gpio->PDDAT |= (1 << 4);
+			gpio->pddat |= (1 << 4);
 		else
-			gpio->PDDAT &= ~(1 << 4);
+			gpio->pddat &= ~(1 << 4);
 		return 0;
 
 	default:
@@ -695,22 +695,22 @@ int do_full_bridge (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* configure PD5 and PD6 as output */
-	gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
-	gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2));
+	gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2));
+	gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2));
 
 	if (strcmp (argv[2], "+") == 0) {
-	      gpio->PDDAT |= (1 << 5);
-	      gpio->PDDAT |= (1 << 6);
+		gpio->pddat |= (1 << 5);
+	      gpio->pddat |= (1 << 6);
 	      return 0;
 	}
 	else if (strcmp (argv[2], "-") == 0) {
-		gpio->PDDAT &= ~(1 << 5);
-		gpio->PDDAT |= (1 << 6);
+		gpio->pddat &= ~(1 << 5);
+		gpio->pddat |= (1 << 6);
 		return 0;
 	}
 	else if (strcmp (argv[2], "off") == 0) {
-		gpio->PDDAT &= ~(1 << 5);
-		gpio->PDDAT &= ~(1 << 6);
+		gpio->pddat &= ~(1 << 5);
+		gpio->pddat &= ~(1 << 6);
 		return 0;
 	}
 	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -804,15 +804,15 @@ int do_motor (char * const *argv)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* Configure I/O port */
-	gpio->PGCON &= ~(0x3 << 0);
-	gpio->PGCON |= (0x1 << 0);
+	gpio->pgcon &= ~(0x3 << 0);
+	gpio->pgcon |= (0x1 << 0);
 
 	if (strcmp (argv[2], "on") == 0) {
-		gpio->PGDAT &= ~(1 << 0);
+		gpio->pgdat &= ~(1 << 0);
 		return 0;
 	}
 	if (strcmp (argv[2], "off") == 0) {
-		gpio->PGDAT |= (1 << 0);
+		gpio->pgdat |= (1 << 0);
 		return 0;
 	}
 	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
@@ -832,36 +832,36 @@ int do_pwm (char * const *argv)
 
 	if (strcmp (argv[2], "on") == 0) {
 		/* configure pin GPD8 as TOUT3 */
-		gpio->PDCON &= ~(0x3 << 8*2);
-		gpio->PDCON |= (0x2 << 8*2);
+		gpio->pdcon &= ~(0x3 << 8*2);
+		gpio->pdcon |= (0x2 << 8*2);
 
 		/* set prescaler for timer 2, 3 and 4 */
-		timers->TCFG0 &= ~0xFF00;
-		timers->TCFG0 |= 0x0F00;
+		timers->tcfg0 &= ~0xFF00;
+		timers->tcfg0 |= 0x0F00;
 
 		/* set divider for timer 3 */
-		timers->TCFG1 &= ~(0xf << 12);
-		timers->TCFG1 |= (0x3 << 12);
+		timers->tcfg1 &= ~(0xf << 12);
+		timers->tcfg1 |= (0x3 << 12);
 
 		/* set frequency */
 		counter = (PCLK / PWM_FREQ) >> 9;
-		timers->ch[3].TCNTB = counter;
-		timers->ch[3].TCMPB = counter / 2;
+		timers->ch[3].tcntb = counter;
+		timers->ch[3].tcmpb = counter / 2;
 
 		/* start timer */
-		timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
-		timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+		timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->tcon = (timers->tcon | START3) & ~UPDATE3;
 		return 0;
 	}
 	if (strcmp (argv[2], "off") == 0) {
 
 		/* stop timer */
-		timers->TCON &= ~(START2 | RELOAD2);
+		timers->tcon &= ~(START2 | RELOAD2);
 
 		/* configure pin GPD8 as output and set to 0 */
-		gpio->PDCON &= ~(0x3 << 8*2);
-		gpio->PDCON |= (0x1 << 8*2);
-		gpio->PDDAT &= ~(1 << 8);
+		gpio->pdcon &= ~(0x3 << 8*2);
+		gpio->pdcon |= (0x1 << 8*2);
+		gpio->pddat &= ~(1 << 8);
 		return 0;
 	}
 	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
index 5890624f0f02c272fd049bd6258cd8e72fa6ef0d..426ed9c520bd60462898c8f2e74c85d782a58b71 100644
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -50,21 +50,21 @@ void tsc2000_spi_init(void)
 	int i;
 
 	/* Configure I/O ports. */
-	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
-	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
-	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
-	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
+	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
+	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
+	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
 
 	CLR_CS_TOUCH();
 
-	spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
-	spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
-	spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+	spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */
+	spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
 				    CPHA=1 */
 
 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++) {
-		spi->ch[0].SPTDAT = 0xFF;
+		spi->ch[0].sptdat = 0xFF;
 	}
 	spi_wait_transmit_done();
 }
@@ -74,7 +74,8 @@ void spi_wait_transmit_done(void)
 {
 	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
 
-	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
+		;
 }
 
 
@@ -85,13 +86,13 @@ void tsc2000_write(unsigned short reg, unsigned short data)
 
 	SET_CS_TOUCH();
 	command = reg;
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi->ch[0].sptdat = (command & 0x00FF);
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (data & 0x00FF);
+	spi->ch[0].sptdat = (data & 0x00FF);
 	spi_wait_transmit_done();
 
 	CLR_CS_TOUCH();
@@ -106,19 +107,19 @@ unsigned short tsc2000_read (unsigned short reg)
 	SET_CS_TOUCH();
 	command = 0x8000 | reg;
 
-	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
-	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi->ch[0].sptdat = (command & 0x00FF);
 	spi_wait_transmit_done();
 
-	spi->ch[0].SPTDAT = 0xFF;
+	spi->ch[0].sptdat = 0xFF;
 	spi_wait_transmit_done();
-	data = spi->ch[0].SPRDAT;
-	spi->ch[0].SPTDAT = 0xFF;
+	data = spi->ch[0].sprdat;
+	spi->ch[0].sptdat = 0xFF;
 	spi_wait_transmit_done();
 
 	CLR_CS_TOUCH();
-	return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+	return (spi->ch[0].sprdat & 0x0FF) | (data << 8);
 }
 
 
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
index 0b6253f656658b401e54e3ec7a86ce143a8347e6..f3cecb928e2e6d88488aa20a10a8f646fa77bcd6 100644
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -29,45 +29,49 @@
 #define _TSC2000_H_
 
 /* temperature channel multiplexer definitions */
-#define CON_MUX0		(gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
-#define CLR_MUX0		(gpio->PCDAT &= 0x0FFEF)
-#define SET_MUX0		(gpio->PCDAT |= 0x00010)
-
-#define CON_MUX1		(gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
-#define CLR_MUX1		(gpio->PCDAT &= 0x0FFDF)
-#define SET_MUX1		(gpio->PCDAT |= 0x00020)
-
-#define CON_MUX1_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
-#define CLR_MUX1_ENABLE		(gpio->PCDAT |= 0x00040)
-#define SET_MUX1_ENABLE		(gpio->PCDAT &= 0x0FFBF)
-
-#define CON_MUX2_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
-#define CLR_MUX2_ENABLE		(gpio->PCDAT |= 0x00080)
-#define SET_MUX2_ENABLE		(gpio->PCDAT &= 0x0FF7F)
-
-#define CON_MUX3_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
-#define CLR_MUX3_ENABLE		(gpio->PCDAT |= 0x00100)
-#define SET_MUX3_ENABLE		(gpio->PCDAT &= 0x0FEFF)
-
-#define CON_MUX4_ENABLE		(gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
-#define CLR_MUX4_ENABLE		(gpio->PCDAT |= 0x00200)
-#define SET_MUX4_ENABLE		(gpio->PCDAT &= 0x0FDFF)
-
-#define CON_SEL_TEMP_V_0	(gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
-#define CLR_SEL_TEMP_V_0	(gpio->PCDAT &= 0x0FBFF)
-#define SET_SEL_TEMP_V_0	(gpio->PCDAT |= 0x00400)
-
-#define CON_SEL_TEMP_V_1	(gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
-#define CLR_SEL_TEMP_V_1	(gpio->PCDAT &= 0x0F7FF)
-#define SET_SEL_TEMP_V_1	(gpio->PCDAT |= 0x00800)
-
-#define CON_SEL_TEMP_V_2	(gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
-#define CLR_SEL_TEMP_V_2	(gpio->PCDAT &= 0x0EFFF)
-#define SET_SEL_TEMP_V_2	(gpio->PCDAT |= 0x01000)
-
-#define CON_SEL_TEMP_V_3	(gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
-#define CLR_SEL_TEMP_V_3	(gpio->PCDAT &= 0x0DFFF)
-#define SET_SEL_TEMP_V_3	(gpio->PCDAT |= 0x02000)
+#define CON_MUX0	(gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0	(gpio->pcdat &= 0x0FFEF)
+#define SET_MUX0	(gpio->pcdat |= 0x00010)
+
+#define CON_MUX1	(gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1	(gpio->pcdat &= 0x0FFDF)
+#define SET_MUX1	(gpio->pcdat |= 0x00020)
+
+#define CON_MUX1_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE	(gpio->pcdat |= 0x00040)
+#define SET_MUX1_ENABLE	(gpio->pcdat &= 0x0FFBF)
+
+#define CON_MUX2_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE	(gpio->pcdat |= 0x00080)
+#define SET_MUX2_ENABLE	(gpio->pcdat &= 0x0FF7F)
+
+#define CON_MUX3_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE	(gpio->pcdat |= 0x00100)
+#define SET_MUX3_ENABLE	(gpio->pcdat &= 0x0FEFF)
+
+#define CON_MUX4_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE	(gpio->pcdat |= 0x00200)
+#define SET_MUX4_ENABLE	(gpio->pcdat &= 0x0FDFF)
+
+#define CON_SEL_TEMP_V_0	(gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \
+							0x00100000)
+#define CLR_SEL_TEMP_V_0	(gpio->pcdat &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0	(gpio->pcdat |= 0x00400)
+
+#define CON_SEL_TEMP_V_1	(gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \
+		0x00400000)
+#define CLR_SEL_TEMP_V_1	(gpio->pcdat &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1	(gpio->pcdat |= 0x00800)
+
+#define CON_SEL_TEMP_V_2	(gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \
+		0x01000000)
+#define CLR_SEL_TEMP_V_2	(gpio->pcdat &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2	(gpio->pcdat |= 0x01000)
+
+#define CON_SEL_TEMP_V_3	(gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \
+		0x04000000)
+#define CLR_SEL_TEMP_V_3	(gpio->pcdat &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3	(gpio->pcdat |= 0x02000)
 
 /* TSC2000 register definition */
 #define TSC2000_REG_X		((0 << 11) | (0 << 5))
@@ -130,7 +134,7 @@ static inline void SET_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT &= 0x5FF;
+	gpio->pddat &= 0x5FF;
 }
 
 
@@ -138,7 +142,7 @@ static inline void CLR_CS_TOUCH(void)
 {
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	gpio->PDDAT |= 0x200;
+	gpio->pddat |= 0x200;
 }
 
 #endif	/* _TSC2000_H_ */
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index b7eb8cce03ceeb71d64cdb20386d7586ced510d3..9a2b1ba1a5acf9c30e58b357abbeea40c88b587b 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -365,12 +365,12 @@ int vfd_init_clocks (void)
 	/* try to determine display type from the value
 	 * defined by pull-ups
 	 */
-	gpio->PCUP = (gpio->PCUP & 0xFFF0);	/* activate  GPC0...GPC3 pullups */
-	gpio->PCCON = (gpio->PCCON & 0xFFFFFF00);	/* configure GPC0...GPC3 as inputs */
+	gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 pullups */
+	gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */
 	/* allow signals to settle */
 	for (i=0; i<10000; i++)	/* udelay isn't working yet at this point! */
 		__asm__("NOP");
-	vfd_board_id = (~gpio->PCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+	vfd_board_id = (~gpio->pcdat) & 0x000F;	/* read GPC0...GPC3 port pins */
 
 	VFD_DISABLE;				/* activate blank for the vfd */
 
@@ -381,39 +381,39 @@ int vfd_init_clocks (void)
 		/* If new board revision, then use PWM 3 as cpld-clock */
 		/* Enable 500 Hz timer for fill level sensor to operate properly */
 		/* Configure TOUT3 as functional pin, disable pull-up */
-		gpio->PDCON &= ~0x30000;
-		gpio->PDCON |= 0x20000;
-		gpio->PDUP |= (1 << 8);
+		gpio->pdcon &= ~0x30000;
+		gpio->pdcon |= 0x20000;
+		gpio->pdup |= (1 << 8);
 
 		/* Configure the prescaler */
-		timers->TCFG0 &= ~0xff00;
-		timers->TCFG0 |= 0x0f00;
+		timers->tcfg0 &= ~0xff00;
+		timers->tcfg0 |= 0x0f00;
 
 		/* Select MUX input (divider) for timer3 (1/16) */
-		timers->TCFG1 &= ~0xf000;
-		timers->TCFG1 |= 0x3000;
+		timers->tcfg1 &= ~0xf000;
+		timers->tcfg1 |= 0x3000;
 
 		/* Enable autoreload and set the counter and compare
 		 * registers to values for the 500 Hz clock
 		 * (for a given  prescaler (15) and divider (16)):
 		 * counter = (66000000 / 500) >> 9;
 		 */
-		timers->ch[3].TCNTB = 0x101;
-		timers->ch[3].TCMPB = 0x101 / 2;
+		timers->ch[3].tcntb = 0x101;
+		timers->ch[3].tcmpb = 0x101 / 2;
 
 		/* Start timer */
-		timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
-		timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+		timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->tcon = (timers->tcon | START3) & ~UPDATE3;
 	}
 #endif
 	/* If old board revision, then use vm-signal as cpld-clock */
-	lcd->LCDCON2 = 0x00FFC000;
-	lcd->LCDCON3 = 0x0007FF00;
-	lcd->LCDCON4 = 0x00000000;
-	lcd->LCDCON5 = 0x00000400;
-	lcd->LCDCON1 = 0x00000B75;
+	lcd->lcdcon2 = 0x00FFC000;
+	lcd->lcdcon3 = 0x0007FF00;
+	lcd->lcdcon4 = 0x00000000;
+	lcd->lcdcon5 = 0x00000400;
+	lcd->lcdcon1 = 0x00000B75;
 	/* VM (GPD1) is used as clock for the CPLD */
-	gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
+	gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008;
 
 	return 0;
 }
@@ -485,40 +485,44 @@ int drv_vfd_init(void)
 	 * see manual S3C2400
 	 */
 	/* Stopp LCD-Controller */
-	lcd->LCDCON1 = 0x00000000;
+	lcd->lcdcon1 = 0x00000000;
 	/* frame buffer startadr */
-	lcd->LCDSADDR1 = gd->fb_base >> 1;
+	lcd->lcdsaddr1 = gd->fb_base >> 1;
 	/* frame buffer endadr */
-	lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
-	lcd->LCDSADDR3 = ((256/4));
-	lcd->LCDCON2 = 0x000DC000;
+	lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+	lcd->lcdsaddr3 = ((256/4));
+	lcd->lcdcon2 = 0x000DC000;
 	if(gd->vfd_type == VFD_TYPE_MN11236)
-		lcd->LCDCON2 = 37 << 14;	/* MN11236: 38 lines */
+		lcd->lcdcon2 = 37 << 14;	/* MN11236: 38 lines */
 	else
-		lcd->LCDCON2 = 55 << 14;	/* T119C:   56 lines */
-	lcd->LCDCON3 = 0x0051000A;
-	lcd->LCDCON4 = 0x00000001;
+		lcd->lcdcon2 = 55 << 14;	/* T119C:   56 lines */
+	lcd->lcdcon3 = 0x0051000A;
+	lcd->lcdcon4 = 0x00000001;
 	if (gd->vfd_type && vfd_inv_data)
-		lcd->LCDCON5 = 0x000004C0;
+		lcd->lcdcon5 = 0x000004C0;
 	else
-		lcd->LCDCON5 = 0x00000440;
+		lcd->lcdcon5 = 0x00000440;
 
 	/* Port pins as LCD output */
-	gpio->PCCON =   (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
-	gpio->PDCON =   (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
+	gpio->pccon =   (gpio->pccon & 0xFFFFFF00) | 0x000000AA;
+	gpio->pdcon =   (gpio->pdcon & 0xFFFFFF03) | 0x000000A8;
 
 	/* Synchronize VFD enable with LCD controller to avoid flicker	*/
-	lcd->LCDCON1 = 0x00000B75;			/* Start LCD-Controller	*/
-	while((lcd->LCDCON5 & 0x180000)!=0x100000);	/* Wait for end of VSYNC */
-	while((lcd->LCDCON5 & 0x060000)!=0x040000);	/* Wait for next HSYNC	*/
-	while((lcd->LCDCON5 & 0x060000)==0x040000);
-	while((lcd->LCDCON5 & 0x060000)!=0x000000);
+	lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller	*/
+	while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */
+		;
+	while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */
+		;
+	while ((lcd->lcdcon5 & 0x060000) == 0x040000)
+		;
+	while ((lcd->lcdcon5 & 0x060000) != 0x000000)
+		;
 	if(gd->vfd_type)
 		VFD_ENABLE;
 
-	debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
-	debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
-	debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
+	debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1);
+	debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2);
+	debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3);
 
 	return 0;
 }
@@ -532,8 +536,8 @@ void disable_vfd (void)
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	VFD_DISABLE;
-	gpio->PDCON &= ~0xC;
-	gpio->PDUP  &= ~0x2;
+	gpio->pdcon &= ~0xC;
+	gpio->pdup  &= ~0x2;
 }
 
 /************************************************************************/
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
index 44c0d495ef2702445edcb0945ba5c1397f622d62..060ac890f7c4ab92ca0d56d7bc4ec234d7cd49e7 100644
--- a/board/trizepsiv/Makefile
+++ b/board/trizepsiv/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= conxs.o eeprom.o
-SOBJS	:= lowlevel_init.o pxavoltage.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk
deleted file mode 100644
index f04eb74efdcbec346afb93790bafbe697d3cb9e5..0000000000000000000000000000000000000000
--- a/board/trizepsiv/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE =0xa1f00000
-# 0xa1700000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 0c67367a5fc93de12a0fa816a9d41c9429116557..99f665b47273092d2da96a41fcc224cf6c5d1001 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -104,8 +104,9 @@ void usb_board_stop(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of ConXS Board */
 	gd->bd->bi_arch_number = 776;
@@ -138,18 +139,18 @@ struct serial_device *default_serial_console (void)
 	return &serial_ffuart_device;
 }
 
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_DRIVER_DM9000
diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S
deleted file mode 100644
index 128d55407610c178cf22f4b161885e471d1472ae..0000000000000000000000000000000000000000
--- a/board/trizepsiv/lowlevel_init.S
+++ /dev/null
@@ -1,503 +0,0 @@
-/*
- * This was originally from the Lubbock u-boot port.
- *
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc	p15,0,\reg,c2,c0,0
-   mov	\reg,\reg
-   sub	pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR3
-	ldr		r1,	=CONFIG_SYS_GPSR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR3
-	ldr		r1,	=CONFIG_SYS_GPCR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER0
-	ldr		r1,	=CONFIG_SYS_GRER0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER1
-	ldr		r1,	=CONFIG_SYS_GRER1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER2
-	ldr		r1,	=CONFIG_SYS_GRER2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER3
-	ldr		r1,	=CONFIG_SYS_GRER3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER0
-	ldr		r1,	=CONFIG_SYS_GFER0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER1
-	ldr		r1,	=CONFIG_SYS_GFER1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER2
-	ldr		r1,	=CONFIG_SYS_GFER2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER3
-	ldr		r1,	=CONFIG_SYS_GFER3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR3
-	ldr		r1,	=CONFIG_SYS_GPDR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR3_L
-	ldr		r1,	=CONFIG_SYS_GAFR3_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR3_U
-	ldr		r1,	=CONFIG_SYS_GAFR3_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface					    */
-	/*								    */
-	/* The sequence below is based on the recommended init steps	    */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.							    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
-	/*	   clocks to settle. Only necessary after hard reset...	    */
-	/*	   FIXME: can be optimized later			    */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty	    */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller	    */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type			    */
-
-	/* MSC0: nCS(0,1)						    */
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
-						/* that data latches	    */
-	/* MSC1: nCS(2,3)						    */
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)						    */
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface				    */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register				    */
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing				    */
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing				    */
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
-	/* ---------------------------------------------------------------- */
-	ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	str	r2,  [r1, #FLYCNFG_OFFSET]
-	str	r2,	[r1, #FLYCNFG_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
-	/* this to power on defaults + DRI field.			    */
-
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-	ldr	r2,	=0xFFF
-	bic	r4,	r4, r2
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	and	r3,	r3,  r2
-
-	orr	r4,	r4, r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
-
-	orr	r4,  r4, #MDREFR_K0RUN
-	orr	r4,  r4, #MDREFR_K0DB4
-	orr	r4,  r4, #MDREFR_K0FREE
-	orr	r4,  r4, #MDREFR_K0DB2
-	orr	r4,  r4, #MDREFR_K1DB2
-	bic	r4,  r4, #MDREFR_K1FREE
-	bic	r4,  r4, #MDREFR_K2FREE
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4			    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits		    */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.						    */
-
-	ldr	r2,  =CONFIG_SYS_SXCNFG_VAL
-	str	r2,  [r1, #SXCNFG_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM					    */
-	/* ---------------------------------------------------------------- */
-
-	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
-
-	orr	r4, r4, #MDREFR_K1RUN
-	bic	r4, r4, #MDREFR_K2DB2
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	bic	r4, r4, #MDREFR_SLFRSH
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	orr	r4, r4, #MDREFR_E1PIN
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	nop
-	nop
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*	    configure but not enable each SDRAM partition pair.	    */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
-
-	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
-	ldr	r4,	[r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
-	/*	    100..200 �sec.					    */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty	    */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
-	/*	    attempting non-burst read or write accesses to disabled */
-	/*	    SDRAM, as commonly specified in the power up sequence   */
-	/*	    documented in SDRAM data sheets. The address(es) used   */
-	/*	    for this purpose must not be cacheable.		    */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted		    */
-	/*	    (MDCNFG:DEx set to 1).				    */
-
-	ldr	r3,	[r1, #MDCNFG_OFFSET]
-	mov	r4, r3
-	orr	r3,	r3,	#MDCNFG_DE0
-	str	r3,	[r1, #MDCNFG_OFFSET]
-	mov	r0, r3
-
-	/* Step 4h: Write MDMRS.					    */
-
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	/* enable APD */
-	ldr	r3,  [r1, #MDREFR_OFFSET]
-	orr	r3,  r3,  #MDREFR_APD
-	str	r3,  [r1, #MDREFR_OFFSET]
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-setvoltage:
-
-	mov	r10,	lr
-	bl	initPXAvoltage	/* In case the board is rebooting with a    */
-	mov	lr,	r10	/* low voltage raise it up to a good one.   */
-
-#if 1
-	b initirqs
-#endif
-
-wakeup:
-	/* Are we waking from sleep? */
-	ldr	r0,	=RCSR
-	ldr	r1,	[r0]
-	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
-	str	r1,	[r0]
-	teq	r1,	#RCSR_SMR
-
-	bne	initirqs
-
-	ldr	r0,	=PSSR
-	mov	r1,	#PSSR_PH
-	str	r1,	[r0]
-
-	/* if so, resume at PSPR */
-	ldr	r0,	=PSPR
-	ldr	r1,	[r0]
-	mov	pc,	r1
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller	    */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
-	str	r1,  [r2]
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation						    */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-
-	/* Turn Off on-chip peripheral clocks (except for memory)	    */
-	/* for re-configuration.					    */
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN
-	str	r2,  [r1]
-
-	/* ... and write the core clock config register			    */
-	ldr	r2,  =CONFIG_SYS_CCCR
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-	/* Turn on turbo mode */
-	mrc	p14, 0, r2, c6, c0, 0
-	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
-	mcr	p14, 0, r2, c6, c0, 0
-
-	/* Re-write MDREFR */
-	ldr	r1, =MEMC_BASE
-	ldr	r2, [r1, #MDREFR_OFFSET]
-	str	r2, [r1, #MDREFR_OFFSET]
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager		    */
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
-	/* has settled.							    */
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#else
-#error "RTC not defined"
-#endif
-
-	/* Interrupt init: Mask all interrupts				    */
-    ldr r0, =ICMR /* enable no sources */
-	mov r1, #0
-    str r1, [r0]
-	/* FIXME */
-
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init							    */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov	pc, lr
diff --git a/board/ttcontrol/vision2/config.mk b/board/ttcontrol/vision2/config.mk
index 59f3367cfc9e8fc04bc6128ac124769b8d3112bd..952037e80606e5503a34ab9447b98f12e5c9c377 100644
--- a/board/ttcontrol/vision2/config.mk
+++ b/board/ttcontrol/vision2/config.mk
@@ -20,6 +20,6 @@
 # MA 02111-1307 USA
 #
 
-LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds
-TEXT_BASE = 0x97800000
+CONFIG_SYS_TEXT_BASE = 0x97800000
 IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
+ALL += $(obj)u-boot.imx
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index ce4cb78e9811f7e2f276b9dc8f7c3b7c7246f71f..f8ef4fc9c5134dfa23881150096f08a9cf4f8a0e 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -37,14 +37,34 @@
 #include <fsl_esdhc.h>
 #include <fsl_pmic.h>
 #include <mc13892.h>
+#include <linux/fb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static u32 system_rev;
 
+extern int mx51_fb_init(struct fb_videomode *mode);
+
 #ifdef CONFIG_HW_WATCHDOG
 #include <watchdog.h>
 
+static struct fb_videomode nec_nl6448bc26_09c = {
+	"NEC_NL6448BC26-09C",
+	60,	/* Refresh */
+	640,	/* xres */
+	480,	/* yres */
+	37650,	/* pixclock = 26.56Mhz */
+	48,	/* left margin */
+	16,	/* right margin */
+	31,	/* upper margin */
+	12,	/* lower margin */
+	96,	/* hsync-len */
+	2,	/* vsync-len */
+	0,	/* sync */
+	FB_VMODE_NONINTERLACED,	/* vmode */
+	0,	/* flag */
+};
+
 void hw_watchdog_reset(void)
 {
 	int val;
@@ -140,19 +160,8 @@ u32 get_board_rev(void)
 
 int dram_init(void)
 {
-#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
-		PHYS_SDRAM_1_SIZE);
-#if (CONFIG_NR_DRAM_BANKS > 1)
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
-		PHYS_SDRAM_2_SIZE);
-#endif
-#else
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
 		PHYS_SDRAM_1_SIZE);
-#endif
 
 	return 0;
 }
@@ -423,6 +432,9 @@ static void setup_gpios(void)
 	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
 	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
 
+	/* PWM Output GPIO1_2 */
+	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+
 	/*
 	 * Set GPIO1_4 to high and output; it is used to reset
 	 * the system on reboot
@@ -630,11 +642,35 @@ int board_early_init_f(void)
 	return 0;
 }
 
+static void backlight(int on)
+{
+	if (on) {
+		mxc_gpio_set(65, 1);
+		udelay(10000);
+		mxc_gpio_set(68, 1);
+	} else {
+		mxc_gpio_set(65, 0);
+		mxc_gpio_set(68, 0);
+	}
+}
+
+void lcd_enable(void)
+{
+	int ret;
+
+	mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+
+	mxc_gpio_set(2, 1);
+	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+
+	ret = mx51_fb_init(&nec_nl6448bc26_09c);
+	if (ret)
+		puts("LCD cannot be configured\n");
+}
+
 int board_init(void)
 {
-#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
-	board_early_init_f();
-#endif
 	gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2;	/* board id for linux */
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -709,3 +745,21 @@ int checkboard(void)
 	return 0;
 }
 
+int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int on;
+
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	on = (strcmp(argv[1], "on") == 0);
+	backlight(on);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
+	"Vision2 Backlight",
+	"lcdbl [on|off]\n"
+);
diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile
deleted file mode 100644
index 0669b0ebbae1c5636261e9fa04b5a3dc4ec1f56d..0000000000000000000000000000000000000000
--- a/board/wepep250/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= wepep250.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk
deleted file mode 100644
index 60cbc2429a55c7a85d402127bb024ecdc2628e66..0000000000000000000000000000000000000000
--- a/board/wepep250/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# This is config used for compilation of WEP EP250 sources
-#
-# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
-#CONFIG_SYS_TEXT_BASE = 0xa1001000
diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c
deleted file mode 100644
index c6e917167cb7251354be97dd2133d82bb5ae2d3f..0000000000000000000000000000000000000000
--- a/board/wepep250/flash.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- *       hopefully may work with other configurations.
- */
-
-#if ( WEP_FLASH_BUS_WIDTH == 1 )
-#  define FLASH_BUS vu_char
-#  define FLASH_BUS_RET u_char
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  else
-#    error "With 8bit bus only one chip is allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 2 )
-#  define FLASH_BUS vu_short
-#  define FLASH_BUS_RET u_short
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 8 )| x )
-#  else
-#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 4 )
-#  define FLASH_BUS vu_long
-#  define FLASH_BUS_RET u_long
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 16 )| x )
-#  elif ( WEP_FLASH_INTERLEAVE == 4 )
-#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-#  else
-#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-#  endif
-
-#else
-#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
-	FLASH_BUS *addr = (FLASH_BUS *) 0;
-
-	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
-	return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
-	int ok = 1;
-
-	reset_timer_masked ();
-	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
-		   FLASH_CMD (CFI_INTEL_SR_READY)) {
-		if (get_timer_masked () > timeout && timeout != 0) {
-			ok = 0;
-			break;
-		}
-	}
-	return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-#  error "WEP platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
-	int i;
-	FLASH_BUS address = WEP_FLASH_BASE;
-
-	flash_info[0].size = WEP_FLASH_BANK_SIZE;
-	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	flash_info[0].flash_id = INTEL_MANUFACT;
-	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
-		flash_info[0].start[i] = address;
-#ifdef WEP_FLASH_UNLOCK
-		/* Some devices are hw locked after start. */
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
-		flash_ready (0);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
-		address += WEP_FLASH_SECT_SIZE;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_SYS_FLASH_BASE,
-				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-				   &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_ENV_ADDR,
-				   CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return WEP_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	printf (" Intel vendor\n");
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if (!(i % 5)) {
-			printf ("\n");
-		}
-
-		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, non_protected = 0, sector;
-	int rc = ERR_OK;
-
-	FLASH_BUS *address;
-
-	for (sector = s_first; sector <= s_last; sector++) {
-		if (!info->protect[sector]) {
-			non_protected++;
-		}
-	}
-
-	if (!non_protected) {
-		return ERR_PROTECTED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	flag = disable_interrupts ();
-
-
-	/* Start erase on unprotected sectors */
-	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
-		if (info->protect[sector]) {
-			printf ("Protected sector %2d skipping...\n", sector);
-			continue;
-		} else {
-			printf ("Erasing sector %2d ... ", sector);
-		}
-
-		address = (FLASH_BUS *) (info->start[sector]);
-
-		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
-		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
-		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
-			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-			printf ("ok.\n");
-		} else {
-			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-			rc = ERR_TIMOUT;
-			printf ("timeout! Aborting...\n");
-			break;
-		}
-		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	}
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
-	FLASH_BUS *address = (FLASH_BUS *) dest;
-	int rc = ERR_OK;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*address & data) != data) {
-		return ERR_NOT_ERASED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-
-	flag = disable_interrupts ();
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
-	*address = data;
-
-	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
-		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-		rc = ERR_TIMOUT;
-		printf ("timeout! Aborting...\n");
-	}
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong read_addr, write_addr;
-	FLASH_BUS data;
-	int i, result = ERR_OK;
-
-
-	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
-	write_addr = read_addr;
-	if (read_addr != addr) {
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (read_addr < addr || cnt == 0) {
-				data |= *((uchar *) read_addr) << i * 8;
-			} else {
-				data |= (*src++) << i * 8;
-				cnt--;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-	}
-	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
-		if ((result = write_data (info, write_addr,
-								  *((FLASH_BUS *) src))) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-		src += sizeof (FLASH_BUS);
-	}
-	if (cnt > 0) {
-		read_addr = write_addr;
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (cnt > 0) {
-				data |= (*src++) << i * 8;
-				cnt--;
-			} else {
-				data |= *((uchar *) read_addr) << i * 8;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != 0) {
-			return result;
-		}
-	}
-	return ERR_OK;
-}
diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h
deleted file mode 100644
index 77498b6e1df77ec2941bded43d5da3c833f1a827..0000000000000000000000000000000000000000
--- a/board/wepep250/intel.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef	FLASH_INTEL_H
-#define	FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define	CFI_CHIP_INTEL_28F320J3A		0x0016
-#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
-#define	CFI_CHIP_INTEL_28F640J3A		0x0017
-#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
-#define	CFI_CHIP_INTEL_28F128J3A		0x0018
-#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define	CFI_CHIP_INTEL_28F640K3			0x8801
-#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
-#define	CFI_CHIP_INTEL_28F128K3			0x8802
-#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
-#define	CFI_CHIP_INTEL_28F256K3			0x8803
-#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
-#define	CFI_CHIP_INTEL_28F640K18		0x8805
-#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
-#define	CFI_CHIP_INTEL_28F128K18		0x8806
-#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
-#define	CFI_CHIP_INTEL_28F256K18		0x8807
-#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
-
-#endif /* FLASH_INTEL_H */
diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S
deleted file mode 100644
index 9bb091f5094a4914dc83d967e5f97cd662781b2d..0000000000000000000000000000000000000000
--- a/board/wepep250/lowlevel_init.S
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2001, 2002 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
- * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- * Documentation:
- * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- *     Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
- *     Revision 1.0, February 2002
- * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
- *     Revision 1.0, February 2002
- *
-*/
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-/*	setup memory - see 6.12 in [1]
- *	Step 1	- wait 200 us
- */
-	mov	r0,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r0, r0, #1
-	bne	1b
-/*	TODO: complete step 1 for Synchronous Static memory*/
-
-	ldr	r0, =0x48000000			/* MC_BASE */
-
-
-/*	step 1.a - setup MSCx
- */
-	ldr	r1, =0x000012B3			/* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
-	str	r1, [r0, #0x8]			/* MSC0_OFFSET */
-
-/*	step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
- *	see AUTO REFRESH chapter in section D. in [2] and in [3]
- *	DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
- *	DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
- *	TODO: complete for Synchronous Static memory
- */
-	ldr	r1, [r0, #4]			/* MDREFR_OFFSET */
-	ldr	r2, =0x01000FFF			/* MDREFR_K1FREE | MDREFR_DRI_MASK */
-	bic	r1, r1, r2
-#if defined( WEP_SDRAM_K4S281633 )
-	orr	r1, r1, #48			/* MDREFR_DRI(48) */
-#elif defined( WEP_SDRAM_K4S561633 )
-	orr	r1, r1, #24			/* MDREFR_DRI(24) */
-#else
-#error SDRAM chip is not defined
-#endif
-
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 2 - only for Synchronous Static memory (TODO)
- *
- *	Step 3 - same as step 4
- *
- *	Step 4
- *
- *	Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
- */
-	orr	r1, r1, #0x00010000		/* MDREFR_K1RUN */
-	bic	r1, r1, #0x00020000		/* MDREFR_K1DB2 */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.b - clear MDREFR:SLFRSH */
-	bic	r1, r1, #0x00400000		/* MDREFR_SLFRSH */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.c - set MDREFR:E1PIN */
-	orr	r1, r1, #0x00008000		/* MDREFR_E1PIN */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.d - automatically done
- *
- *	Steps 4.e and 4.f - configure SDRAM
- */
-#if defined( WEP_SDRAM_K4S281633 )
-	ldr	r1, =0x00000AA8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
-#elif defined( WEP_SDRAM_K4S561633 )
-	ldr	r1, =0x00000AC8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
-#else
-#error SDRAM chip is not defined
-#endif
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 5 - wait at least 200 us for SDRAM
- *	see section B. in [2]
- */
-	mov	r2,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r2, r2, #1
-	bne	1b
-
-/*	Step 6 - after reset dcache is disabled, so automatically done
- *
- *	Step 7 - eight refresh cycles
- */
-	mov	r2, #0xA0000000
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-
-/*	Step 8 - we don't need dcache now
- *
- *	Step 9 - enable SDRAM partition 0
- */
-	orr	r1, r1, #1			/* MDCNFG_DE0 */
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 10 - write MDMRS */
-	mov	r1, #0
-	str	r1, [r0, #0x40]			/* MDMRS_OFFSET */
-
-/*	Step 11 - optional (TODO) */
-
-	mov	pc,r10
diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
deleted file mode 100644
index 6e41ea6d01e5e5b5a5a89f4c5f74f806fc216396..0000000000000000000000000000000000000000
--- a/board/wepep250/wepep250.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
-	gd->bd->bi_boot_params = 0xa0000000;
-/*
- * Setup GPIO stuff to get serial working
- */
-#if defined( CONFIG_FFUART )
-	writel(0x80, GPDR1);
-	writel(0x8010, GAFR1_L);
-#elif defined( CONFIG_BTUART )
-	writel(0x800, GPDR1);
-	writel(0x900000, GAFR1_L);
-#endif
-	writel(0x20, PSSR);
-
-	return 0;
-}
-
-int dram_init (void)
-{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
-	gd->bd->bi_dram[0].start = WEP_SDRAM_1;
-	gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
-	gd->bd->bi_dram[1].start = WEP_SDRAM_2;
-	gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
-	gd->bd->bi_dram[2].start = WEP_SDRAM_3;
-	gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
-	gd->bd->bi_dram[3].start = WEP_SDRAM_4;
-	gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
-#endif
-
-	return 0;
-}
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
index 7dd2ea04a6958fbd3208aedef1b23126f7020dce..554915a6f98d0ac7329e8c28a0d86bcccb92ae54 100644
--- a/board/xaeniax/Makefile
+++ b/board/xaeniax/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= xaeniax.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/xaeniax/config.mk b/board/xaeniax/config.mk
deleted file mode 100644
index c63975279bf28368f26ee264f4d9e14dd73db728..0000000000000000000000000000000000000000
--- a/board/xaeniax/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa3FB0000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S
deleted file mode 100644
index 57e16200501a6ec2a55bf77d32ff98d1a3932d6c..0000000000000000000000000000000000000000
--- a/board/xaeniax/lowlevel_init.S
+++ /dev/null
@@ -1,424 +0,0 @@
- /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	 r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr	r0,=GPSR0
-	ldr	r1,=CONFIG_SYS_GPSR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPSR1
-	ldr	r1,=CONFIG_SYS_GPSR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPSR2
-	ldr	r1,=CONFIG_SYS_GPSR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR0
-	ldr	r1,=CONFIG_SYS_GPCR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR1
-	ldr	r1,=CONFIG_SYS_GPCR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR2
-	ldr	r1,=CONFIG_SYS_GPCR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR0
-	ldr	r1,=CONFIG_SYS_GPDR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR1
-	ldr	r1,=CONFIG_SYS_GPDR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR2
-	ldr	r1,=CONFIG_SYS_GPDR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR0_L
-	ldr	r1,=CONFIG_SYS_GAFR0_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR0_U
-	ldr	r1,=CONFIG_SYS_GAFR0_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR1_L
-	ldr	r1,=CONFIG_SYS_GAFR1_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR1_U
-	ldr	r1,=CONFIG_SYS_GAFR1_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR2_L
-	ldr	r1,=CONFIG_SYS_GAFR2_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR2_U
-	ldr	r1,=CONFIG_SYS_GAFR2_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=PSSR		/* enable GPIO pins */
-	ldr	r1,=CONFIG_SYS_PSSR_VAL
-	str	r1,[r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-
-	ldr	r1,=MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC0_VAL
-	str     r2,[r1, #MSC0_OFFSET]
-	ldr     r2,[r1, #MSC0_OFFSET]	/* read back to ensure data latches */
-
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC1_VAL
-	str     r2,[r1, #MSC1_OFFSET]
-	ldr     r2,[r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC2_VAL
-	str     r2,[r1, #MSC2_OFFSET]
-	ldr     r2,[r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,=CONFIG_SYS_MECR_VAL
-	str     r2,[r1, #MECR_OFFSET]
-	ldr	r2,[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,=CONFIG_SYS_MCMEM0_VAL
-	str     r2,[r1, #MCMEM0_OFFSET]
-	ldr	r2,[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,=CONFIG_SYS_MCMEM1_VAL
-	str     r2,[r1, #MCMEM1_OFFSET]
-	ldr	r2,[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,=CONFIG_SYS_MCATT0_VAL
-	str     r2,[r1, #MCATT0_OFFSET]
-	ldr	r2,[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,=CONFIG_SYS_MCATT1_VAL
-	str     r2,[r1, #MCATT1_OFFSET]
-	ldr	r2,[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,=CONFIG_SYS_MCIO0_VAL
-	str     r2,[r1, #MCIO0_OFFSET]
-	ldr	r2,[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,=CONFIG_SYS_MCIO1_VAL
-	str     r2,[r1, #MCIO1_OFFSET]
-	ldr	r2,[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	@ get the mdrefr settings
-	ldr     r4,=CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	str     r4,[r1, #MDREFR_OFFSET]
-	ldr     r4,[r1, #MDREFR_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	@ set K1RUN for bank 0
-	@
-	orr   r4,  r4,  #MDREFR_K1RUN
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic     r4,  r4,  #MDREFR_SLFRSH
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@ if E0PIN is also used:	 #(MDREFR_E1PIN|MDREFR_E0PIN)
-	orr     r4,  r4, #(MDREFR_E1PIN)
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-
-	/* Step 4d:							*/
-	/* fetch platform value of mdcnfg				*/
-	@
-	ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str     r2,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 �sec.                                          */
-
-	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/* get memory controller base address                               */
-	ldr     r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr     r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,	=CONFIG_SYS_MDMRS_VAL
-	str     r2,	[r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r1,  =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
-	ldr     r2,  =ICMR
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value						    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	@ Turn on needed clocks
-	@
-test:
-	ldr     r1,  =CKEN
-	ldr     r2,  =CONFIG_SYS_CKEN_VAL
-	str     r2,  [r1]
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size ?*/
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov     pc, lr
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
index 4c19c4dd4ef888a56e748d89c353ca60cb7d49ce..40b0f3b30e21b319581350fb58e95da05ec156c4 100644
--- a/board/xaeniax/xaeniax.c
+++ b/board/xaeniax/xaeniax.c
@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of xaeniax */
 	gd->bd->bi_arch_number = 585;
@@ -58,19 +59,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	/*	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
-	/*	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
-	/*	gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
-	/*	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
-	/*	gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
-	/*	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index d022831830a2de6020b7a80ead8e69e58b65c41f..16e0b66218a446a684245b3392ab7835d0e4726c 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -32,7 +32,11 @@ LIB	= $(obj)lib$(VENDOR).a
 COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
 COBJS-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
 COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
+COBJS-$(CONFIG_P2020)		+= fsl_8xxx_clk.o
 COBJS-$(CONFIG_FSL_DDR2)	+= fsl_8xxx_ddr.o
+COBJS-$(CONFIG_FSL_DDR3)	+= fsl_8xxx_ddr.o
+COBJS-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
+COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
 COBJS-$(CONFIG_NAND_ACTL)	+= actl_nand.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/xes/common/board.c b/board/xes/common/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..738f0a6486b483395a2c7f37bb8b3144e5b868ac
--- /dev/null
+++ b/board/xes/common/board.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include "fsl_8xxx_misc.h"
+
+int checkboard(void)
+{
+	char name[] = CONFIG_SYS_BOARD_NAME;
+	char *s;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+	s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+	s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+	s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+	s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+	s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+	s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+	s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+	s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+	s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+	s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+	s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+	s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+	s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+	s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+	name[strlen(name) - 1] += get_board_derivative();
+	printf("Board: X-ES %s %s SBC\n", name, s);
+
+	/* Display board specific information */
+	puts("       ");
+	if ((s = getenv("board_rev")))
+		printf("Rev %s, ", s);
+	if ((s = getenv("serial#")))
+		printf("Serial# %s, ", s);
+	if ((s = getenv("board_cfg")))
+		printf("Cfg %s", s);
+	puts("\n");
+
+	return 0;
+}
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index f4a17b78c6060e9463e31ff213be0302a03cbfd3..20d0a308b9a17f6fd4c70d022264bc6372260f61 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -38,7 +38,11 @@ unsigned long get_board_sys_clk(ulong dummy)
 	if (in_be32(&gur->gpporcr) & 0x10000)
 		return 66666666;
 	else
+#ifdef CONFIG_P2020
+		return 100000000;
+#else
 		return 50000000;
+#endif
 }
 
 #ifdef CONFIG_MPC85xx
@@ -54,6 +58,13 @@ unsigned long get_board_ddr_clk(ulong dummy)
 	if (ddr_ratio == 0x7)
 		return get_board_sys_clk(dummy);
 
+#ifdef CONFIG_P2020
+	if (in_be32(&gur->gpporcr) & 0x20000)
+		return 66666666;
+	else
+		return 100000000;
+#else
 	return 66666666;
+#endif
 }
 #endif
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
new file mode 100644
index 0000000000000000000000000000000000000000..36e9146654c941f89c3e8c149c02381d9135d0e4
--- /dev/null
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+	if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_NVM_WP)
+		return 1;
+
+	return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number.  For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+       volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+       volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+       /*
+	* The top 4 lines of the local bus address are pulled low/high and
+	* can be read to determine the least significant digit of a board's
+	* model number.
+	*/
+       return gur->gpporcr >> 28;
+}
diff --git a/board/palmtc/lowlevel_init.S b/board/xes/common/fsl_8xxx_misc.h
similarity index 63%
rename from board/palmtc/lowlevel_init.S
rename to board/xes/common/fsl_8xxx_misc.h
index 74050dc70cbbe4f1bd74a296cda07694d854304d..ecc70daba13498b530fc34d80c53ce6e4e24777f 100644
--- a/board/palmtc/lowlevel_init.S
+++ b/board/xes/common/fsl_8xxx_misc.h
@@ -1,7 +1,5 @@
 /*
- * Palm Tungsten|C Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -13,7 +11,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -22,18 +20,9 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
 
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
+uint get_board_derivative(void);
 
-	mov	pc, lr
+#endif /* __FSL_8XXX_MISC_H__ */
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index ece7882577852c5faca67d0a453226e99ddcd3c6..f425ceedc45664f90b48e13b3f84b3adb12f6429 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -25,10 +25,10 @@
 #include <pci.h>
 #include <asm/fsl_pci.h>
 #include <asm/io.h>
+#include <linux/compiler.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 
-int first_free_busno = 0;
 
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
@@ -43,111 +43,6 @@ static struct pci_controller pcie2_hose;
 static struct pci_controller pcie3_hose;
 #endif
 
-#ifdef CONFIG_MPC8572
-/* Correlate host/agent POR bits to usable info. Table 4-14 */
-struct host_agent_cfg_t {
-	uchar pcie_root[3];
-	uchar rio_host;
-} host_agent_cfg[8] = {
-	{{0, 0, 0}, 0},
-	{{0, 1, 1}, 1},
-	{{1, 0, 1}, 0},
-	{{1, 1, 0}, 1},
-	{{0, 0, 1}, 0},
-	{{0, 1, 0}, 1},
-	{{1, 0, 0}, 0},
-	{{1, 1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-15 */
-struct io_port_cfg_t {
-	uchar pcie_width[3];
-	uchar rio_width;
-} io_port_cfg[16] = {
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{4, 0, 0}, 0},
-	{{4, 4, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 4},
-	{{4, 2, 2}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{0, 0, 0}, 0},
-	{{4, 0, 0}, 4},
-	{{4, 0, 0}, 4},
-	{{0, 0, 0}, 4},
-	{{0, 0, 0}, 4},
-	{{8, 0, 0}, 0},
-};
-#elif defined CONFIG_MPC8548
-/* Correlate host/agent POR bits to usable info. Table 4-12 */
-struct host_agent_cfg_t {
-	uchar pci_host[2];
-	uchar pcie_root[1];
-	uchar rio_host;
-} host_agent_cfg[8] = {
-	{{1, 1}, {0}, 0},
-	{{1, 1}, {1}, 0},
-	{{1, 1}, {0}, 1},
-	{{0, 0}, {0}, 0}, /* reserved */
-	{{0, 1}, {1}, 0},
-	{{1, 1}, {1}, 0},
-	{{0, 1}, {1}, 1},
-	{{1, 1}, {1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-13 */
-struct io_port_cfg_t {
-	uchar pcie_width[1];
-	uchar rio_width;
-} io_port_cfg[8] = {
-	{{0}, 0},
-	{{0}, 0},
-	{{0}, 0},
-	{{4}, 4},
-	{{4}, 4},
-	{{0}, 4},
-	{{0}, 4},
-	{{8}, 0},
-};
-#elif defined CONFIG_MPC86xx
-/* Correlate host/agent POR bits to usable info. Table 4-17 */
-struct host_agent_cfg_t {
-	uchar pcie_root[2];
-	uchar rio_host;
-} host_agent_cfg[8] = {
-	{{0, 0}, 0},
-	{{1, 0}, 1},
-	{{0, 1}, 0},
-	{{1, 1}, 1}
-};
-
-/* Correlate port width POR bits to usable info. Table 4-16 */
-struct io_port_cfg_t {
-	uchar pcie_width[2];
-	uchar rio_width;
-} io_port_cfg[16] = {
-	{{0, 0}, 0},
-	{{0, 0}, 0},
-	{{8, 0}, 0},
-	{{8, 8}, 0},
-	{{0, 0}, 0},
-	{{8, 0}, 4},
-	{{8, 0}, 4},
-	{{8, 0}, 4},
-	{{0, 0}, 0},
-	{{0, 0}, 4},
-	{{0, 0}, 4},
-	{{0, 0}, 4},
-	{{0, 0}, 0},
-	{{0, 0}, 0},
-	{{0, 8}, 0},
-	{{8, 8}, 0},
-};
-#endif
-
 /*
  * 85xx and 86xx share naming conventions, but different layout.
  * Correlate names to CPU-specific values to share common
@@ -173,22 +68,22 @@ struct io_port_cfg_t {
 
 void pci_init_board(void)
 {
-	struct pci_controller *hose;
-	volatile ccsr_fsl_pci_t *pci;
-	int width;
-	int host;
+	struct fsl_pci_info pci_info[3];
+	int first_free_busno = 0;
+	int num = 0;
+	int pcie_ep;
+	__maybe_unused int pcie_configured;
+
 #if defined(CONFIG_MPC85xx)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #elif defined(CONFIG_MPC86xx)
 	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 #endif
-	uint devdisr = in_be32(&gur->devdisr);
-	uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >>
+	u32 devdisr = in_be32(&gur->devdisr);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	__maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
 			MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
-	uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >>
-			MPC8xxx_PORBMSR_HA_SHIFT;
-	struct pci_region *r;
 
 #ifdef CONFIG_PCI1
 	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
@@ -197,49 +92,19 @@ void pci_init_board(void)
 	uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
 	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 
-	width = 0; /* Silence compiler warning... */
-	io_sel &= 0xf; /* Silence compiler warning... */
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-	hose = &pci1_hose;
-	host = host_agent_cfg[host_agent].pci_host[0];
-	r = hose->regions;
-
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
 		printf("\n    PCI1: %d bit %s, %s %d MHz, %s, %s\n",
 			pci_32 ? 32 : 64,
 			pcix ? "PCIX" : "PCI",
 			pci_spd_norm ? ">=" : "<=",
 			pcix ? freq * 2 : freq,
-			host ? "host" : "agent",
+			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCI1_MEM_BASE,
-				CONFIG_SYS_PCI1_MEM_PHYS,
-				CONFIG_SYS_PCI1_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCI1_IO_BASE,
-				CONFIG_SYS_PCI1_IO_PHYS,
-				CONFIG_SYS_PCI1_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCI1 on bus %02x - %02x\n",
-			hose->first_busno, hose->last_busno);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pci1_hose, first_free_busno);
 	} else {
 		printf("    PCI1: disabled\n");
 	}
@@ -247,148 +112,53 @@ void pci_init_board(void)
 	/* PCI1 not present on MPC8572 */
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
-#ifdef CONFIG_PCIE1
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	hose = &pcie1_hose;
-	host = host_agent_cfg[host_agent].pcie_root[0];
-	width = io_port_cfg[io_sel].pcie_width[0];
-	r = hose->regions;
-
-	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
-		printf("\n    PCIE1 connected as %s (x%d)",
-			host ? "Root Complex" : "Endpoint", width);
-		if (in_be32(&pci->pme_msg_det)) {
-			out_be32(&pci->pme_msg_det, 0xffffffff);
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				in_be32(&pci->pme_msg_det));
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_MEM_BASE,
-				CONFIG_SYS_PCIE1_MEM_PHYS,
-				CONFIG_SYS_PCIE1_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_IO_BASE,
-				CONFIG_SYS_PCIE1_IO_PHYS,
-				CONFIG_SYS_PCIE1_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCIE1 on bus %02x - %02x\n",
-				hose->first_busno, hose->last_busno);
+#ifdef CONFIG_PCIE1
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+		printf("    PCIE1 connected as %s\n",
+			pcie_ep ? "Endpoint" : "Root Complex");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
+	} else {
+		printf("    PCIE1: disabled\n");
 	}
 #else
 	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
 #endif /* CONFIG_PCIE1 */
 
 #ifdef CONFIG_PCIE2
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	hose = &pcie2_hose;
-	host = host_agent_cfg[host_agent].pcie_root[1];
-	width = io_port_cfg[io_sel].pcie_width[1];
-	r = hose->regions;
-
-	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
-		printf("\n    PCIE2 connected as %s (x%d)",
-			host ? "Root Complex" : "Endpoint", width);
-		if (in_be32(&pci->pme_msg_det)) {
-			out_be32(&pci->pme_msg_det, 0xffffffff);
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				in_be32(&pci->pme_msg_det));
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE2_MEM_BASE,
-				CONFIG_SYS_PCIE2_MEM_PHYS,
-				CONFIG_SYS_PCIE2_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE2_IO_BASE,
-				CONFIG_SYS_PCIE2_IO_PHYS,
-				CONFIG_SYS_PCIE2_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCIE2 on bus %02x - %02x\n",
-				hose->first_busno, hose->last_busno);
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+		printf("    PCIE2 connected as %s\n",
+			pcie_ep ? "Endpoint" : "Root Complex");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie2_hose, first_free_busno);
+	} else {
+		printf("    PCIE2: disabled\n");
 	}
 #else
 	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
 #endif /* CONFIG_PCIE2 */
 
 #ifdef CONFIG_PCIE3
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
-	hose = &pcie3_hose;
-	host = host_agent_cfg[host_agent].pcie_root[2];
-	width = io_port_cfg[io_sel].pcie_width[2];
-	r = hose->regions;
-
-	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
-		printf("\n    PCIE3 connected as %s (x%d)",
-			host ? "Root Complex" : "Endpoint", width);
-		if (in_be32(&pci->pme_msg_det)) {
-			out_be32(&pci->pme_msg_det, 0xffffffff);
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				in_be32(&pci->pme_msg_det));
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE3_MEM_BASE,
-				CONFIG_SYS_PCIE3_MEM_PHYS,
-				CONFIG_SYS_PCIE3_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE3_IO_BASE,
-				CONFIG_SYS_PCIE3_IO_PHYS,
-				CONFIG_SYS_PCIE3_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		/* Unlock inbound PCI configuration cycles */
-		if (!host)
-			fsl_pci_config_unlock(hose);
-
-		first_free_busno = hose->last_busno + 1;
-		printf("    PCIE3 on bus %02x - %02x\n",
-				hose->first_busno, hose->last_busno);
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
+		SET_STD_PCIE_INFO(pci_info[num], 3);
+		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
+		printf("    PCIE3 connected as %s\n",
+			pcie_ep ? "Endpoint" : "Root Complex");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie3_hose, first_free_busno);
+	} else {
+		printf("    PCIE3: disabled\n");
 	}
 #else
 	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
diff --git a/board/xes/xpedite5170/Makefile b/board/xes/xpedite517x/Makefile
similarity index 100%
rename from board/xes/xpedite5170/Makefile
rename to board/xes/xpedite517x/Makefile
diff --git a/board/xes/xpedite5170/ddr.c b/board/xes/xpedite517x/ddr.c
similarity index 100%
rename from board/xes/xpedite5170/ddr.c
rename to board/xes/xpedite517x/ddr.c
diff --git a/board/xes/xpedite5170/law.c b/board/xes/xpedite517x/law.c
similarity index 100%
rename from board/xes/xpedite5170/law.c
rename to board/xes/xpedite517x/law.c
diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite517x/xpedite517x.c
similarity index 88%
rename from board/xes/xpedite5170/xpedite5170.c
rename to board/xes/xpedite517x/xpedite517x.c
index 58229418f36a5a4348c5f5b1f7ddcc5034c6897e..0f7fa6c43abe3767bb2dcb8bcc04bdc2b6590632 100644
--- a/board/xes/xpedite5170/xpedite5170.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -26,30 +26,12 @@
 #include <asm/io.h>
 #include <fdt_support.h>
 #include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
 
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 #endif
 
-int checkboard(void)
-{
-	char *s;
-
-	printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
-	printf("       ");
-	s = getenv("board_rev");
-	if (s)
-		printf("Rev %s, ", s);
-	s = getenv("serial#");
-	if (s)
-		printf("Serial# %s, ", s);
-	s = getenv("board_cfg");
-	if (s)
-		printf("Cfg %s", s);
-	printf("\n");
-
-	return 0;
-}
 /*
  * Print out which flash was booted from and if booting from the 2nd flash,
  * swap flash chip selects to maintain consistent flash numbering/addresses.
diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite520x/Makefile
similarity index 100%
rename from board/xes/xpedite5200/Makefile
rename to board/xes/xpedite520x/Makefile
diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite520x/ddr.c
similarity index 100%
rename from board/xes/xpedite5200/ddr.c
rename to board/xes/xpedite520x/ddr.c
diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite520x/law.c
similarity index 100%
rename from board/xes/xpedite5200/law.c
rename to board/xes/xpedite520x/law.c
diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite520x/tlb.c
similarity index 100%
rename from board/xes/xpedite5200/tlb.c
rename to board/xes/xpedite520x/tlb.c
diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite520x/xpedite520x.c
similarity index 79%
rename from board/xes/xpedite5200/xpedite5200.c
rename to board/xes/xpedite520x/xpedite520x.c
index a2627f8673604c1b89c2dd625cd0bf3365781981..dc5c96511423ea08714f549f198e1c904968e98e 100644
--- a/board/xes/xpedite5200/xpedite5200.c
+++ b/board/xes/xpedite520x/xpedite520x.c
@@ -36,33 +36,6 @@
 
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 
-int checkboard(void)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-	char *s;
-
-	printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
-	printf("       ");
-	s = getenv("board_rev");
-	if (s)
-		printf("Rev %s, ", s);
-	s = getenv("serial#");
-	if (s)
-		printf("Serial# %s, ", s);
-	s = getenv("board_cfg");
-	if (s)
-		printf("Cfg %s", s);
-	printf("\n");
-
-	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
-	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
-	out_be32(&ecm->eedr, 0xffffffff);	/* Clear ecm errors */
-	out_be32(&ecm->eeer, 0xffffffff);	/* Enable ecm errors */
-
-	return 0;
-}
-
 static void flash_cs_fixup(void)
 {
 	int flash_sel;
diff --git a/board/xes/xpedite5370/Makefile b/board/xes/xpedite537x/Makefile
similarity index 100%
rename from board/xes/xpedite5370/Makefile
rename to board/xes/xpedite537x/Makefile
diff --git a/board/xes/xpedite5370/ddr.c b/board/xes/xpedite537x/ddr.c
similarity index 100%
rename from board/xes/xpedite5370/ddr.c
rename to board/xes/xpedite537x/ddr.c
diff --git a/board/xes/xpedite5370/law.c b/board/xes/xpedite537x/law.c
similarity index 100%
rename from board/xes/xpedite5370/law.c
rename to board/xes/xpedite537x/law.c
diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite537x/tlb.c
similarity index 100%
rename from board/xes/xpedite5370/tlb.c
rename to board/xes/xpedite537x/tlb.c
diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite537x/xpedite537x.c
similarity index 89%
rename from board/xes/xpedite5370/xpedite5370.c
rename to board/xes/xpedite537x/xpedite537x.c
index 2a060c246251864193d714a32ad26303d535bcd4..89fa6c78b3034babba4e44b399ca39025f4c3942 100644
--- a/board/xes/xpedite5370/xpedite5370.c
+++ b/board/xes/xpedite537x/xpedite537x.c
@@ -36,26 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 
-int checkboard(void)
-{
-	char *s;
-
-	printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
-	printf("       ");
-	s = getenv("board_rev");
-	if (s)
-		printf("Rev %s, ", s);
-	s = getenv("serial#");
-	if (s)
-		printf("Serial# %s, ", s);
-	s = getenv("board_cfg");
-	if (s)
-		printf("Cfg %s", s);
-	printf("\n");
-
-	return 0;
-}
-
 static void flash_cs_fixup(void)
 {
 	int flash_sel;
diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..8980a4b3f6aae87a08873aee5243009492aa9123
--- /dev/null
+++ b/board/xes/xpedite550x/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
new file mode 100644
index 0000000000000000000000000000000000000000..38a459715fda4aa6642316aa7cbb6a05a7d85593
--- /dev/null
+++ b/board/xes/xpedite550x/ddr.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+		 sizeof(ddr3_spd_eeprom_t));
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+/*
+ *     There are traditionally three board-specific SDRAM timing parameters
+ *     which must be calculated based on the particular PCB artwork.  These are:
+ *     1.) CPO (Read Capture Delay)
+ *	       - TIMING_CFG_2 register
+ *	       Source: Calculation based on board trace lengths and
+ *		       chip-specific internal delays.
+ *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ *	       - DDR_SDRAM_CLK_CNTL register
+ *	       Source: Signal Integrity Simulations
+ *     3.) 2T Timing on Addr/Ctl
+ *	       - TIMING_CFG_2 register
+ *	       Source: Signal Integrity Simulations
+ *	       Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ *     ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ *     The P2020 processor provides an autoleveling option. Setting CPO to
+ *     0x1f enables this auto configuration.
+ */
+
+typedef struct {
+	unsigned short datarate_mhz_low;
+	unsigned short datarate_mhz_high;
+	unsigned char clk_adjust;
+	unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+		/* Controller 0 */
+		{
+			/* DDR3-600/667 */
+			.datarate_mhz_low	= 500,
+			.datarate_mhz_high	= 750,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+		{
+			/* DDR3-800 */
+			.datarate_mhz_low	= 750,
+			.datarate_mhz_high	= 850,
+			.clk_adjust		= 5,
+			.cpo			= 31,
+		},
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/*
+	 * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/*
+	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->twoT_en = 0;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+
+	/*
+	 * Enable on-die termination.
+	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR
+	 * is handled in the Freescale DDR3 driver.  Set RTT_Nom here.
+	 */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = 3;
+}
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
new file mode 100644
index 0000000000000000000000000000000000000000..4d4445d3108956da0bb8850c2cb449ade9c54219
--- /dev/null
+++ b/board/xes/xpedite550x/law.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
+#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
+#endif
+#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/tlb.c b/board/xes/xpedite550x/tlb.c
new file mode 100644
index 0000000000000000000000000000000000000000..cf3ff4d45f8149a1abe5d75163666cdc660b4dc3
--- /dev/null
+++ b/board/xes/xpedite550x/tlb.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* W**G* - NOR flashes */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G* - NAND flash */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 2, BOOKE_PAGESZ_1M, 1),
+
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+	/* *I*G* - PCIe */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
new file mode 100644
index 0000000000000000000000000000000000000000..2ad30a30f90284ab26419d25ca29817ad4b5448c
--- /dev/null
+++ b/board/xes/xpedite550x/xpedite550x.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+	int flash_sel;
+
+	/*
+	 * Print boot dev and swap flash flash chip selects if booted from 2nd
+	 * flash.  Swapping chip selects presents user with a common memory
+	 * map regardless of which flash was booted from.
+	 */
+	flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+			CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+	printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+	if (flash_sel) {
+		set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+		set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+		set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+		set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+	}
+}
+
+int board_early_init_r(void)
+{
+	/* Initialize PCA9557 devices */
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+	/*
+	 * Remap NOR flash region to caching-inhibited
+	 * so that flash can be erased/programmed properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* Invalidate existing TLB entry for NOR flash */
+	disable_tlb(0);
+	set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, 0, BOOKE_PAGESZ_256M, 1);
+
+	flash_cs_fixup();
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+	ft_board_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/xm250/Makefile b/board/xm250/Makefile
index a174f66199e0802bf2cb9c0e30bc8c9531dcd932..11e2b304c28208970622f8f27b178c8479e2995e 100644
--- a/board/xm250/Makefile
+++ b/board/xm250/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= xm250.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/xm250/config.mk b/board/xm250/config.mk
deleted file mode 100644
index a3fa0e5b91f3f3a5f7885756e1eb5e7062e5b880..0000000000000000000000000000000000000000
--- a/board/xm250/config.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys XM250 board:
-#
-
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xA3F80000
diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S
deleted file mode 100644
index 8230550c688b95df45aaac6c3ead29a178d671df..0000000000000000000000000000000000000000
--- a/board/xm250/lowlevel_init.S
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc	p15,0,\reg,c2,c0,0
-	mov	\reg,\reg
-	sub	pc,pc,#4
-	.endm
-/*
-	.macro SET_LED val
-	ldr	r6, =CRADLE_LED_CLR_REG
-	ldr	r7, =0
-	str	r7, [r6]
-	ldr	r6, =CRADLE_LED_SET_REG
-	ldr	r7, =\val
-	str	r7, [r6]
-	.endm
-*/
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-	/* Set up GPIO pins first */
-
-	ldr	r0,   =GPSR0
-	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR1
-	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR2
-	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR0
-	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR1
-	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR2
-	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER0
-	ldr	r1,   =CONFIG_SYS_GRER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER1
-	ldr	r1,   =CONFIG_SYS_GRER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER2
-	ldr	r1,   =CONFIG_SYS_GRER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER0
-	ldr	r1,   =CONFIG_SYS_GFER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER1
-	ldr	r1,   =CONFIG_SYS_GFER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER2
-	ldr	r1,   =CONFIG_SYS_GFER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR0
-	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR1
-	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR2
-	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_L
-	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_U
-	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_L
-	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_U
-	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_L
-	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_U
-	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
-	str	r1,   [r0]
-
-	/* enable GPIO pins */
-	ldr	r0,   =PSSR
-	ldr	r1,   =CONFIG_SYS_PSSR_VAL
-	str	r1,   [r0]
-
-	/* SET_LED 1 */
-
-	ldr	r3, =MSC1		/* low - bank 2 Lubbock Registers / SRAM */
-	ldr	r2, =CONFIG_SYS_MSC1_VAL	/* high - bank 3 Ethernet Controller */
-	str	r2, [r3]		/* need to set MSC1 before trying to write to the HEX LEDs */
-	ldr	r2, [r3]		/* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- *  Initlialize Memory Controller
- *
- *  See PXA250 Operating System Developer's Guide
- *
- *  pause for 200 uSecs- allow internal clocks to settle
- *  *Note: only need this if hard reset... doing it anyway for now
- */
-
-	@ Step 1
-	@ ---- Wait 200 usec
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-	/* SET_LED 2 */
-
-mem_init:
-	@ get memory controller base address
-	ldr	r1,  =MEMC_BASE
-
-
-@****************************************************************************
-@  Step 2
-@
-
-	@ Step 2a
-	@ write msc0, read back to ensure data latches
-	@
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]
-
-	@ write msc1
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	@ write msc2
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-	@ Step 2b
-	@ write mecr
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-
-	@ write mcmem0
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-
-	@ write mcmem1
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-
-	@ write mcatt0
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-
-	@ write mcatt1
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-
-	@ write mcio0
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-
-	@ write mcio1
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-
-	/*SET_LED 3 */
-
-	@ Step 2c
-	@ fly-by-dma is defeatured on this part
-	@ write flycnfg
-	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	@str	r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ extract DRI field (we need a valid DRI field)
-	@
-	ldr	r2,  =0xFFF
-
-	@ valid DRI field in r3
-	@
-	and	r3,  r3,  r2
-
-	@ get the reset state of MDREFR
-	@
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ clear the DRI field
-	@
-	bic	r4,  r4,  r2
-
-	@ insert the valid DRI field loaded above
-	@
-	orr	r4,  r4,  r3
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ *Note: preserve the mdrefr value in r4 *
-
-	/*SET_LED 4 */
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-	mov   pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-	@ clear the free-running clock bits
-	@ (clear K0Free, K1Free, K2Free
-	@
-	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4, #0x00002000
-
-	@ set K1RUN if bank 0 installed
-	@
-	orr	r4,  r4, #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#else
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r4,  =CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@  Step 4
-
-	@ set K0RUN for FLASH clock
-	@
-	orr	r4,  r4, #0x00002000
-
-	@ set K1RUN for bank DRAM 0
-	@
-	orr	r4,  r4, #0x00010000
-
-	@ set K2RUN for bank PLD
-	@
-	orr	r4,  r4, #0x00040000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#endif
-
-	@ Step 4d
-	@ fetch platform value of mdcnfg
-	@
-	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic	r2,  r2,  #MDCNFG_DWID0		@0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str	r2,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4e
-	@ pause for 200 uSecs
-	@
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-	/*SET_LED 5 */
-
-	/* Why is this here??? */
-	mov	r0, #0x78		@turn everything off
-	mcr	p15, 0, r0, c1, c0, 0	@(caches off, MMU off, etc.)
-
-	@ Step 4f
-	@ Access memory *not yet enabled* for CBR refresh cycles (8)
-	@ - CBR is generated for all banks
-
-	ldr	r2, =CONFIG_SYS_DRAM_BASE
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-
-	@ Step 4g
-	@get memory controller base address
-	@
-	ldr	r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr	r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr	r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str	r3,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4h
-	@ write mdmrs
-	@
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	@ Done Memory Init
-
-	/*SET_LED 6 */
-
-	@********************************************************************
-	@ Disable (mask) all interrupts at the interrupt controller
-	@
-
-	@ clear the interrupt level register (use IRQ, not FIQ)
-	@
-	mov	r1, #0
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	@ Set interrupt mask register
-	@
-	ldr	r1,  =CONFIG_SYS_ICMR_VAL
-	ldr	r2,  =ICMR
-	str	r1,  [r2]
-
-	@ ********************************************************************
-	@ Disable the peripheral clocks, and set the core clock
-	@
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-	ldr	r1,  =CKEN
-	mov	r2,  #0
-	str	r2,  [r1]
-
-	@ set core clocks
-	@
-	ldr	r2,  =CONFIG_SYS_CCCR_VAL
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-#ifdef ENABLE32KHZ
-	@ enable the 32Khz oscillator for RTC and PowerManager
-	@
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	@ NOTE:	 spin here until OSCC.OOK get set,
-	@	 meaning the PLL has settled.
-	@
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#endif
-
-	@ Turn on needed clocks
-	@
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN_VAL
-	str	r2,  [r1]
-
-	/*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0	/* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0	/* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0	/* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0	/* dcsr */
-
-#endif
-
-	/*SET_LED 8 */
-
-	mov	pc, r10
-
-@ End lowlevel_init
diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c
index 246bdde750271f1068dcc20ef0e70371b0371652..3188cf2fabb5aff0047fcd33e0162ad6fbbe0560 100644
--- a/board/xm250/xm250.c
+++ b/board/xm250/xm250.c
@@ -56,6 +56,10 @@ int
 board_init (void)
 /**********************************************************/
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	/* arch number of MicroSys XM250 */
 	gd->bd->bi_arch_number = MACH_TYPE_XM250;
 
@@ -65,21 +69,18 @@ board_init (void)
 	return 0;
 }
 
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-	return (0);
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/xsengine/config.mk b/board/xsengine/config.mk
deleted file mode 100644
index 821bb3b09260200c079e28e2d75a85dc4583f5d4..0000000000000000000000000000000000000000
--- a/board/xsengine/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xA3F80000
diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c
deleted file mode 100644
index 736905ad7178ff0c3d85e6185ab4c92beae07d84..0000000000000000000000000000000000000000
--- a/board/xsengine/flash.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define SWAP(x)               __swab32(x)
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Functions */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-			break;
-		case 1:
-			flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
-			break;
-		default:
-			panic ("configured too many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors */
-	flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
-	flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) return;
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
-			info->protect[i] = 0;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
-				break;
-	case FLASH_S29GL064M:	printf ("S29GL064M (64Mbit, top boot sector size)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
-	switch (value) {
-	case AMD_MANUFACT:
-		debug ("Manufacturer: AMD\n");
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		debug ("Manufacturer: FUJITSU\n");
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		debug ("Manufacturer: *** unknown ***\n");
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
-	switch (value) {
-
-	case AMD_ID_MIRROR:
-		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
-			addr[14], addr[15]);
-		switch(addr[14]) {
-		case AMD_ID_LV640U_2:
-			if (addr[15] != AMD_ID_LV640U_3) {
-				debug ("Chip: AMLV640U -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: AMLV640U\n");
-				info->flash_id += FLASH_AMLV640U;
-				info->sector_count = 128;
-				info->size = 0x01000000;
-			}
-			break;				/* => 16 MB	*/
-		case AMD_ID_GL064MT_2:
-			if (addr[15] != AMD_ID_GL064MT_3) {
-				debug ("Chip: S29GL064M-R3 -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: S29GL064M-R3\n");
-				info->flash_id += FLASH_S29GL064M;
-				info->sector_count = 128;
-				info->size = 0x01000000;
-			}
-			break;				/* => 16 MB	*/
-		default:
-			debug ("Chip: *** unknown ***\n");
-			info->flash_id = FLASH_UNKNOWN;
-			break;
-		}
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	switch (value) {
-	case AMD_ID_MIRROR:
-		switch (info->flash_id & FLASH_TYPEMASK) {
-		/* only known types here - no default */
-		case FLASH_AMLV128U:
-		case FLASH_AMLV640U:
-		case FLASH_AMLV320U:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				base += 0x20000;
-			}
-			break;
-		case FLASH_AMLV320B:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				/*
-				 * The first 8 sectors are 8 kB,
-				 * all the other ones  are 64 kB
-				 */
-				base += (i < 8)
-					?  2 * ( 8 << 10)
-					:  2 * (64 << 10);
-			}
-			break;
-		}
-		break;
-
-	default:
-		return (0);
-		break;
-	}
-
-#if 0
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-#endif
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 100000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, SWAP(data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S
deleted file mode 100644
index 0d94ab60a66569326a9256880d6c595885c0ae73..0000000000000000000000000000000000000000
--- a/board/xsengine/lowlevel_init.S
+++ /dev/null
@@ -1,221 +0,0 @@
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-.globl lowlevel_init
-lowlevel_init:
-
-   mov      r10, lr
-
-/* ---- GPIO INITIALISATION ---- */
-/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
-
-   /* General purpose set registers */
-   ldr      r0,   =GPSR0
-   ldr      r1,   =CONFIG_SYS_GPSR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPSR1
-   ldr      r1,   =CONFIG_SYS_GPSR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPSR2
-   ldr      r1,   =CONFIG_SYS_GPSR2_VAL
-   str      r1,   [r0]
-
-   /* General purpose clear registers */
-   ldr      r0,   =GPCR0
-   ldr      r1,   =CONFIG_SYS_GPCR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPCR1
-   ldr      r1,   =CONFIG_SYS_GPCR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPCR2
-   ldr      r1,   =CONFIG_SYS_GPCR2_VAL
-   str      r1,   [r0]
-
-   /* General rising edge registers */
-   ldr      r0,   =GRER0
-   ldr      r1,   =CONFIG_SYS_GRER0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GRER1
-   ldr      r1,   =CONFIG_SYS_GRER1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GRER2
-   ldr      r1,   =CONFIG_SYS_GRER2_VAL
-   str      r1,   [r0]
-
-   /* General falling edge registers */
-   ldr      r0,   =GFER0
-   ldr      r1,   =CONFIG_SYS_GFER0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GFER1
-   ldr      r1,   =CONFIG_SYS_GFER1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GFER2
-   ldr      r1,   =CONFIG_SYS_GFER2_VAL
-   str      r1,   [r0]
-
-   /* General edge detect registers */
-   ldr      r0,   =GPDR0
-   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR1
-   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR2
-   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
-   str      r1,   [r0]
-
-   /* General alternate function registers */
-   ldr      r0,   =GAFR0_L		/* [0:15] */
-   ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR0_U		/* [31:16] */
-   ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR1_L		/* [47:32] */
-   ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR1_U		/* [63:48] */
-   ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR2_L		/* [79:64] */
-   ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR2_U		/* [80] */
-   ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
-   str      r1,   [r0]
-
-   /* General purpose direction registers */
-   ldr      r0,   =GPDR0
-   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR1
-   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR2
-   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
-   str      r1,   [r0]
-
-   /* Power manager sleep status */
-   ldr      r0,   =PSSR
-   ldr      r1,   =CONFIG_SYS_PSSR_VAL
-   str      r1,   [r0]
-
-/* ---- MEMORY INITIALISATION ---- */
-/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
-/* pause for 200 uSecs- allow internal clocks to settle */
-   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300	/* really 0x2E1 is about 200usec, so 0x300 should be plenty */
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-mem_init:
-/* get memory controller base address */
-   ldr     r1,  =MEMC_BASE
-
-/* ---- FLASH INITIALISATION ---- */
-/* Write MSC0 and read back to ensure data change is accepted by cpu */
-   ldr     r2,   =CONFIG_SYS_MSC0_VAL
-   str     r2,   [r1, #MSC0_OFFSET]
-   ldr     r2,   [r1, #MSC0_OFFSET]
-
-/* ---- SDRAM INITIALISATION ---- */
-/* get the MDREFR settings */
-   ldr     r2,  =CONFIG_SYS_MDREFR_VAL
-   str     r2,  [r1, #MDREFR_OFFSET]
-
-/* fetch platform value of MDCNFG */
-   ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-/* disable all sdram banks */
-   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-/* write initial value of MDCNFG, w/o enabling sdram banks */
-   str     r2,  [r1, #MDCNFG_OFFSET]
-
-/* pause for 200 uSecs */
-   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300	/* about 200 usec */
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-/* Access memory *not yet enabled* for CBR refresh cycles (8) */
-/* CBR is generated for all banks */
-
-   ldr     r2, =CONFIG_SYS_DRAM_BASE
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-
-/* get memory controller base address */
-   ldr     r2,  =MEMC_BASE
-
-/* Enable SDRAM bank 0 in MDCNFG register */
-   ldr     r2,  [r1, #MDCNFG_OFFSET]
-   orr     r2,  r2,  #MDCNFG_DE0
-   str     r2,  [r1, #MDCNFG_OFFSET]
-
-/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
-   ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-   str     r2,  [r1, #MDMRS_OFFSET]
-
-/* ---- INTERRUPT INITIALISATION ---- */
-/* Disable (mask) all interrupts at the interrupt controller */
-/* clear the interrupt level register (use IRQ, not FIQ) */
-   mov     r1, #0
-   ldr     r2,  =ICLR
-   str     r1,  [r2]
-
-/* Set interrupt mask register */
-   ldr     r1,  =CONFIG_SYS_ICMR_VAL
-   ldr     r2,  =ICMR
-   str     r1,  [r2]
-
-/* ---- CLOCK INITIALISATION ---- */
-/* Disable the peripheral clocks, and set the core clock */
-
-/* Turn Off ALL on-chip peripheral clocks for re-configuration */
-   ldr     r1,  =CKEN
-   mov     r2,  #0
-   str     r2,  [r1]
-
-/* set core clocks */
-   ldr     r2,  =CONFIG_SYS_CCCR_VAL
-   ldr     r1,  =CCCR
-   str     r2,  [r1]
-
-#ifdef ENABLE32KHZ
-/* enable the 32Khz oscillator for RTC and PowerManager */
-   ldr     r1,  =OSCC
-   mov     r2,  #OSCC_OON
-   str     r2,  [r1]
-
-/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL has settled. */
-60:
-   ldr     r2, [r1]
-   ands    r2, r2, #1
-   beq     60b
-#endif
-
-/* Turn on needed clocks */
-   ldr     r1,  =CKEN
-   ldr     r2,  =CONFIG_SYS_CKEN_VAL
-   str     r2,  [r1]
-
-   mov   pc, r10
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
deleted file mode 100644
index 4464fd4a0a73789bd01fb0e47be2b9b3a5b8cddd..0000000000000000000000000000000000000000
--- a/board/xsengine/xsengine.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
-
-	/* arch number */
-	gd->bd->bi_arch_number = MACH_TYPE_XSENGINE;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	return 0;
-}
-
-int board_late_init (void)
-{
-	setenv ("stdout", "serial");
-	setenv ("stderr", "serial");
-	return 0;
-}
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/boards.cfg b/boards.cfg
index 0f3292fd3905526bb711139aa951a087959e981e..6c2a6672ff314816a27a6806a76ee0b122cadc8a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -65,7 +65,6 @@ balloon3	arm	pxa
 cerf250		arm	pxa
 cradle		arm	pxa
 csb226		arm	pxa
-delta		arm	pxa
 innokom		arm	pxa
 lubbock		arm	pxa
 palmld		arm	pxa
@@ -402,8 +401,6 @@ lpd7a400	arm	lh7a40x		lpd7a40x
 lpd7a404	arm	lh7a40x		lpd7a40x
 colibri_pxa270	arm	pxa
 pxa255_idp	arm	pxa
-wepep250	arm	pxa
-xsengine	arm	pxa
 zylonite	arm	pxa
 atngw100	avr32	at32ap		-		atmel		at32ap700x
 atstk1002	avr32	at32ap		atstk1000	atmel		at32ap700x
@@ -416,6 +413,7 @@ bct-brettl2	blackfin	blackfin
 bf518f-ezbrd	blackfin	blackfin
 bf526-ezbrd	blackfin	blackfin
 bf527-ezkit	blackfin	blackfin
+bf527-ezkit-v2	blackfin	blackfin	bf527-ezkit	-	-	bf527-ezkit:BF527_EZKIT_REV_2_1
 bf527-sdp	blackfin	blackfin
 bf533-ezkit	blackfin	blackfin
 bf533-stamp	blackfin	blackfin
@@ -527,7 +525,6 @@ MPC8272ADS	powerpc	mpc8260		mpc8260ads	freescale	-	MPC8260ADS:ADSTYPE=CONFIG_SYS
 PQ2FADS-VR	powerpc	mpc8260		mpc8260ads	freescale	-	MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000
 PQ2FADS-ZU	powerpc	mpc8260		mpc8260ads	freescale	-	MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS
 PQ2FADS_lowboot	powerpc	mpc8260		mpc8260ads	freescale	-	MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000
-VoVPN-GW_100MHz	powerpc	mpc8260		vovpn-gw	funkwerk	-	VoVPN-GW:CLKIN_100MHz
 VoVPN-GW_66MHz	powerpc	mpc8260		vovpn-gw	funkwerk	-	VoVPN-GW:CLKIN_66MHz
 MPC8308RDB	powerpc	mpc83xx		mpc8308rdb	freescale
 MPC8323ERDB	powerpc	mpc83xx		mpc8323erdb	freescale
@@ -556,8 +553,9 @@ MPC8540ADS	powerpc	mpc85xx		mpc8540ads	freescale
 MPC8544DS	powerpc	mpc85xx		mpc8544ds	freescale
 MPC8560ADS	powerpc	mpc85xx		mpc8560ads	freescale
 MPC8568MDS	powerpc	mpc85xx		mpc8568mds	freescale
-XPEDITE5200	powerpc	mpc85xx		xpedite5200	xes
-XPEDITE5370	powerpc	mpc85xx		xpedite5370	xes
+xpedite520x	powerpc	mpc85xx		-		xes
+xpedite537x	powerpc	mpc85xx		-		xes
+xpedite550x	powerpc	mpc85xx		-		xes
 sbc8540_33	powerpc	mpc85xx		sbc8560		-		-	SBC8540
 sbc8540_66	powerpc	mpc85xx		sbc8560		-		-	SBC8540
 sbc8548_PCI_33	powerpc	mpc85xx		sbc8548		-		-	sbc8548:PCI,33
@@ -597,7 +595,7 @@ P2020RDB_NAND	powerpc	mpc85xx		p1_p2_rdb	freescale	-	P1_P2_RDB:P2020,NAND
 P2020RDB_SDCARD	powerpc	mpc85xx		p1_p2_rdb	freescale	-	P1_P2_RDB:P2020,SDCARD
 sbc8641d	powerpc	mpc86xx
 MPC8610HPCD	powerpc	mpc86xx		mpc8610hpcd	freescale
-XPEDITE5170	powerpc	mpc86xx		xpedite5170	xes
+xpedite517x	powerpc	mpc86xx		-		xes
 MPC8641HPCN	powerpc	mpc86xx		mpc8641hpcn	freescale	-	MPC8641HPCN
 cogent_mpc8xx	powerpc	mpc8xx		cogent
 ESTEEM192E	powerpc	mpc8xx		esteem192e
@@ -644,11 +642,13 @@ CPCI405AB	powerpc	ppc4xx		cpci405		esd
 CPCI405DT	powerpc	ppc4xx		cpci405		esd
 dlvision	powerpc	ppc4xx		-		gdsys
 gdppc440etx	powerpc	ppc4xx		-		gdsys
+io		powerpc	ppc4xx		405ep		gdsys
+iocon		powerpc	ppc4xx		405ep		gdsys
 CPCIISER4	powerpc	ppc4xx		cpciiser4	esd
 DASA_SIM	powerpc	ppc4xx		dasa_sim	esd
 PMC405DE	powerpc	ppc4xx		pmc405de	esd
 METROBOX	powerpc	ppc4xx		metrobox	sandburst
-XPEDITE1000	powerpc	ppc4xx		xpedite1000	xes
+xpedite1000	powerpc	ppc4xx		-		xes
 korat_perm	powerpc	ppc4xx		korat		-		-	korat:KORAT_PERMANENT
 haleakala	powerpc	ppc4xx		kilauea		amcc		-	kilauea:HALEAKALA
 sycamore	powerpc	ppc4xx		walnut		amcc		-	walnut
@@ -732,5 +732,18 @@ davinci_dm6467evm arm	arm926ejs	dm6467evm	davinci		davinci
 davinci_schmoogie arm	arm926ejs	schmoogie	davinci		davinci
 davinci_dm355leopard arm arm926ejs	dm355leopard	davinci		davinci
 bf527-ad7160-eval blackfin	blackfin
+rsk7203	sh	sh2		rsk7203		renesas		-
+mpr2	sh	sh3		mpr2	-	-
+ms7720se	sh	sh3	ms7720se	-	-
+MigoRsh	sh4	MigoR	renesas	-   
+ms7750se	sh	sh4	ms7750se	-	-   
+ms7722se	sh	sh4	ms7722se	-	-   
+r2dplus	sh	sh4	r2dplus	renesas	-   
+r7780mp	sh	sh4	r7780mp	renesas	-   
+sh7763rdp	sh	sh4	sh7763rdp	renesas	-   
+sh7785lcr	sh	sh4	sh7785lcr	renesas	-   
+sh7785lcr_32bit	sh  sh4	sh7785lcr	renesas	-	sh7785lcr:SH_32BIT=1
+ap325rxa	sh	sh4	ap325rxa	renesas	-   
+espt	sh	sh4	espt	-	-
 # Target	ARCH	CPU		Board name	Vendor		SoC		Options
 ###############################################################################################
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 1326c8fac194901a48e3f2b09c1ef42d803b2f65..bba73746097757f969bdb7a7e8ed335b6073fb2d 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -192,7 +192,7 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	printf("CONFIG_SYS_PROM_OFFSET        = 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
 	       CONFIG_SYS_PROM_SIZE);
 	printf("CONFIG_SYS_GBL_DATA_OFFSET    = 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
-	       CONFIG_SYS_GBL_DATA_SIZE);
+	       GENERATED_GBL_DATA_SIZE);
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
@@ -343,7 +343,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf ("ip_addr     = %pI4\n", &bd->bi_ip_addr);
 #endif
 	printf ("baudrate    = %d bps\n", bd->bi_baudrate);
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
 	print_num ("TLB addr", gd->tlb_addr);
 #endif
@@ -352,7 +351,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num ("irq_sp", gd->irq_sp);	/* irq stack pointer */
 	print_num ("sp start ", gd->start_addr_sp);
 	print_num ("FB base  ", gd->fb_base);
-#endif
 	return 0;
 }
 
diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c
index 6fa8a150235200f2c14037e9acebff5ab49ea36f..f2a48f751c24aa3590a2066a9c6fda4739f2ff07 100644
--- a/common/cmd_bmp.c
+++ b/common/cmd_bmp.c
@@ -137,7 +137,7 @@ static cmd_tbl_t cmd_bmp_sub[] = {
 	U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""),
 };
 
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 void bmp_reloc(void) {
 	fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub));
 }
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index ce3c77c61574664f7fe38c482fc7a47604278cd3..1a024f168f7d1bea73fd7b0c26f81480ec602f4a 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -590,7 +590,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	ulong		load_end = 0;
 	int		ret;
 	boot_os_fn	*boot_fn;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 	static int relocated = 0;
 
 	/* relocate boot function table */
diff --git a/common/cmd_date.c b/common/cmd_date.c
index 50b42402673696c987e5f04e93b048f357ed64ba..8dbf16d32a1220772427fbbb133a8c9fd0282aba 100644
--- a/common/cmd_date.c
+++ b/common/cmd_date.c
@@ -35,10 +35,10 @@ const char *weekdays[] = {
 	"Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur",
 };
 
-#ifdef CONFIG_RELOC_FIXUP_WORKS
-#define RELOC(a)	a
-#else
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 #define RELOC(a)	((typeof(a))((unsigned long)(a) + gd->reloc_off))
+#else
+#define RELOC(a)	a
 #endif
 
 int mk_date (char *, struct rtc_time *);
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 0a0cfceb45ca6d7e424655dec811a6540355df31..c272b0dd4f7dda1782c2abe8b24cff299e0f99ee 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -1284,7 +1284,7 @@ static cmd_tbl_t cmd_i2c_sub[] = {
 	U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
 };
 
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 void i2c_reloc(void) {
 	fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
 }
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 3d30c321d5bae2a845fa2d00ab3db3ed8d4d3a4c..3fd8abc157f98f4f67326a90ceea5acbe6a77d25 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -837,7 +837,7 @@ static cmd_tbl_t cmd_env_sub[] = {
 	U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""),
 };
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 void env_reloc(void)
 {
 	fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub));
diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
index 83d967bd18169bab10f4b004ea1fc7d509e1e4f9..33108f1b34a833a789cc26f0d95f62bac7b518a7 100644
--- a/common/cmd_onenand.c
+++ b/common/cmd_onenand.c
@@ -525,10 +525,19 @@ static cmd_tbl_t cmd_onenand_sub[] = {
 	U_BOOT_CMD_MKENT(markbad, CONFIG_SYS_MAXARGS, 0, do_onenand_markbad, "", ""),
 };
 
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+void onenand_reloc(void) {
+	fixup_cmdtable(cmd_onenand_sub, ARRAY_SIZE(cmd_onenand_sub));
+}
+#endif
+
 static int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	cmd_tbl_t *c;
 
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
 	mtd = &onenand_mtd;
 
 	/* Strip off leading 'onenand' command argument */
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index 4bde0599118dd805dcc2cf8c0295f90eebb0847a..ccf5adaaad6b13d8cd77e62ed1ea5d5e46ec5e7d 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -497,6 +497,10 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		if ((bdf = get_pci_dev(argv[2])) == -1)
 			return 1;
 		break;
+#ifdef CONFIG_CMD_PCI_ENUM
+	case 'e':
+		break;
+#endif
 	default:		/* scan bus */
 		value = 1; /* short listing */
 		bdf = 0;   /* bus number  */
@@ -518,6 +522,11 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return 0;
 	case 'd':		/* display */
 		return pci_cfg_display(bdf, addr, size, value);
+#ifdef CONFIG_CMD_PCI_ENUM
+	case 'e':
+		pci_init();
+		return 0;
+#endif
 	case 'n':		/* next */
 		if (argc < 4)
 			goto usage;
@@ -545,6 +554,10 @@ U_BOOT_CMD(
 	"list and access PCI Configuration Space",
 	"[bus] [long]\n"
 	"    - short or long list of PCI devices on bus 'bus'\n"
+#ifdef CONFIG_CMD_PCI_ENUM
+	"pci enum\n"
+	"    - re-enumerate PCI buses\n"
+#endif
 	"pci header b.d.f\n"
 	"    - show header of PCI device 'bus.device.function'\n"
 	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
diff --git a/common/command.c b/common/command.c
index d47d719779fe728eb583c56c959c9704cef20dba..0020eacf5c46fe8d8da0617e4c449df03ad9e757 100644
--- a/common/command.c
+++ b/common/command.c
@@ -466,7 +466,7 @@ int cmd_get_data_size(char* arg, int default_size)
 }
 #endif
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 DECLARE_GLOBAL_DATA_PTR;
 
 void fixup_cmdtable(cmd_tbl_t *cmdtp, int size)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index fce7a762b1ed177906f03968c2ca0f4a8dcacbbf..4871f4b0990457a47732abe3c51f3f54a132f2e3 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1491,7 +1491,7 @@ static mbinptr av_[NAV * 2 + 2] = {
  IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127)
 };
 
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 void malloc_bin_reloc (void)
 {
 	unsigned long *p = (unsigned long *)(&av_[2]);
diff --git a/common/env_common.c b/common/env_common.c
index 5acda4d49ed66225889aa7e9e409652c9ad03cce..a276efc634717eb4740b4ce5351402eb3c6ee483 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -227,7 +227,7 @@ int env_import(const char *buf, int check)
 
 void env_relocate (void)
 {
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	extern void env_reloc(void);
 
 	env_reloc();
diff --git a/common/env_flash.c b/common/env_flash.c
index 1da78b7102e4c13b3589abb9a18e04d71bd4a927..54c0bfec7624192276886dbfa0c886fc13052a02 100644
--- a/common/env_flash.c
+++ b/common/env_flash.c
@@ -82,9 +82,6 @@ uchar env_get_char_spec(int index)
 	return (*((uchar *)(gd->env_addr + index)));
 }
 
-#undef debug
-#define debug printf
-
 #ifdef CONFIG_ENV_ADDR_REDUND
 
 int  env_init(void)
diff --git a/common/env_sf.c b/common/env_sf.c
index fb0c39b3ce8d654ea42a62acb4e8ced6d5af5f32..a597b24dcb35213c00eabedc73481219015bffe8 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -51,7 +51,7 @@ static ulong env_new_offset = CONFIG_ENV_OFFSET_REDUND;
 
 #define ACTIVE_FLAG   1
 #define OBSOLETE_FLAG 0
-#endif /* CONFIG_ENV_ADDR_REDUND */
+#endif /* CONFIG_ENV_OFFSET_REDUND */
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -69,13 +69,6 @@ uchar env_get_char_spec(int index)
 }
 
 #if defined(CONFIG_ENV_OFFSET_REDUND)
-void swap_env(void)
-{
-	ulong tmp_offset = env_offset;
-
-	env_offset = env_new_offset;
-	env_new_offset = tmp_offset;
-}
 
 int saveenv(void)
 {
@@ -89,8 +82,13 @@ int saveenv(void)
 	char	flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG;
 
 	if (!env_flash) {
-		puts("Environment SPI flash not initialized\n");
-		return 1;
+		env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+			CONFIG_ENV_SPI_CS,
+			CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+		if (!env_flash) {
+			set_default_env("!spi_flash_probe() failed");
+			return 1;
+		}
 	}
 
 	res = (char *)&env_new.data;
@@ -102,6 +100,14 @@ int saveenv(void)
 	env_new.crc   = crc32(0, env_new.data, ENV_SIZE);
 	env_new.flags = ACTIVE_FLAG;
 
+	if (gd->env_valid == 1) {
+		env_new_offset = CONFIG_ENV_OFFSET_REDUND;
+		env_offset = CONFIG_ENV_OFFSET;
+	} else {
+		env_new_offset = CONFIG_ENV_OFFSET;
+		env_offset = CONFIG_ENV_OFFSET_REDUND;
+	}
+
 	/* Is the sector larger than the env (i.e. embedded) */
 	if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) {
 		saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE;
@@ -130,27 +136,9 @@ int saveenv(void)
 		goto done;
 
 	puts("Writing to SPI flash...");
-	ret = spi_flash_write(env_flash,
-		env_new_offset + offsetof(env_t, data),
-		sizeof(env_new.data), env_new.data);
-	if (ret)
-		goto done;
-
-	ret = spi_flash_write(env_flash,
-		env_new_offset + offsetof(env_t, crc),
-		sizeof(env_new.crc), &env_new.crc);
-	if (ret)
-		goto done;
 
-	ret = spi_flash_write(env_flash,
-		env_offset + offsetof(env_t, flags),
-		sizeof(env_new.flags), &flag);
-	if (ret)
-		goto done;
-
-	ret = spi_flash_write(env_flash,
-		env_new_offset + offsetof(env_t, flags),
-		sizeof(env_new.flags), &new_flag);
+	ret = spi_flash_write(env_flash, env_new_offset,
+		CONFIG_ENV_SIZE, &env_new);
 	if (ret)
 		goto done;
 
@@ -161,11 +149,18 @@ int saveenv(void)
 			goto done;
 	}
 
-	swap_env();
+	ret = spi_flash_write(env_flash,
+		env_offset + offsetof(env_t, flags),
+		sizeof(env_new.flags), &flag);
+	if (ret)
+		goto done;
 
-	ret = 0;
 	puts("done\n");
 
+	gd->env_valid = (gd->env_valid == 2 ? 1 : 2);
+
+	printf("Valid environment: %d\n", gd->env_valid);
+
  done:
 	if (saved_buffer)
 		free(saved_buffer);
@@ -178,7 +173,7 @@ void env_relocate_spec(void)
 	int crc1_ok = 0, crc2_ok = 0;
 	env_t *tmp_env1 = NULL;
 	env_t *tmp_env2 = NULL;
-	env_t ep;
+	env_t *ep = NULL;
 	uchar flag1, flag2;
 	/* current_env is set only in case both areas are valid! */
 	int current_env = 0;
@@ -219,90 +214,57 @@ void env_relocate_spec(void)
 		flag2 = tmp_env2->flags;
 	}
 
-	if (!crc1_ok && !crc2_ok)
-		goto err_crc;
-	else if (crc1_ok && !crc2_ok) {
+	if (!crc1_ok && !crc2_ok) {
+		free(tmp_env1);
+		free(tmp_env2);
+		set_default_env("!bad CRC");
+		return;
+	} else if (crc1_ok && !crc2_ok) {
 		gd->env_valid = 1;
 		ep = tmp_env1;
 	} else if (!crc1_ok && crc2_ok) {
 		gd->env_valid = 1;
-		ep = tmp_env2;
-		swap_env();
 	} else if (flag1 == ACTIVE_FLAG && flag2 == OBSOLETE_FLAG) {
 		gd->env_valid = 1;
-		ep = tmp_env1;
 	} else if (flag1 == OBSOLETE_FLAG && flag2 == ACTIVE_FLAG) {
-		gd->env_valid = 1;
-		ep = tmp_env2;
-		swap_env();
+		gd->env_valid = 2;
 	} else if (flag1 == flag2) {
 		gd->env_valid = 2;
-		ep = tmp_env1;
-		current_env = 1;
 	} else if (flag1 == 0xFF) {
 		gd->env_valid = 2;
-		ep = tmp_env1;
-		current_env = 1;
 	} else {
 		/*
 		 * this differs from code in env_flash.c, but I think a sane
 		 * default path is desirable.
 		 */
 		gd->env_valid = 2;
-		ep = tmp_env2;
-		swap_env();
-		current_env = 2;
 	}
 
-	rc = env_import((char *)ep, 0);
-	if (!rc) {
-		error("Cannot import environment: errno = %d\n", errno);
-		goto out;
-	}
+	free(env_ptr);
 
-	if (current_env == 1) {
-		if (flag2 != OBSOLETE_FLAG) {
-			flag2 = OBSOLETE_FLAG;
-			spi_flash_write(env_flash,
-				env_new_offset + offsetof(env_t, flags),
-				sizeof(env_new.flags), &flag2);
-		}
-		if (flag1 != ACTIVE_FLAG) {
-			flag1 = ACTIVE_FLAG;
-			spi_flash_write(env_flash,
-				env_offset + offsetof(env_t, flags),
-				sizeof(env_new.flags), &flag1);
-		}
-	} else if (current_env == 2) {
-		if (flag1 != OBSOLETE_FLAG) {
-			flag1 = OBSOLETE_FLAG;
-			spi_flash_write(env_flash,
-				env_new_offset + offsetof(env_t, flags),
-				sizeof(env_new.flags), &flag1);
-		}
-		if (flag2 != ACTIVE_FLAG) {
-			flag2 = ACTIVE_FLAG;
-			spi_flash_write(env_flash,
-				env_offset + offsetof(env_t, flags),
-				sizeof(env_new.flags), &flag2);
-		}
-	}
-	if (gd->env_valid == 2) {
-		puts("*** Warning - some problems detected "
-			"reading environment; recovered successfully\n\n");
+	if (gd->env_valid == 1)
+		ep = tmp_env1;
+	else
+		ep = tmp_env2;
+
+	ret = env_import((char *)ep, 0);
+	if (!ret) {
+		error("Cannot import environment: errno = %d\n", errno);
+		set_default_env("env_import failed");
 	}
-	if (tmp_env1)
-		free(tmp_env1);
-	if (tmp_env2)
-		free(tmp_env2);
-	return;
 
 err_read:
 	spi_flash_free(env_flash);
 	env_flash = NULL;
 out:
+	if (tmp_env1)
+		free(tmp_env1);
+	if (tmp_env2)
+		free(tmp_env2);
 	free(tmp_env1);
 	free(tmp_env2);
+
+	return;
 }
 #else
 int saveenv(void)
@@ -311,10 +273,18 @@ int saveenv(void)
 	char *saved_buffer = NULL;
 	u32 sector = 1;
 	int ret;
+	env_t	env_new;
+	char	*res;
+	ssize_t	len;
 
 	if (!env_flash) {
-		puts("Environment SPI flash not initialized\n");
-		return 1;
+		env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+			CONFIG_ENV_SPI_CS,
+			CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+		if (!env_flash) {
+			set_default_env("!spi_flash_probe() failed");
+			return 1;
+		}
 	}
 
 	/* Is the sector larger than the env (i.e. embedded) */
@@ -326,7 +296,8 @@ int saveenv(void)
 			ret = 1;
 			goto done;
 		}
-		ret = spi_flash_read(env_flash, saved_offset, saved_size, saved_buffer);
+		ret = spi_flash_read(env_flash, saved_offset,
+			saved_size, saved_buffer);
 		if (ret)
 			goto done;
 	}
@@ -337,18 +308,29 @@ int saveenv(void)
 			sector++;
 	}
 
+	res = (char *)&env_new.data;
+	len = hexport('\0', &res, ENV_SIZE);
+	if (len < 0) {
+		error("Cannot export environment: errno = %d\n", errno);
+		goto done;
+	}
+	env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+
 	puts("Erasing SPI flash...");
-	ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE);
+	ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET,
+		sector * CONFIG_ENV_SECT_SIZE);
 	if (ret)
 		goto done;
 
 	puts("Writing to SPI flash...");
-	ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, env_ptr);
+	ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET,
+		CONFIG_ENV_SIZE, &env_new);
 	if (ret)
 		goto done;
 
 	if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) {
-		ret = spi_flash_write(env_flash, saved_offset, saved_size, saved_buffer);
+		ret = spi_flash_write(env_flash, saved_offset,
+			saved_size, saved_buffer);
 		if (ret)
 			goto done;
 	}
diff --git a/common/hush.c b/common/hush.c
index 4dd9513b0365475d06c6ee8d98cf8a3e77332f79..2188fd4ac8dd23b57f719c48d95918751cf5fa2f 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -3268,7 +3268,7 @@ int parse_file_outer(void)
 }
 
 #ifdef __U_BOOT__
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 static void u_boot_hush_reloc(void)
 {
 	unsigned long addr;
@@ -3290,7 +3290,7 @@ int u_boot_hush_start(void)
 		top_vars->next = 0;
 		top_vars->flg_export = 0;
 		top_vars->flg_read_only = 1;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 		u_boot_hush_reloc();
 #endif
 	}
diff --git a/common/hwconfig.c b/common/hwconfig.c
index 1f9f4a09b4b5a2293c995a9ef4a714b7a60099d0..3c9759fc557547fa8a2f0bc16fa87658fa166e23 100644
--- a/common/hwconfig.c
+++ b/common/hwconfig.c
@@ -26,6 +26,8 @@
 #define min(a, b) (((a) < (b)) ? (a) : (b))
 #endif /* HWCONFIG_TEST */
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static const char *hwconfig_parse(const char *opts, size_t maxlen,
 				  const char *opt, char *stopchs, char eqch,
 				  size_t *arglen)
@@ -69,9 +71,26 @@ next:
 const char *cpu_hwconfig __attribute__((weak));
 const char *board_hwconfig __attribute__((weak));
 
+#define HWCONFIG_PRE_RELOC_BUF_SIZE	128
+
 static const char *__hwconfig(const char *opt, size_t *arglen)
 {
-	const char *env_hwconfig = getenv("hwconfig");
+	const char *env_hwconfig = NULL;
+	char buf[HWCONFIG_PRE_RELOC_BUF_SIZE];
+
+	if (gd->flags & GD_FLG_ENV_READY) {
+		env_hwconfig = getenv("hwconfig");
+	} else {
+		/*
+		 * Use our own on stack based buffer before relocation to allow
+		 * accessing longer hwconfig strings that might be in the
+		 * environment before we've relocated.  This is pretty fragile
+		 * on both the use of stack and if the buffer is big enough.
+		 * However we will get a warning from getenv_f for the later.
+		 */
+		if ((getenv_f("hwconfig", buf, sizeof(buf))) > 0)
+			env_hwconfig = buf;
+	}
 
 	if (env_hwconfig)
 		return hwconfig_parse(env_hwconfig, strlen(env_hwconfig),
diff --git a/common/image.c b/common/image.c
index 89c10b8596ed969f95de976d70d1f6189d97e339..42f5b79cf2e6791f7966de3947c3cd4a6fce8ac7 100644
--- a/common/image.c
+++ b/common/image.c
@@ -520,7 +520,7 @@ char *get_table_entry_name (table_entry_t *table, char *msg, int id)
 {
 	for (; table->id >= 0; ++table) {
 		if (table->id == id)
-#if defined(USE_HOSTCC) || defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC)
 			return table->lname;
 #else
 			return table->lname + gd->reloc_off;
@@ -585,10 +585,10 @@ int get_table_entry_id (table_entry_t *table,
 	fprintf (stderr, "\n");
 #else
 	for (t = table; t->id >= 0; ++t) {
-#ifdef CONFIG_RELOC_FIXUP_WORKS
-		if (t->sname && strcmp(t->sname, name) == 0)
-#else
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 		if (t->sname && strcmp(t->sname + gd->reloc_off, name) == 0)
+#else
+		if (t->sname && strcmp(t->sname, name) == 0)
 #endif
 			return (t->id);
 	}
diff --git a/common/serial.c b/common/serial.c
index c3323ea51ac8609b566b80383c630538577736b7..051ae4e1d22d2880446dd9e87e69df501b6a8fa1 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -99,7 +99,7 @@ struct serial_device *default_serial_console(void) __attribute__((weak, alias("_
 
 int serial_register (struct serial_device *dev)
 {
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 	dev->init += gd->reloc_off;
 	dev->setbrg += gd->reloc_off;
 	dev->getc += gd->reloc_off;
diff --git a/common/stdio.c b/common/stdio.c
index 25013693f7db72e2f88e70dc20a732faf7a0c182..ab7c5abde1bbe3c0eb4048b07c7b390ef47adaec 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -193,7 +193,7 @@ int stdio_deregister(char *devname)
 
 int stdio_init (void)
 {
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	/* already relocated for current ARM implementation */
 	ulong relocation_offset = gd->reloc_off;
 	int i;
@@ -203,7 +203,7 @@ int stdio_init (void)
 		stdio_names[i] = (char *) (((ulong) stdio_names[i]) +
 						relocation_offset);
 	}
-#endif /* !CONFIG_RELOC_FIXUP_WORKS */
+#endif /* CONFIG_NEEDS_MANUAL_RELOC */
 
 	/* Initialize the list */
 	INIT_LIST_HEAD(&(devs.list));
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 613c4f0f1f7e79a653ad6267a8341e7c30207f80..1e6cd6af27491467870ad76cc61d7c631a8a277f 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -70,7 +70,7 @@
 /* direction table -- this indicates the direction of the data
  * transfer for each command code -- a 1 indicates input
  */
-unsigned char us_direction[256/8] = {
+static const unsigned char us_direction[256/8] = {
 	0x28, 0x81, 0x14, 0x14, 0x20, 0x01, 0x90, 0x77,
 	0x0C, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01,
diff --git a/disk/part.c b/disk/part.c
index 2b63db6c75f00f1b951f9bbf28dcbaab72929f82..13723f23b3113c74fa7b2590de65bf0d7d3c5a6b 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -81,13 +81,13 @@ block_dev_desc_t *get_dev(char* ifname, int dev)
 	char *name;
 
 	name = drvr->name;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 	name += gd->reloc_off;
 #endif
 	while (name) {
 		name = drvr->name;
 		reloc_get_dev = drvr->get_dev;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 		name += gd->reloc_off;
 		reloc_get_dev += gd->reloc_off;
 #endif
diff --git a/doc/README.LED_display b/doc/README.LED_display
index 521746e12912f56b8625ab4b6d3450bc8971d4d8..19977ea7e0d1aba27e961a82d090f3ba533698fe 100644
--- a/doc/README.LED_display
+++ b/doc/README.LED_display
@@ -14,7 +14,6 @@ This function should control the state of the LED display. Argument is
 an ORed combination of the following values:
  DISPLAY_CLEAR	-- clear the display
  DISPLAY_HOME	-- set the position to the beginning of display
- DISPLAY_MARK	-- enable mark (decimal point), if implemented
 
 int display_putc(char c);
 
diff --git a/doc/README.POST b/doc/README.POST
index eeb218d39c64c064cd69143a848676074f3b9404..6815d491cf4fbcaf790c332722257a279564e54e 100644
--- a/doc/README.POST
+++ b/doc/README.POST
@@ -659,12 +659,19 @@ not need any modifications for porting them to another board/CPU.
 2.2.2.1. I2C test
 
 For verifying the I2C bus, a full I2C bus scanning will be performed
-using the i2c_probe() routine. If any I2C device is found, the test
-will be considered as passed, otherwise failed. This particular way
-will be used because it provides the most common method of testing.
-For example, using the internal loopback mode of the CPM I2C
-controller for testing would not work on boards where the software
-I2C driver (also known as bit-banged driver) is used.
+using the i2c_probe() routine. If a board defines
+CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices
+listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional
+devices are detected.  If CONFIG_SYS_POST_I2C_ADDRS is not defined
+the test will pass if any I2C device is found.
+
+The CONFIG_SYS_POST_I2C_IGNORES define can be used to list I2C
+devices which may or may not be present when using
+CONFIG_SYS_POST_I2C_ADDRS.  The I2C POST test will pass regardless
+if the devices in CONFIG_SYS_POST_I2C_IGNORES are found or not.
+This is useful in cases when I2C devices are optional (eg on a
+daughtercard that may or may not be present) or not critical
+to board operation.
 
 2.2.2.2. Watchdog timer test
 
diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
index 3856633e9d90d49e2454815c6d46bcb0b1911d2c..c0957c210ceca37efd1c9c236768df57b8456c6e 100644
--- a/doc/README.arm-relocation
+++ b/doc/README.arm-relocation
@@ -34,18 +34,10 @@ At lib level:
 
 	Board.c code is adapted from ppc code
 
-At config level:
-
-	Define CONFIG_RELOC_FIXUP_WORKS.
-	Undefine CONFIG_SYS_ARM_WITHOUT_RELOC
-
 * WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING *
 
 Boards which are not fixed to support relocation will be REMOVED!
 
-Eventually, CONFIG_SYS_ARM_WITHOUT_RELOC and CONFIG_RELOC_FIXUP_WORKS will
-disappear and boards which have to migrated to relocation will disappear too.
-
 -----------------------------------------------------------------------------
 
 For boards which boot from nand_spl, it is possible to save one copy
@@ -93,7 +85,7 @@ Relocation with NAND_SPL (example for the tx25):
   and start with code execution on this address.
 
 - The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c
-  which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE  and loads
+  which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE	and loads
   the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
   @CONFIG_SYS_NAND_U_BOOT_START
 
@@ -162,7 +154,7 @@ e) load new symbol table:
 
 (gdb) add-symbol-file u-boot 0x8ff08000
 add symbol table from file "u-boot" at
-        .text_addr = 0x8ff08000
+	.text_addr = 0x8ff08000
 (y or n) y
 Reading symbols from /home/hs/celf/u-boot/u-boot...done.
 (gdb) c
@@ -170,12 +162,12 @@ Continuing.
 ^C
 Program received signal SIGSTOP, Stopped (signal).
 0x8ff17f18 in serial_getc () at serial_mxc.c:192
-192             while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+192		while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
 (gdb)
 
 add-symbol-file u-boot 0x8ff08000
-                       ^^^^^^^^^^
-                       get this address from u-boot debug printfs
+		       ^^^^^^^^^^
+		       get this address from u-boot debug printfs
 
 U-Boot 2010.06-rc2-00009-gf77b8b8-dirty (Jun 22 2010 - 09:43:46)
 
@@ -187,7 +179,7 @@ Top of RAM usable for U-Boot at: 90000000
 LCD panel info: 640 x 480, 16 bit/pix
 Reserving 600k for LCD Framebuffer at: 8ff6a000
 Reserving 391k for U-Boot at: 8ff08000
-                              ^^^^^^^^
+			      ^^^^^^^^
 Reserving 1280k for malloc() at: 8fdc8000
 Reserving 24 Bytes for Board Info at: 8fdc7fe8
 Reserving 52 Bytes for Global Data at: 8fdc7fb4
@@ -197,6 +189,6 @@ Bank #0: 80000000 256 MiB
 relocation Offset is: eff08000
 mon: 00058BAC gd->monLen: 00061F10
 Now running in RAM - U-Boot at: 8ff08000
-                                ^^^^^^^^
+				^^^^^^^^
 
 Now you can use gdb as usual :-)
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a707c6fa9376659992166ce3d3202d721c2c82e5..42865593bd773a185cf31e33806b6e63f7348880 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
 
 Board	Arch	CPU	removed	    Commit	last known maintainer/contact
 =============================================================================
+VoVPN-GW_100MHz	powerpc	MPC8260 - 2010-10-24	Juergen Selent <j.selent@elmeg.de>
 NC650	powerpc	MPC852	333d86d   2010-10-19	Wolfgang Denk <wd@denx.de>
 CP850	powerpc	MPC852	333d86d   2010-10-19	Wolfgang Denk <wd@denx.de>
 logodl	ARM	PXA2xx	059e778   2010-10-18	August Hoeraendl <august.hoerandl@gmx.at>
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index ffe261513c86867b3b6a0c53191ad868e02b4532..180ead5d81bed77352ce6f3995b8c7ffd4d7fc7c 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -5,33 +5,6 @@ and who is going to be doing the work.	When the feature is removed
 from U-Boot, its corresponding entry should also be removed from this
 file.
 
----------------------------
-What:	CONFIG_SYS_ARM_WITHOUT_RELOC option
-When:	After Release 2011.03
-
-Why:	The implementation of U-Boot for the ARM architecture has
-	been reworked to support relocation. This allows to
-	efficiently use the same U-Boot binary image on systems with
-	different RAM sizes, and brings the implementation much more
-	in line with the code used for example on Power Architecture
-	systems (eventually allowing to merge into common code). This
-	seems especailly interesting now that ARM is getting Device
-	Tree support as well.
-
-	All ARM boards need to be adapted to this new code, which
-	requires testing on the actual hardware, so this is a task
-	for the respective board maintainers or other users.
-
-	Please see the commit message of commit f1d2b31 for details:
-
-	http://git.denx.de/?p=u-boot.git;a=commit;h=f1d2b31
-
-	Support for CONFIG_SYS_ARM_WITHOUT_RELOC will be removed
-	after release v2011.03; all boards that have not been
-	converted by then, i. e. that are still broken then, are
-	considered unmaintained and without interest for the
-	community and will be removed as well.
-
 ---------------------------
 
 What:	CONFIG_NET_MULTI option
diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c
index a0e782310241580edce899f13127a201b0a5036a..c3b2355f9418c840e8727190b8daabec77e99b65 100644
--- a/drivers/fpga/lattice.c
+++ b/drivers/fpga/lattice.c
@@ -395,5 +395,3 @@ int lattice_info(Lattice_desc *desc)
 
 	return ret_val;
 }
-
-
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index a72d1a125702dd7f3f55ec2476a80b91ad6d7fea..fab49fd969eabb48487feb469c195612bedd2e1f 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -329,7 +329,7 @@ int i2c_probe (uchar chip)
 
 	while (1) {
 		status = wait_for_pin();
-		if (status == 0) {
+		if (status == 0 || status & I2C_STAT_AL) {
 			res = 1;
 			goto probe_exit;
 		}
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index c8371cf730c0256f911a3a54d05034fe8b584651..ba6f39bee11c6f831ffcfa3b9c15e31a6a8748b8 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -58,10 +58,10 @@ static int GetI2CSDA(void)
 	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 
 #ifdef CONFIG_S3C2410
-	return (readl(&gpio->GPEDAT) & 0x8000) >> 15;
+	return (readl(&gpio->gpedat) & 0x8000) >> 15;
 #endif
 #ifdef CONFIG_S3C2400
-	return (readl(&gpio->PGDAT) & 0x0020) >> 5;
+	return (readl(&gpio->pgdat) & 0x0020) >> 5;
 #endif
 }
 
@@ -77,10 +77,10 @@ static void SetI2CSCL(int x)
 	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 
 #ifdef CONFIG_S3C2410
-	writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT);
+	writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat);
 #endif
 #ifdef CONFIG_S3C2400
-	writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT);
+	writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
 #endif
 }
 
@@ -90,26 +90,26 @@ static int WaitForXfer(void)
 	int i;
 
 	i = I2C_TIMEOUT * 10000;
-	while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) {
+	while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
 		udelay(100);
 		i--;
 	}
 
-	return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
+	return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 }
 
 static int IsACK(void)
 {
 	struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
 
-	return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK);
+	return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
 }
 
 static void ReadWriteByte(void)
 {
 	struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
 
-	writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON);
+	writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 }
 
 void i2c_init(int speed, int slaveadd)
@@ -122,30 +122,30 @@ void i2c_init(int speed, int slaveadd)
 	/* wait for some time to give previous transfer a chance to finish */
 
 	i = I2C_TIMEOUT * 1000;
-	while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) {
+	while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) {
 		udelay(1000);
 		i--;
 	}
 
-	if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
+	if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 #ifdef CONFIG_S3C2410
-		ulong old_gpecon = readl(&gpio->GPECON);
+		ulong old_gpecon = readl(&gpio->gpecon);
 #endif
 #ifdef CONFIG_S3C2400
-		ulong old_gpecon = readl(&gpio->PGCON);
+		ulong old_gpecon = readl(&gpio->pgcon);
 #endif
 		/* bus still busy probably by (most) previously interrupted
 		   transfer */
 
 #ifdef CONFIG_S3C2410
 		/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
-		writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000,
-		       &gpio->GPECON);
+		writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
+		       &gpio->gpecon);
 #endif
 #ifdef CONFIG_S3C2400
 		/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
-		writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000,
-		       &gpio->PGCON);
+		writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
+		       &gpio->pgcon);
 #endif
 
 		/* toggle I2CSCL until bus idle */
@@ -164,10 +164,10 @@ void i2c_init(int speed, int slaveadd)
 
 		/* restore pin functions */
 #ifdef CONFIG_S3C2410
-		writel(old_gpecon, &gpio->GPECON);
+		writel(old_gpecon, &gpio->gpecon);
 #endif
 #ifdef CONFIG_S3C2400
-		writel(old_gpecon, &gpio->PGCON);
+		writel(old_gpecon, &gpio->pgcon);
 #endif
 	}
 
@@ -183,13 +183,13 @@ void i2c_init(int speed, int slaveadd)
 
 	/* set prescaler, divisor according to freq, also set
 	 * ACKGEN, IRQ */
-	writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON);
+	writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 
 	/* init to SLAVE REVEIVE and set slaveaddr */
-	writel(0, &i2c->IICSTAT);
-	writel(slaveadd, &i2c->IICADD);
+	writel(0, &i2c->iicstat);
+	writel(slaveadd, &i2c->iicadd);
 	/* program Master Transmit (and implicit STOP) */
-	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
+	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 
 }
 
@@ -218,47 +218,47 @@ int i2c_transfer(unsigned char cmd_type,
 
 	/* Check I2C bus idle */
 	i = I2C_TIMEOUT * 1000;
-	while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) {
+	while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 		udelay(1000);
 		i--;
 	}
 
-	if (readl(&i2c->IICSTAT) & I2CSTAT_BSY)
+	if (readl(&i2c->iicstat) & I2CSTAT_BSY)
 		return I2C_NOK_TOUT;
 
-	writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON);
+	writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon);
 	result = I2C_OK;
 
 	switch (cmd_type) {
 	case I2C_WRITE:
 		if (addr && addr_len) {
-			writel(chip, &i2c->IICDS);
+			writel(chip, &i2c->iicds);
 			/* send START */
 			writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
-			       &i2c->IICSTAT);
+			       &i2c->iicstat);
 			i = 0;
 			while ((i < addr_len) && (result == I2C_OK)) {
 				result = WaitForXfer();
-				writel(addr[i], &i2c->IICDS);
+				writel(addr[i], &i2c->iicds);
 				ReadWriteByte();
 				i++;
 			}
 			i = 0;
 			while ((i < data_len) && (result == I2C_OK)) {
 				result = WaitForXfer();
-				writel(data[i], &i2c->IICDS);
+				writel(data[i], &i2c->iicds);
 				ReadWriteByte();
 				i++;
 			}
 		} else {
-			writel(chip, &i2c->IICDS);
+			writel(chip, &i2c->iicds);
 			/* send START */
 			writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
-			       &i2c->IICSTAT);
+			       &i2c->iicstat);
 			i = 0;
 			while ((i < data_len) && (result = I2C_OK)) {
 				result = WaitForXfer();
-				writel(data[i], &i2c->IICDS);
+				writel(data[i], &i2c->iicds);
 				ReadWriteByte();
 				i++;
 			}
@@ -268,42 +268,42 @@ int i2c_transfer(unsigned char cmd_type,
 			result = WaitForXfer();
 
 		/* send STOP */
-		writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+		writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 		ReadWriteByte();
 		break;
 
 	case I2C_READ:
 		if (addr && addr_len) {
-			writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
-			writel(chip, &i2c->IICDS);
+			writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
+			writel(chip, &i2c->iicds);
 			/* send START */
-			writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
-			       &i2c->IICSTAT);
+			writel(readl(&i2c->iicstat) | I2C_START_STOP,
+			       &i2c->iicstat);
 			result = WaitForXfer();
 			if (IsACK()) {
 				i = 0;
 				while ((i < addr_len) && (result == I2C_OK)) {
-					writel(addr[i], &i2c->IICDS);
+					writel(addr[i], &i2c->iicds);
 					ReadWriteByte();
 					result = WaitForXfer();
 					i++;
 				}
 
-				writel(chip, &i2c->IICDS);
+				writel(chip, &i2c->iicds);
 				/* resend START */
 				writel(I2C_MODE_MR | I2C_TXRX_ENA |
-				       I2C_START_STOP, &i2c->IICSTAT);
+				       I2C_START_STOP, &i2c->iicstat);
 				ReadWriteByte();
 				result = WaitForXfer();
 				i = 0;
 				while ((i < data_len) && (result == I2C_OK)) {
 					/* disable ACK for final READ */
 					if (i == data_len - 1)
-						writel(readl(&i2c->IICCON)
-						       & ~0x80, &i2c->IICCON);
+						writel(readl(&i2c->iiccon)
+						       & ~0x80, &i2c->iiccon);
 					ReadWriteByte();
 					result = WaitForXfer();
-					data[i] = readl(&i2c->IICDS);
+					data[i] = readl(&i2c->iicds);
 					i++;
 				}
 			} else {
@@ -311,11 +311,11 @@ int i2c_transfer(unsigned char cmd_type,
 			}
 
 		} else {
-			writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
-			writel(chip, &i2c->IICDS);
+			writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+			writel(chip, &i2c->iicds);
 			/* send START */
-			writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
-			       &i2c->IICSTAT);
+			writel(readl(&i2c->iicstat) | I2C_START_STOP,
+			       &i2c->iicstat);
 			result = WaitForXfer();
 
 			if (IsACK()) {
@@ -323,11 +323,11 @@ int i2c_transfer(unsigned char cmd_type,
 				while ((i < data_len) && (result == I2C_OK)) {
 					/* disable ACK for final READ */
 					if (i == data_len - 1)
-						writel(readl(&i2c->IICCON) &
-						       ~0x80, &i2c->IICCON);
+						writel(readl(&i2c->iiccon) &
+						       ~0x80, &i2c->iiccon);
 					ReadWriteByte();
 					result = WaitForXfer();
-					data[i] = readl(&i2c->IICDS);
+					data[i] = readl(&i2c->iicds);
 					i++;
 				}
 			} else {
@@ -336,7 +336,7 @@ int i2c_transfer(unsigned char cmd_type,
 		}
 
 		/* send STOP */
-		writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+		writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 		ReadWriteByte();
 		break;
 
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c543d837dc7e286dff1b28546e3ba7af7fd58dd0..eb7bfb39e925f45807e8d54eec9933c4f18f665a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -78,17 +78,11 @@ struct mmc *find_mmc_device(int dev_num)
 }
 
 static ulong
-mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
+mmc_write_blocks(struct mmc *mmc, ulong start, lbaint_t blkcnt, const void*src)
 {
 	struct mmc_cmd cmd;
 	struct mmc_data data;
-	int err;
-	int stoperr = 0;
-	struct mmc *mmc = find_mmc_device(dev_num);
-	int blklen;
-
-	if (!mmc)
-		return -1;
+	int blklen, err;
 
 	blklen = mmc->write_bl_len;
 
@@ -97,12 +91,6 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
 			start + blkcnt, mmc->block_dev.lba);
 		return 0;
 	}
-	err = mmc_set_blocklen(mmc, mmc->write_bl_len);
-
-	if (err) {
-		printf("set write bl len failed\n\r");
-		return err;
-	}
 
 	if (blkcnt > 1)
 		cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
@@ -134,9 +122,45 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
 		cmd.cmdarg = 0;
 		cmd.resp_type = MMC_RSP_R1b;
 		cmd.flags = 0;
-		stoperr = mmc_send_cmd(mmc, &cmd, NULL);
+		err = mmc_send_cmd(mmc, &cmd, NULL);
+		if (err) {
+			printf("mmc fail to send stop cmd\n\r");
+			return err;
+		}
+	}
+
+	return blkcnt;
+}
+
+static ulong
+mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
+{
+	int err;
+	struct mmc *mmc = find_mmc_device(dev_num);
+	lbaint_t cur, blocks_todo = blkcnt;
+
+	if (!mmc)
+		return -1;
+
+	err = mmc_set_blocklen(mmc, mmc->write_bl_len);
+	if (err) {
+		printf("set write bl len failed\n\r");
+		return err;
 	}
 
+	do {
+		/*
+		 * The 65535 constraint comes from some hardware has
+		 * only 16 bit width block number counter
+		 */
+		cur = (blocks_todo > 65535) ? 65535 : blocks_todo;
+		if(mmc_write_blocks(mmc, start, cur, src) != cur)
+			return -1;
+		blocks_todo -= cur;
+		start += cur;
+		src += cur * mmc->write_bl_len;
+	} while (blocks_todo > 0);
+
 	return blkcnt;
 }
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 9271470e3681cff18ddf95d9287345d338fc325b..c7f76209f33cbe8a6ca23d490bf31958c121ec4c 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -412,4 +412,3 @@ int omap_mmc_init(int dev_index)
 
 	return 0;
 }
-
diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c
index 1fd425cbb67467d4ae2e4c6443a5f73c0e72abc8..195b5be39ea2d33fe12168d3603c165a48727dae 100644
--- a/drivers/mmc/s5p_mmc.c
+++ b/drivers/mmc/s5p_mmc.c
@@ -352,11 +352,16 @@ static void mmc_set_ios(struct mmc *mmc)
 	ctrl = readb(&host->reg->hostctl);
 
 	/*
+	 * WIDE8[5]
+	 * 0 = Depend on WIDE4
+	 * 1 = 8-bit mode
 	 * WIDE4[1]
 	 * 1 = 4-bit mode
 	 * 0 = 1-bit mode
 	 */
-	if (mmc->bus_width == 4)
+	if (mmc->bus_width == 8)
+		ctrl |= (1 << 5);
+	else if (mmc->bus_width == 4)
 		ctrl |= (1 << 1);
 	else
 		ctrl &= ~(1 << 1);
@@ -437,7 +442,7 @@ static int mmc_core_init(struct mmc *mmc)
 	return 0;
 }
 
-static int s5p_mmc_initialize(int dev_index)
+static int s5p_mmc_initialize(int dev_index, int bus_width)
 {
 	struct mmc *mmc;
 
@@ -450,7 +455,11 @@ static int s5p_mmc_initialize(int dev_index)
 	mmc->init = mmc_core_init;
 
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
+	if (bus_width == 8)
+		mmc->host_caps = MMC_MODE_8BIT;
+	else
+		mmc->host_caps = MMC_MODE_4BIT;
+	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	mmc->f_min = 400000;
 	mmc->f_max = 52000000;
@@ -462,7 +471,7 @@ static int s5p_mmc_initialize(int dev_index)
 	return 0;
 }
 
-int s5p_mmc_init(int dev_index)
+int s5p_mmc_init(int dev_index, int bus_width)
 {
-	return s5p_mmc_initialize(dev_index);
+	return s5p_mmc_initialize(dev_index, bus_width);
 }
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 798902f337698d9e54dad633dcc134481fa2069e..c92c7a7a490cd8c7fa45fec2c7091ecbcdebb010 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -85,6 +85,17 @@ static phys_addr_t __cfi_flash_bank_addr(int i)
 phys_addr_t cfi_flash_bank_addr(int i)
 	__attribute__((weak, alias("__cfi_flash_bank_addr")));
 
+static unsigned long __cfi_flash_bank_size(int i)
+{
+#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
+	return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
+#else
+	return 0;
+#endif
+}
+unsigned long cfi_flash_bank_size(int i)
+	__attribute__((weak, alias("__cfi_flash_bank_size")));
+
 static void __flash_write8(u8 value, void *addr)
 {
 	__raw_writeb(value, addr);
@@ -1826,7 +1837,7 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
  * The following code cannot be run from FLASH!
  *
  */
-ulong flash_get_size (phys_addr_t base, int banknum)
+ulong flash_get_size (phys_addr_t base, int banknum, unsigned long max_size)
 {
 	flash_info_t *info = &flash_info[banknum];
 	int i, j;
@@ -1915,6 +1926,13 @@ ulong flash_get_size (phys_addr_t base, int banknum)
 		debug ("size_ratio %d port %d bits chip %d bits\n",
 		       size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+		info->size = 1 << qry.dev_size;
+		/* multiply the size by the number of chips */
+		info->size *= size_ratio;
+		if (max_size && (info->size > max_size)) {
+			debug("[truncated from %ldMiB]", info->size >> 20);
+			info->size = max_size;
+		}
 		debug ("found %d erase regions\n", num_erase_regions);
 		sect_cnt = 0;
 		sector = base;
@@ -1935,6 +1953,8 @@ ulong flash_get_size (phys_addr_t base, int banknum)
 			debug ("erase_region_count = %d erase_region_size = %d\n",
 				erase_region_count, erase_region_size);
 			for (j = 0; j < erase_region_count; j++) {
+				if (sector - base >= info->size)
+					break;
 				if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
 					printf("ERROR: too many flash sectors\n");
 					break;
@@ -1968,9 +1988,6 @@ ulong flash_get_size (phys_addr_t base, int banknum)
 		}
 
 		info->sector_count = sect_cnt;
-		info->size = 1 << qry.dev_size;
-		/* multiply the size by the number of chips */
-		info->size *= size_ratio;
 		info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
 		tmp = 1 << qry.block_erase_timeout_typ;
 		info->erase_blk_tout = tmp *
@@ -2026,7 +2043,8 @@ unsigned long flash_init (void)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 		if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
-			flash_get_size(cfi_flash_bank_addr(i), i);
+			flash_get_size(cfi_flash_bank_addr(i), i,
+					cfi_flash_bank_size(i));
 		size += flash_info[i].size;
 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
 #ifndef CONFIG_SYS_FLASH_QUIET_TEST
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 47d6872fd03cd1ce277c04d18d187e4ccfb5f34b..c0e068ab7d5f9c08973961055242a4bb581798cd 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -54,7 +54,7 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
 		if (nand_scan(mtd, maxchips) == 0) {
 			if (!mtd->name)
 				mtd->name = (char *)default_nand_name;
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 			else
 				mtd->name += gd->reloc_off;
 #endif
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index a27d47e5f1f7c4c7c58f17d11b2bb6812a25b0d5..f70daefbfe126c5910dffd444697e79b00312773 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -69,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 		chip->IO_ADDR_W = (void *)IO_ADDR_W;
 
 		if (ctrl & NAND_NCE)
-			writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
-			       &nand->NFCONF);
+			writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
+			       &nand->nfconf);
 		else
-			writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
-			       &nand->NFCONF);
+			writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
+			       &nand->nfconf);
 	}
 
 	if (cmd != NAND_CMD_NONE)
@@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd)
 {
 	struct s3c2410_nand *nand = s3c2410_get_base_nand();
 	debugX(1, "dev_ready\n");
-	return readl(&nand->NFSTAT) & 0x01;
+	return readl(&nand->nfstat) & 0x01;
 }
 
 #ifdef CONFIG_S3C2410_NAND_HWECC
@@ -92,16 +92,16 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	struct s3c2410_nand *nand = s3c2410_get_base_nand();
 	debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
-	writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
+	writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
 }
 
 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 				      u_char *ecc_code)
 {
 	struct s3c2410_nand *nand = s3c2410_get_base_nand();
-	ecc_code[0] = readb(&nand->NFECC);
-	ecc_code[1] = readb(&nand->NFECC + 1);
-	ecc_code[2] = readb(&nand->NFECC + 2);
+	ecc_code[0] = readb(&nand->nfecc);
+	ecc_code[1] = readb(&nand->nfecc + 1);
+	ecc_code[2] = readb(&nand->nfecc + 2);
 	debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
 	       mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
 
@@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand)
 
 	debugX(1, "board_nand_init()\n");
 
-	writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
 	/* initialize hardware */
 	twrph0 = 3;
@@ -141,10 +141,11 @@ int board_nand_init(struct nand_chip *nand)
 	cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
 	cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 	cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
-	writel(cfg, &nand_reg->NFCONF);
+	writel(cfg, &nand_reg->nfconf);
 
 	/* initialize nand_chip data structure */
-	nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
+	nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
+	nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
 
 	nand->select_chip = NULL;
 
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index 1045cf1ba980ae91d56bf4ddb35728e089e44a28..49a1f5fb49fd8269852ad8a6c138652b4549bc75 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -127,7 +127,7 @@ void bb_miiphy_init(void)
 	int i;
 
 	for (i = 0; i < bb_miiphy_buses_num; i++) {
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 		/* Relocate the hook pointers*/
 		BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
 		BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 001e6eb900701185c46f981aa62c1426ff8e7116..1f021036e5f00040b0a2826664e890d2b92fb78b 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -91,6 +91,9 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
 {
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
 
+	/* Reset hose to make sure its in a clean state */
+	memset(hose, 0, sizeof(struct pci_controller));
+
 	pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 
 	return fsl_is_pci_agent(hose);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index cd64a87fc6d9b200ed805ae1e6f5a7e014180435..848746f1ed2ea4b20a7c5ae012aebc2ed9f42a02 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -139,7 +139,7 @@ void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
  *
  */
 
-static struct pci_controller* hose_head = NULL;
+static struct pci_controller* hose_head;
 
 void pci_register_hose(struct pci_controller* hose)
 {
@@ -640,6 +640,8 @@ void pci_init(void)
 	}
 #endif /* CONFIG_PCI_BOOTDELAY */
 
+	hose_head = NULL;
+
 	/* now call board specific pci_init()... */
 	pci_init_board();
 }
diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c
index 7738a7acaa0c79054d67a835945fdf30a5810cef..25e4a7bcdb8222cb58e457283296176533bb0f79 100644
--- a/drivers/rtc/ftrtc010.c
+++ b/drivers/rtc/ftrtc010.c
@@ -34,6 +34,13 @@ struct ftrtc010 {
 	unsigned int alarm_hour;	/* 0x18 */
 	unsigned int record;		/* 0x1c */
 	unsigned int cr;		/* 0x20 */
+	unsigned int wsec;		/* 0x24 */
+	unsigned int wmin;		/* 0x28 */
+	unsigned int whour;		/* 0x2c */
+	unsigned int wday;		/* 0x30 */
+	unsigned int intr;		/* 0x34 */
+	unsigned int div;		/* 0x38 */
+	unsigned int rev;		/* 0x3c */
 };
 
 /*
@@ -85,7 +92,11 @@ int rtc_get(struct rtc_time *tmp)
 	debug("%s(): record register: %x\n",
 	      __func__, readl(&rtc->record));
 
+#ifdef CONFIG_FTRTC010_PCLK
+	now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT;
+#else /* CONFIG_FTRTC010_EXTCLK */
 	now = ftrtc010_time() + readl(&rtc->record);
+#endif
 
 	to_tm(now, tmp);
 
diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c
index 04de5ca545d52c88780e459bdd785a806d5e822f..7f02f0585ff3fb8890fa52512bbb5b6c4affbf1a 100644
--- a/drivers/rtc/s3c24x0_rtc.c
+++ b/drivers/rtc/s3c24x0_rtc.c
@@ -49,11 +49,11 @@ static inline void SetRTC_Access(RTC_ACCESS a)
 
 	switch (a) {
 	case RTC_ENABLE:
-		writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON);
+		writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon);
 		break;
 
 	case RTC_DISABLE:
-		writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON);
+		writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon);
 		break;
 	}
 }
@@ -71,23 +71,23 @@ int rtc_get(struct rtc_time *tmp)
 
 	/* read RTC registers */
 	do {
-		sec  = readb(&rtc->BCDSEC);
-		min  = readb(&rtc->BCDMIN);
-		hour = readb(&rtc->BCDHOUR);
-		mday = readb(&rtc->BCDDATE);
-		wday = readb(&rtc->BCDDAY);
-		mon  = readb(&rtc->BCDMON);
-		year = readb(&rtc->BCDYEAR);
-	} while (sec != readb(&rtc->BCDSEC));
+		sec  = readb(&rtc->bcdsec);
+		min  = readb(&rtc->bcdmin);
+		hour = readb(&rtc->bcdhour);
+		mday = readb(&rtc->bcddate);
+		wday = readb(&rtc->bcdday);
+		mon  = readb(&rtc->bcdmon);
+		year = readb(&rtc->bcdyear);
+	} while (sec != readb(&rtc->bcdsec));
 
 	/* read ALARM registers */
-	a_sec   = readb(&rtc->ALMSEC);
-	a_min   = readb(&rtc->ALMMIN);
-	a_hour  = readb(&rtc->ALMHOUR);
-	a_date  = readb(&rtc->ALMDATE);
-	a_mon   = readb(&rtc->ALMMON);
-	a_year  = readb(&rtc->ALMYEAR);
-	a_armed = readb(&rtc->RTCALM);
+	a_sec   = readb(&rtc->almsec);
+	a_min   = readb(&rtc->almmin);
+	a_hour  = readb(&rtc->almhour);
+	a_date  = readb(&rtc->almdate);
+	a_mon   = readb(&rtc->almmon);
+	a_year  = readb(&rtc->almyear);
+	a_armed = readb(&rtc->rtcalm);
 
 	/* disable access to RTC registers */
 	SetRTC_Access(RTC_DISABLE);
@@ -145,13 +145,13 @@ int rtc_set(struct rtc_time *tmp)
 	SetRTC_Access(RTC_ENABLE);
 
 	/* write RTC registers */
-	writeb(sec, &rtc->BCDSEC);
-	writeb(min, &rtc->BCDMIN);
-	writeb(hour, &rtc->BCDHOUR);
-	writeb(mday, &rtc->BCDDATE);
-	writeb(wday, &rtc->BCDDAY);
-	writeb(mon, &rtc->BCDMON);
-	writeb(year, &rtc->BCDYEAR);
+	writeb(sec, &rtc->bcdsec);
+	writeb(min, &rtc->bcdmin);
+	writeb(hour, &rtc->bcdhour);
+	writeb(mday, &rtc->bcddate);
+	writeb(wday, &rtc->bcdday);
+	writeb(mon, &rtc->bcdmon);
+	writeb(year, &rtc->bcdyear);
 
 	/* disable access to RTC registers */
 	SetRTC_Access(RTC_DISABLE);
@@ -163,8 +163,8 @@ void rtc_reset(void)
 {
 	struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
 
-	writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON);
-	writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON);
+	writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
+	writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
 }
 
 #endif
diff --git a/drivers/serial/atmel_usart.h b/drivers/serial/atmel_usart.h
index 7cfc2d500cb938bef0043643d107e6b77ea7694f..7e4b2c9c69ed50dac3dc2692514a6a84cd7d6176 100644
--- a/drivers/serial/atmel_usart.h
+++ b/drivers/serial/atmel_usart.h
@@ -42,7 +42,7 @@ typedef struct atmel_usart3 {
 	u32	reserved1;
 	u32	ifr;
 	u32	man;
-	u32	reserved2[54]; // version and PDC not needed
+	u32	reserved2[54]; /* version and PDC not needed */
 } atmel_usart3_t;
 
 /* Bitfields in CR */
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 8a3e30209cfae7857d3ad59925031480f8e4c791..f42b15e45ecc80f8c70c06e9a3471fa1b1694cb0 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -101,7 +101,7 @@ void _serial_setbrg(const int dev_index)
 	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
 	reg = get_PCLK() / (16 * gd->baudrate) - 1;
 
-	writel(reg, &uart->UBRDIV);
+	writel(reg, &uart->ubrdiv);
 	for (i = 0; i < 100; i++)
 		/* Delay */ ;
 }
@@ -131,26 +131,26 @@ static int serial_init_dev(const int dev_index)
 #endif
 
 	/* FIFO enable, Tx/Rx FIFO clear */
-	writel(0x07, &uart->UFCON);
-	writel(0x0, &uart->UMCON);
+	writel(0x07, &uart->ufcon);
+	writel(0x0, &uart->umcon);
 
 	/* Normal,No parity,1 stop,8 bit */
-	writel(0x3, &uart->ULCON);
+	writel(0x3, &uart->ulcon);
 	/*
 	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal,interrupt or polling
 	 */
-	writel(0x245, &uart->UCON);
+	writel(0x245, &uart->ucon);
 
 #ifdef CONFIG_HWFLOW
-	writel(0x1, &uart->UMCON);	/* RTS up */
+	writel(0x1, &uart->umcon);	/* rts up */
 #endif
 
 	/* FIXME: This is sooooooooooooooooooo ugly */
 #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
 	/* we need auto hw flow control on the gsm and gps port */
 	if (dev_index == 0 || dev_index == 1)
-		writel(0x10, &uart->UMCON);
+		writel(0x10, &uart->umcon);
 #endif
 	_serial_setbrg(dev_index);
 
@@ -176,10 +176,10 @@ int _serial_getc(const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
-	while (!(readl(&uart->UTRSTAT) & 0x1))
+	while (!(readl(&uart->utrstat) & 0x1))
 		/* wait for character to arrive */ ;
 
-	return readb(&uart->URXH) & 0xff;
+	return readb(&uart->urxh) & 0xff;
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
@@ -237,15 +237,15 @@ void _serial_putc(const char c, const int dev_index)
 		return;
 #endif
 
-	while (!(readl(&uart->UTRSTAT) & 0x2))
+	while (!(readl(&uart->utrstat) & 0x2))
 		/* wait for room in the tx FIFO */ ;
 
 #ifdef CONFIG_HWFLOW
-	while (hwflow && !(readl(&uart->UMSTAT) & 0x1))
+	while (hwflow && !(readl(&uart->umstat) & 0x1))
 		/* Wait for CTS up */ ;
 #endif
 
-	writeb(c, &uart->UTXH);
+	writeb(c, &uart->utxh);
 
 	/* If \n, also do \r */
 	if (c == '\n')
@@ -272,7 +272,7 @@ int _serial_tstc(const int dev_index)
 {
 	struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
 
-	return readl(&uart->UTRSTAT) & 0x1;
+	return readl(&uart->utrstat) & 0x1;
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 77096643f1f87a01eebab57727926bf5f42eea77..36333c3d49a78d9292c8a82d8c049be679b006cd 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -70,7 +70,11 @@ void serial_setbrg_dev(const int dev_index)
 	val = uclk / baudrate;
 
 	writel(val / 16 - 1, &uart->ubrdiv);
-	writew(udivslot[val % 16], &uart->udivslot);
+
+	if (use_divslot)
+		writew(udivslot[val % 16], &uart->rest.slot);
+	else
+		writeb(val % 16, &uart->rest.value);
 }
 
 /*
diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c
index cf22629b971d95471fdf0480505f3c7105d0d038..f9163a80ed17cbcf912f0e4baf2a9b39fc6705e5 100644
--- a/drivers/usb/gadget/config.c
+++ b/drivers/usb/gadget/config.c
@@ -116,4 +116,3 @@ int usb_gadget_config_buf(
 	cp->bmAttributes |= USB_CONFIG_ATT_ONE;
 	return len;
 }
-
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 7cf3c673ddd702641ce620205a0571a7df90bb94..18964894215f025063f66b69e6e8311ed19b7c34 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -302,4 +302,3 @@ void usb_ep_autoconfig_reset(struct usb_gadget *gadget)
 #endif
 	epnum = 0;
 }
-
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index b22ca90fc6824b92e19c34cea1f69b10d2675777..5a18e035b6ef9f39d1c20becf9dea85e46931ebe 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -1968,4 +1968,3 @@ fail:
 	error("%s failed. error = %d", __func__, status);
 	return status;
 }
-
diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c
index 6e9d1bf0f29b408c34df71834143d9a91cdb84ef..95555cf96b9c3a1f1b52482c54c5ae9830ae3a2a 100644
--- a/drivers/usb/gadget/usbstring.c
+++ b/drivers/usb/gadget/usbstring.c
@@ -137,4 +137,3 @@ usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf)
 	buf[1] = USB_DT_STRING;
 	return buf[0];
 }
-
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index f44fc4e3c4b693117979078adf55d692d83002be..982f96e8b8ff242d7617389f5181abab4238b3fe 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -205,12 +205,12 @@ static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
 	uint32_t result;
 	do {
 		result = ehci_readl(ptr);
+		udelay(5);
 		if (result == ~(uint32_t)0)
 			return -1;
 		result &= mask;
 		if (result == done)
 			return 0;
-		udelay(1);
 		usec--;
 	} while (usec > 0);
 	return -1;
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 047902a0c1c62fed41a3ba1827b95248cf865eee..cff34389295c5d13ce12d8988bdad47ab8c64c0a 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -53,6 +53,10 @@ int ehci_hcd_init(void)
 	hcor = (struct ehci_hcor *)((uint32_t) hccr +
 			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 
+	debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+			(uint32_t)hccr, (uint32_t)hcor,
+			(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
 	return 0;
 }
 
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index d3aa55b4a6c70a40ff6f584b22ca8b482b4d7c4e..945ab64f95119fbf8790813f43a540af2d63d64b 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -175,7 +175,7 @@ struct qTD {
 	uint32_t qt_buffer_hi[5];	/* Appendix B */
 	/* pad struct for 32 byte alignment */
 	uint32_t unused[3];
-} __attribute__ ((aligned (32)));
+};
 
 /* Queue Head (QH). */
 struct QH {
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 6fe2c39bce800cb6eac58008431f8c3a2fb36f10..545ebf4b502322cdecd71ddd2b5cc72ff24f209a 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -76,7 +76,7 @@ void musb_start(void)
  * epinfo	- Pointer to EP configuration table
  * cnt		- Number of entries in the EP conf table.
  */
-void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt)
+void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
 {
 	u16 csr;
 	u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 8f73876f8067ec1f7d8cdced275c6eaa141841a5..a8adcce00fa4ae558cd72944faa7dad4f956ebf1 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -357,7 +357,7 @@ extern struct musb_regs		*musbr;
 
 /* exported functions */
 extern void musb_start(void);
-extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt);
+extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
 extern void write_fifo(u8 ep, u32 length, void *fifo_data);
 extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index f38b279096c31fbfaf5abb161526ffa82eca19c1..8b0c61d642662609057c1a87dbf98850e0ee0888 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -29,7 +29,7 @@
 #define USB_MSC_BBB_GET_MAX_LUN	0xFE
 
 /* Endpoint configuration information */
-static struct musb_epinfo epinfo[3] = {
+static const struct musb_epinfo epinfo[3] = {
 	{MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
 	{MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In  - 512 Bytes */
 	{MUSB_INTR_EP, 0, 64}   /* EP2 - Interrupt IN - 64 Bytes */
@@ -41,7 +41,7 @@ static int rh_devnum;
 static u32 port_status;
 
 /* Device descriptor */
-static u8 root_hub_dev_des[] = {
+static const u8 root_hub_dev_des[] = {
 	0x12,			/*  __u8  bLength; */
 	0x01,			/*  __u8  bDescriptorType; Device */
 	0x00,			/*  __u16 bcdUSB; v1.1 */
@@ -63,7 +63,7 @@ static u8 root_hub_dev_des[] = {
 };
 
 /* Configuration descriptor */
-static u8 root_hub_config_des[] = {
+static const u8 root_hub_config_des[] = {
 	0x09,			/*  __u8  bLength; */
 	0x02,			/*  __u8  bDescriptorType; Configuration */
 	0x19,			/*  __u16 wTotalLength; */
@@ -96,14 +96,14 @@ static u8 root_hub_config_des[] = {
 	0xff			/*  __u8  ep_bInterval; 255 ms */
 };
 
-static unsigned char root_hub_str_index0[] = {
+static const unsigned char root_hub_str_index0[] = {
 	0x04,			/*  __u8  bLength; */
 	0x03,			/*  __u8  bDescriptorType; String-descriptor */
 	0x09,			/*  __u8  lang ID */
 	0x04,			/*  __u8  lang ID */
 };
 
-static unsigned char root_hub_str_index1[] = {
+static const unsigned char root_hub_str_index1[] = {
 	0x1c,			/*  __u8  bLength; */
 	0x03,			/*  __u8  bDescriptorType; String-descriptor */
 	'M',			/*  __u8  Unicode */
@@ -557,7 +557,7 @@ static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 	int len = 0;
 	int stat = 0;
 	u32 datab[4];
-	u8 *data_buf = (u8 *) datab;
+	const u8 *data_buf = (u8 *) datab;
 	u16 bmRType_bReq;
 	u16 wValue;
 	u16 wIndex;
@@ -778,25 +778,27 @@ static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 
 		break;
 
-	case RH_GET_DESCRIPTOR | RH_CLASS:
+	case RH_GET_DESCRIPTOR | RH_CLASS: {
+		u8 *_data_buf = (u8 *) datab;
 		debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
 
-		data_buf[0] = 0x09;	/* min length; */
-		data_buf[1] = 0x29;
-		data_buf[2] = 0x1;	/* 1 port */
-		data_buf[3] = 0x01;	/* per-port power switching */
-		data_buf[3] |= 0x10;	/* no overcurrent reporting */
+		_data_buf[0] = 0x09;	/* min length; */
+		_data_buf[1] = 0x29;
+		_data_buf[2] = 0x1;	/* 1 port */
+		_data_buf[3] = 0x01;	/* per-port power switching */
+		_data_buf[3] |= 0x10;	/* no overcurrent reporting */
 
 		/* Corresponds to data_buf[4-7] */
-		data_buf[4] = 0;
-		data_buf[5] = 5;
-		data_buf[6] = 0;
-		data_buf[7] = 0x02;
-		data_buf[8] = 0xff;
+		_data_buf[4] = 0;
+		_data_buf[5] = 5;
+		_data_buf[6] = 0;
+		_data_buf[7] = 0x02;
+		_data_buf[8] = 0xff;
 
 		len = min_t(unsigned int, leni,
 			    min_t(unsigned int, data_buf[0], wLength));
 		break;
+	}
 
 	case RH_GET_CONFIGURATION:
 		debug("RH_GET_CONFIGURATION\n");
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 4be82e739603d87935b128a6cad7a349e9b6548e..5b7b2612686393eda7b3cc6bcdd2bbc19e90cccb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
+COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
diff --git a/drivers/video/ipu.h b/drivers/video/ipu.h
new file mode 100644
index 0000000000000000000000000000000000000000..d8bc287d84110352f3f5fa04f794502186f2135e
--- /dev/null
+++ b/drivers/video/ipu.h
@@ -0,0 +1,321 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_IPU_H__
+#define __ASM_ARCH_IPU_H__
+
+#include <linux/types.h>
+
+#define IDMA_CHAN_INVALID	0xFF
+#define HIGH_RESOLUTION_WIDTH	1024
+
+struct clk {
+	const char *name;
+	int id;
+	/* Source clock this clk depends on */
+	struct clk *parent;
+	/* Secondary clock to enable/disable with this clock */
+	struct clk *secondary;
+	/* Current clock rate */
+	unsigned long rate;
+	/* Reference count of clock enable/disable */
+	__s8 usecount;
+	/* Register bit position for clock's enable/disable control. */
+	u8 enable_shift;
+	/* Register address for clock's enable/disable control. */
+	void *enable_reg;
+	u32 flags;
+	/*
+	 * Function ptr to recalculate the clock's rate based on parent
+	 * clock's rate
+	 */
+	void (*recalc) (struct clk *);
+	/*
+	 * Function ptr to set the clock to a new rate. The rate must match a
+	 * supported rate returned from round_rate. Leave blank if clock is not
+	* programmable
+	 */
+	int (*set_rate) (struct clk *, unsigned long);
+	/*
+	 * Function ptr to round the requested clock rate to the nearest
+	 * supported rate that is less than or equal to the requested rate.
+	 */
+	unsigned long (*round_rate) (struct clk *, unsigned long);
+	/*
+	 * Function ptr to enable the clock. Leave blank if clock can not
+	 * be gated.
+	 */
+	int (*enable) (struct clk *);
+	/*
+	 * Function ptr to disable the clock. Leave blank if clock can not
+	 * be gated.
+	 */
+	void (*disable) (struct clk *);
+	/* Function ptr to set the parent clock of the clock. */
+	int (*set_parent) (struct clk *, struct clk *);
+};
+
+/*
+ * Enumeration of Synchronous (Memory-less) panel types
+ */
+typedef enum {
+	IPU_PANEL_SHARP_TFT,
+	IPU_PANEL_TFT,
+} ipu_panel_t;
+
+/*  IPU Pixel format definitions */
+#define fourcc(a, b, c, d)\
+	(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
+ * the same used by V4L2 API.
+ */
+
+#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
+#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
+#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
+#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
+
+#define IPU_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')	/*<  8  RGB-3-3-2    */
+#define IPU_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')	/*< 16  RGB-5-5-5    */
+#define IPU_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')	/*< 1 6  RGB-5-6-5   */
+#define IPU_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')	/*< 18  RGB-6-6-6    */
+#define IPU_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')	/*< 18  BGR-6-6-6    */
+#define IPU_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')	/*< 24  BGR-8-8-8    */
+#define IPU_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')	/*< 24  RGB-8-8-8    */
+#define IPU_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')	/*< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')	/*< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')	/*< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')	/*< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')	/*< 32  ABGR-8-8-8-8 */
+
+/* YUV Interleaved Formats */
+#define IPU_PIX_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')	/*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_UYVY    fourcc('U', 'Y', 'V', 'Y')	/*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_Y41P    fourcc('Y', '4', '1', 'P')	/*< 12 YUV 4:1:1 */
+#define IPU_PIX_FMT_YUV444  fourcc('Y', '4', '4', '4')	/*< 24 YUV 4:4:4 */
+
+/* two planes -- one Y, one Cb + Cr interleaved  */
+#define IPU_PIX_FMT_NV12    fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
+
+#define IPU_PIX_FMT_GREY    fourcc('G', 'R', 'E', 'Y')	/*< 8  Greyscale */
+#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9')	/*< 9  YVU 4:1:0 */
+#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9')	/*< 9  YUV 4:1:0 */
+#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2')	/*< 12 YVU 4:2:0 */
+#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0')	/*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2')	/*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6')	/*< 16 YVU 4:2:2 */
+#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*< 16 YUV 4:2:2 */
+
+/*
+ * IPU Driver channels definitions.
+ * Note these are different from IDMA channels
+ */
+#define IPU_MAX_CH	32
+#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
+	((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
+#define _MAKE_ALT_CHAN(ch)		(ch | (IPU_MAX_CH << 24))
+#define IPU_CHAN_ID(ch)			(ch >> 24)
+#define IPU_CHAN_ALT(ch)		(ch & 0x02000000)
+#define IPU_CHAN_ALPHA_IN_DMA(ch)	((uint32_t) (ch >> 6) & 0x3F)
+#define IPU_CHAN_GRAPH_IN_DMA(ch)	((uint32_t) (ch >> 12) & 0x3F)
+#define IPU_CHAN_VIDEO_IN_DMA(ch)	((uint32_t) (ch >> 18) & 0x3F)
+#define IPU_CHAN_OUT_DMA(ch)		((uint32_t) (ch & 0x3F))
+#define NO_DMA 0x3F
+#define ALT	1
+
+/*
+ * Enumeration of IPU logical channels. An IPU logical channel is defined as a
+ * combination of an input (memory to IPU), output (IPU to memory), and/or
+ * secondary input IDMA channels and in some cases an Image Converter task.
+ * Some channels consist of only an input or output.
+ */
+typedef enum {
+	CHAN_NONE = -1,
+
+	MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
+	MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
+	MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
+	MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
+
+	MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
+	MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
+	MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
+	MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
+
+	DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+	DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+
+} ipu_channel_t;
+
+/*
+ * Enumeration of types of buffers for a logical channel.
+ */
+typedef enum {
+	IPU_OUTPUT_BUFFER = 0,	/*< Buffer for output from IPU */
+	IPU_ALPHA_IN_BUFFER = 1,	/*< Buffer for input to IPU */
+	IPU_GRAPH_IN_BUFFER = 2,	/*< Buffer for input to IPU */
+	IPU_VIDEO_IN_BUFFER = 3,	/*< Buffer for input to IPU */
+	IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
+	IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
+} ipu_buffer_t;
+
+#define IPU_PANEL_SERIAL		1
+#define IPU_PANEL_PARALLEL		2
+
+struct ipu_channel {
+	u8 video_in_dma;
+	u8 alpha_in_dma;
+	u8 graph_in_dma;
+	u8 out_dma;
+};
+
+enum ipu_dmfc_type {
+	DMFC_NORMAL = 0,
+	DMFC_HIGH_RESOLUTION_DC,
+	DMFC_HIGH_RESOLUTION_DP,
+	DMFC_HIGH_RESOLUTION_ONLY_DP,
+};
+
+
+/*
+ * Union of initialization parameters for a logical channel.
+ */
+typedef union {
+	struct {
+		uint32_t di;
+		unsigned char interlaced;
+	} mem_dc_sync;
+	struct {
+		uint32_t temp;
+	} mem_sdc_fg;
+	struct {
+		uint32_t di;
+		unsigned char interlaced;
+		uint32_t in_pixel_fmt;
+		uint32_t out_pixel_fmt;
+		unsigned char alpha_chan_en;
+	} mem_dp_bg_sync;
+	struct {
+		uint32_t temp;
+	} mem_sdc_bg;
+	struct {
+		uint32_t di;
+		unsigned char interlaced;
+		uint32_t in_pixel_fmt;
+		uint32_t out_pixel_fmt;
+		unsigned char alpha_chan_en;
+	} mem_dp_fg_sync;
+} ipu_channel_params_t;
+
+/*
+ * Bitfield of Display Interface signal polarities.
+ */
+typedef struct {
+	unsigned datamask_en:1;
+	unsigned ext_clk:1;
+	unsigned interlaced:1;
+	unsigned odd_field_first:1;
+	unsigned clksel_en:1;
+	unsigned clkidle_en:1;
+	unsigned data_pol:1;	/* true = inverted */
+	unsigned clk_pol:1;	/* true = rising edge */
+	unsigned enable_pol:1;
+	unsigned Hsync_pol:1;	/* true = active high */
+	unsigned Vsync_pol:1;
+} ipu_di_signal_cfg_t;
+
+typedef enum {
+	RGB,
+	YCbCr,
+	YUV
+} ipu_color_space_t;
+
+/* Common IPU API */
+int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
+void ipu_uninit_channel(ipu_channel_t channel);
+
+int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+				uint32_t u_offset, uint32_t v_offset);
+
+int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+				  uint32_t bufNum, dma_addr_t phyaddr);
+
+int32_t ipu_is_channel_busy(ipu_channel_t channel);
+void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum);
+int32_t ipu_enable_channel(ipu_channel_t channel);
+int32_t ipu_disable_channel(ipu_channel_t channel);
+
+int32_t ipu_init_sync_panel(int disp,
+			    uint32_t pixel_clk,
+			    uint16_t width, uint16_t height,
+			    uint32_t pixel_fmt,
+			    uint16_t h_start_width, uint16_t h_sync_width,
+			    uint16_t h_end_width, uint16_t v_start_width,
+			    uint16_t v_sync_width, uint16_t v_end_width,
+			    uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
+
+int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
+				  uint8_t alpha);
+int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
+			       uint32_t colorKey);
+
+uint32_t bytes_per_pixel(uint32_t fmt);
+
+void clk_enable(struct clk *clk);
+void clk_disable(struct clk *clk);
+u32 clk_get_rate(struct clk *clk);
+int clk_set_rate(struct clk *clk, unsigned long rate);
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+int clk_get_usecount(struct clk *clk);
+struct clk *clk_get_parent(struct clk *clk);
+
+void ipu_dump_registers(void);
+int ipu_probe(void);
+
+void ipu_dmfc_init(int dmfc_type, int first);
+void ipu_init_dc_mappings(void);
+void ipu_dmfc_set_wait4eot(int dma_chan, int width);
+void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
+void ipu_dc_uninit(int dc_chan);
+void ipu_dp_dc_enable(ipu_channel_t channel);
+int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
+		 uint32_t out_pixel_fmt);
+void ipu_dp_uninit(ipu_channel_t channel);
+void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
+ipu_color_space_t format_to_colorspace(uint32_t fmt);
+
+#endif
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
new file mode 100644
index 0000000000000000000000000000000000000000..9d20c864bac8adc70cd1acb1dcf2538d71bcaebd
--- /dev/null
+++ b/drivers/video/ipu_common.c
@@ -0,0 +1,1183 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+#include <common.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include "ipu.h"
+#include "ipu_regs.h"
+
+extern struct mxc_ccm_reg *mxc_ccm;
+extern u32 *ipu_cpmem_base;
+
+struct ipu_ch_param_word {
+	uint32_t data[5];
+	uint32_t res[3];
+};
+
+struct ipu_ch_param {
+	struct ipu_ch_param_word word[2];
+};
+
+#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
+
+#define _param_word(base, w) \
+	(((struct ipu_ch_param *)(base))->word[(w)].data)
+
+#define ipu_ch_param_set_field(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	_param_word(base, w)[i] |= (v) << off; \
+	if (((bit) + (size) - 1) / 32 > i) { \
+		_param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
+	} \
+}
+
+#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	u32 temp = _param_word(base, w)[i]; \
+	temp &= ~(mask << off); \
+	_param_word(base, w)[i] = temp | (v) << off; \
+	if (((bit) + (size) - 1) / 32 > i) { \
+		temp = _param_word(base, w)[i + 1]; \
+		temp &= ~(mask >> (32 - off)); \
+		_param_word(base, w)[i + 1] = \
+			temp | ((v) >> (off ? (32 - off) : 0)); \
+	} \
+}
+
+#define ipu_ch_param_read_field(base, w, bit, size) ({ \
+	u32 temp2; \
+	int i = (bit) / 32; \
+	int off = (bit) % 32; \
+	u32 mask = (1UL << size) - 1; \
+	u32 temp1 = _param_word(base, w)[i]; \
+	temp1 = mask & (temp1 >> off); \
+	if (((bit)+(size) - 1) / 32 > i) { \
+		temp2 = _param_word(base, w)[i + 1]; \
+		temp2 &= mask >> (off ? (32 - off) : 0); \
+		temp1 |= temp2 << (off ? (32 - off) : 0); \
+	} \
+	temp1; \
+})
+
+
+void clk_enable(struct clk *clk)
+{
+	if (clk) {
+		if (clk->usecount++ == 0) {
+			clk->enable(clk);
+		}
+	}
+}
+
+void clk_disable(struct clk *clk)
+{
+	if (clk) {
+		if (!(--clk->usecount)) {
+			if (clk->disable)
+				clk->disable(clk);
+		}
+	}
+}
+
+int clk_get_usecount(struct clk *clk)
+{
+	if (clk == NULL)
+		return 0;
+
+	return clk->usecount;
+}
+
+u32 clk_get_rate(struct clk *clk)
+{
+	if (!clk)
+		return 0;
+
+	return clk->rate;
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+	if (!clk)
+		return 0;
+
+	return clk->parent;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk && clk->set_rate)
+		clk->set_rate(clk, rate);
+	return clk->rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk == NULL || !clk->round_rate)
+		return 0;
+
+	return clk->round_rate(clk, rate);
+}
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	clk->parent = parent;
+	if (clk->set_parent)
+		return clk->set_parent(clk, parent);
+	return 0;
+}
+
+static int clk_ipu_enable(struct clk *clk)
+{
+	u32 reg;
+
+	reg = __raw_readl(clk->enable_reg);
+	reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
+	__raw_writel(reg, clk->enable_reg);
+
+	/* Handshake with IPU when certain clock rates are changed. */
+	reg = __raw_readl(&mxc_ccm->ccdr);
+	reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+	__raw_writel(reg, &mxc_ccm->ccdr);
+
+	/* Handshake with IPU when LPM is entered as its enabled. */
+	reg = __raw_readl(&mxc_ccm->clpcr);
+	reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+	__raw_writel(reg, &mxc_ccm->clpcr);
+
+	return 0;
+}
+
+static void clk_ipu_disable(struct clk *clk)
+{
+	u32 reg;
+
+	reg = __raw_readl(clk->enable_reg);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
+	__raw_writel(reg, clk->enable_reg);
+
+	/*
+	 * No handshake with IPU whe dividers are changed
+	 * as its not enabled.
+	 */
+	reg = __raw_readl(&mxc_ccm->ccdr);
+	reg |= MXC_CCM_CCDR_IPU_HS_MASK;
+	__raw_writel(reg, &mxc_ccm->ccdr);
+
+	/* No handshake with IPU when LPM is entered as its not enabled. */
+	reg = __raw_readl(&mxc_ccm->clpcr);
+	reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+	__raw_writel(reg, &mxc_ccm->clpcr);
+}
+
+
+static struct clk ipu_clk = {
+	.name = "ipu_clk",
+	.rate = 133000000,
+	.enable_reg = (u32 *)(MXC_CCM_BASE +
+		offsetof(struct mxc_ccm_reg, CCGR5)),
+	.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+	.enable = clk_ipu_enable,
+	.disable = clk_ipu_disable,
+	.usecount = 0,
+};
+
+/* Globals */
+struct clk *g_ipu_clk;
+unsigned char g_ipu_clk_enabled;
+struct clk *g_di_clk[2];
+struct clk *g_pixel_clk[2];
+unsigned char g_dc_di_assignment[10];
+uint32_t g_channel_init_mask;
+uint32_t g_channel_enable_mask;
+
+static int ipu_dc_use_count;
+static int ipu_dp_use_count;
+static int ipu_dmfc_use_count;
+static int ipu_di_use_count[2];
+
+u32 *ipu_cpmem_base;
+u32 *ipu_dc_tmpl_reg;
+
+/* Static functions */
+
+static inline void ipu_ch_param_set_high_priority(uint32_t ch)
+{
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
+};
+
+static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
+{
+	return ((uint32_t) ch >> (6 * type)) & 0x3F;
+};
+
+/* Either DP BG or DP FG can be graphic window */
+static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
+{
+	return (dma_chan == 23 || dma_chan == 27);
+}
+
+static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
+{
+	return ((dma_chan >= 23) && (dma_chan <= 29));
+}
+
+
+static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
+					    dma_addr_t phyaddr)
+{
+	ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
+			       phyaddr / 8);
+};
+
+#define idma_is_valid(ch)	(ch != NO_DMA)
+#define idma_mask(ch)		(idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
+#define idma_is_set(reg, dma)	(__raw_readl(reg(dma)) & idma_mask(dma))
+
+static void ipu_pixel_clk_recalc(struct clk *clk)
+{
+	u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
+	if (div == 0)
+		clk->rate = 0;
+	else
+		clk->rate = (clk->parent->rate * 16) / div;
+}
+
+static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
+	unsigned long rate)
+{
+	u32 div, div1;
+	u32 tmp;
+	/*
+	 * Calculate divider
+	 * Fractional part is 4 bits,
+	 * so simply multiply by 2^4 to get fractional part.
+	 */
+	tmp = (clk->parent->rate * 16);
+	div = tmp / rate;
+
+	if (div < 0x10)            /* Min DI disp clock divider is 1 */
+		div = 0x10;
+	if (div & ~0xFEF)
+		div &= 0xFF8;
+	else {
+		div1 = div & 0xFE0;
+		if ((tmp/div1 - tmp/div) < rate / 4)
+			div = div1;
+		else
+			div &= 0xFF8;
+	}
+	return (clk->parent->rate * 16) / div;
+}
+
+static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 div = (clk->parent->rate * 16) / rate;
+
+	__raw_writel(div, DI_BS_CLKGEN0(clk->id));
+
+	/* Setup pixel clock timing */
+	__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
+
+	clk->rate = (clk->parent->rate * 16) / div;
+	return 0;
+}
+
+static int ipu_pixel_clk_enable(struct clk *clk)
+{
+	u32 disp_gen = __raw_readl(IPU_DISP_GEN);
+	disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
+	__raw_writel(disp_gen, IPU_DISP_GEN);
+
+	return 0;
+}
+
+static void ipu_pixel_clk_disable(struct clk *clk)
+{
+	u32 disp_gen = __raw_readl(IPU_DISP_GEN);
+	disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
+	__raw_writel(disp_gen, IPU_DISP_GEN);
+
+}
+
+static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
+
+	if (parent == g_ipu_clk)
+		di_gen &= ~DI_GEN_DI_CLK_EXT;
+	else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
+		di_gen |= DI_GEN_DI_CLK_EXT;
+	else
+		return -EINVAL;
+
+	__raw_writel(di_gen, DI_GENERAL(clk->id));
+	ipu_pixel_clk_recalc(clk);
+	return 0;
+}
+
+static struct clk pixel_clk[] = {
+	{
+	.name = "pixel_clk",
+	.id = 0,
+	.recalc = ipu_pixel_clk_recalc,
+	.set_rate = ipu_pixel_clk_set_rate,
+	.round_rate = ipu_pixel_clk_round_rate,
+	.set_parent = ipu_pixel_clk_set_parent,
+	.enable = ipu_pixel_clk_enable,
+	.disable = ipu_pixel_clk_disable,
+	.usecount = 0,
+	},
+	{
+	.name = "pixel_clk",
+	.id = 1,
+	.recalc = ipu_pixel_clk_recalc,
+	.set_rate = ipu_pixel_clk_set_rate,
+	.round_rate = ipu_pixel_clk_round_rate,
+	.set_parent = ipu_pixel_clk_set_parent,
+	.enable = ipu_pixel_clk_enable,
+	.disable = ipu_pixel_clk_disable,
+	.usecount = 0,
+	},
+};
+
+/*
+ * This function resets IPU
+ */
+void ipu_reset(void)
+{
+	u32 *reg;
+	u32 value;
+
+	reg = (u32 *)SRC_BASE_ADDR;
+	value = __raw_readl(reg);
+	value = value | SW_IPU_RST;
+	__raw_writel(value, reg);
+}
+
+/*
+ * This function is called by the driver framework to initialize the IPU
+ * hardware.
+ *
+ * @param	dev	The device structure for the IPU passed in by the
+ *			driver framework.
+ *
+ * @return      Returns 0 on success or negative error code on error
+ */
+int ipu_probe(void)
+{
+	unsigned long ipu_base;
+	u32 temp;
+
+	u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
+	u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
+
+	 __raw_writel(0xF00, reg_hsc_mcd);
+
+	/* CSI mode reserved*/
+	temp = __raw_readl(reg_hsc_mxt_conf);
+	 __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
+
+	temp = __raw_readl(reg_hsc_mxt_conf);
+	__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
+
+	ipu_base = IPU_CTRL_BASE_ADDR;
+	ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
+	ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
+
+	g_pixel_clk[0] = &pixel_clk[0];
+	g_pixel_clk[1] = &pixel_clk[1];
+
+	g_ipu_clk = &ipu_clk;
+	debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
+
+	ipu_reset();
+
+	clk_set_parent(g_pixel_clk[0], g_ipu_clk);
+	clk_set_parent(g_pixel_clk[1], g_ipu_clk);
+	clk_enable(g_ipu_clk);
+
+	g_di_clk[0] = NULL;
+	g_di_clk[1] = NULL;
+
+	__raw_writel(0x807FFFFF, IPU_MEM_RST);
+	while (__raw_readl(IPU_MEM_RST) & 0x80000000)
+		;
+
+	ipu_init_dc_mappings();
+
+	__raw_writel(0, IPU_INT_CTRL(5));
+	__raw_writel(0, IPU_INT_CTRL(6));
+	__raw_writel(0, IPU_INT_CTRL(9));
+	__raw_writel(0, IPU_INT_CTRL(10));
+
+	/* DMFC Init */
+	ipu_dmfc_init(DMFC_NORMAL, 1);
+
+	/* Set sync refresh channels as high priority */
+	__raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
+
+	/* Set MCU_T to divide MCU access window into 2 */
+	__raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
+
+	clk_disable(g_ipu_clk);
+
+	return 0;
+}
+
+void ipu_dump_registers(void)
+{
+	debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
+	debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
+	debug("IDMAC_CHA_EN1 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_EN(0)));
+	debug("IDMAC_CHA_EN2 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_EN(32)));
+	debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_PRI(0)));
+	debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
+	       __raw_readl(IDMAC_CHA_PRI(32)));
+	debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
+	       __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
+	debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
+	       __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
+	debug("DMFC_WR_CHAN = \t0x%08X\n",
+	       __raw_readl(DMFC_WR_CHAN));
+	debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
+	       __raw_readl(DMFC_WR_CHAN_DEF));
+	debug("DMFC_DP_CHAN = \t0x%08X\n",
+	       __raw_readl(DMFC_DP_CHAN));
+	debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
+	       __raw_readl(DMFC_DP_CHAN_DEF));
+	debug("DMFC_IC_CTRL = \t0x%08X\n",
+	       __raw_readl(DMFC_IC_CTRL));
+	debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_PROC_FLOW1));
+	debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_PROC_FLOW2));
+	debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_PROC_FLOW3));
+	debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
+	       __raw_readl(IPU_FS_DISP_FLOW1));
+}
+
+/*
+ * This function is called to initialize a logical IPU channel.
+ *
+ * @param       channel Input parameter for the logical channel ID to init.
+ *
+ * @param       params  Input parameter containing union of channel
+ *                      initialization parameters.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
+{
+	int ret = 0;
+	uint32_t ipu_conf;
+
+	debug("init channel = %d\n", IPU_CHAN_ID(channel));
+
+	if (g_ipu_clk_enabled == 0) {
+		g_ipu_clk_enabled = 1;
+		clk_enable(g_ipu_clk);
+	}
+
+
+	if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
+		printf("Warning: channel already initialized %d\n",
+			IPU_CHAN_ID(channel));
+	}
+
+	ipu_conf = __raw_readl(IPU_CONF);
+
+	switch (channel) {
+	case MEM_DC_SYNC:
+		if (params->mem_dc_sync.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		g_dc_di_assignment[1] = params->mem_dc_sync.di;
+		ipu_dc_init(1, params->mem_dc_sync.di,
+			     params->mem_dc_sync.interlaced);
+		ipu_di_use_count[params->mem_dc_sync.di]++;
+		ipu_dc_use_count++;
+		ipu_dmfc_use_count++;
+		break;
+	case MEM_BG_SYNC:
+		if (params->mem_dp_bg_sync.di > 1) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
+		ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
+			     params->mem_dp_bg_sync.out_pixel_fmt);
+		ipu_dc_init(5, params->mem_dp_bg_sync.di,
+			     params->mem_dp_bg_sync.interlaced);
+		ipu_di_use_count[params->mem_dp_bg_sync.di]++;
+		ipu_dc_use_count++;
+		ipu_dp_use_count++;
+		ipu_dmfc_use_count++;
+		break;
+	case MEM_FG_SYNC:
+		ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
+			     params->mem_dp_fg_sync.out_pixel_fmt);
+
+		ipu_dc_use_count++;
+		ipu_dp_use_count++;
+		ipu_dmfc_use_count++;
+		break;
+	default:
+		printf("Missing channel initialization\n");
+		break;
+	}
+
+	/* Enable IPU sub module */
+	g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
+	if (ipu_dc_use_count == 1)
+		ipu_conf |= IPU_CONF_DC_EN;
+	if (ipu_dp_use_count == 1)
+		ipu_conf |= IPU_CONF_DP_EN;
+	if (ipu_dmfc_use_count == 1)
+		ipu_conf |= IPU_CONF_DMFC_EN;
+	if (ipu_di_use_count[0] == 1) {
+		ipu_conf |= IPU_CONF_DI0_EN;
+	}
+	if (ipu_di_use_count[1] == 1) {
+		ipu_conf |= IPU_CONF_DI1_EN;
+	}
+
+	__raw_writel(ipu_conf, IPU_CONF);
+
+err:
+	return ret;
+}
+
+/*
+ * This function is called to uninitialize a logical IPU channel.
+ *
+ * @param       channel Input parameter for the logical channel ID to uninit.
+ */
+void ipu_uninit_channel(ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t in_dma, out_dma = 0;
+	uint32_t ipu_conf;
+
+	if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+		debug("Channel already uninitialized %d\n",
+			IPU_CHAN_ID(channel));
+		return;
+	}
+
+	/*
+	 * Make sure channel is disabled
+	 * Get input and output dma channels
+	 */
+	in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
+	    idma_is_set(IDMAC_CHA_EN, out_dma)) {
+		printf(
+			"Channel %d is not disabled, disable first\n",
+			IPU_CHAN_ID(channel));
+		return;
+	}
+
+	ipu_conf = __raw_readl(IPU_CONF);
+
+	/* Reset the double buffer */
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
+	__raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
+	__raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
+
+	switch (channel) {
+	case MEM_DC_SYNC:
+		ipu_dc_uninit(1);
+		ipu_di_use_count[g_dc_di_assignment[1]]--;
+		ipu_dc_use_count--;
+		ipu_dmfc_use_count--;
+		break;
+	case MEM_BG_SYNC:
+		ipu_dp_uninit(channel);
+		ipu_dc_uninit(5);
+		ipu_di_use_count[g_dc_di_assignment[5]]--;
+		ipu_dc_use_count--;
+		ipu_dp_use_count--;
+		ipu_dmfc_use_count--;
+		break;
+	case MEM_FG_SYNC:
+		ipu_dp_uninit(channel);
+		ipu_dc_use_count--;
+		ipu_dp_use_count--;
+		ipu_dmfc_use_count--;
+		break;
+	default:
+		break;
+	}
+
+	g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+	if (ipu_dc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DC_EN;
+	if (ipu_dp_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DP_EN;
+	if (ipu_dmfc_use_count == 0)
+		ipu_conf &= ~IPU_CONF_DMFC_EN;
+	if (ipu_di_use_count[0] == 0) {
+		ipu_conf &= ~IPU_CONF_DI0_EN;
+	}
+	if (ipu_di_use_count[1] == 0) {
+		ipu_conf &= ~IPU_CONF_DI1_EN;
+	}
+
+	__raw_writel(ipu_conf, IPU_CONF);
+
+	if (ipu_conf == 0) {
+		clk_disable(g_ipu_clk);
+		g_ipu_clk_enabled = 0;
+	}
+
+}
+
+static inline void ipu_ch_param_dump(int ch)
+{
+#ifdef DEBUG
+	struct ipu_ch_param *p = ipu_ch_param_addr(ch);
+	debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
+		 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
+		 p->word[0].data[3], p->word[0].data[4]);
+	debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
+		 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
+		 p->word[1].data[3], p->word[1].data[4]);
+	debug("PFS 0x%x, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
+	debug("BPP 0x%x, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
+	debug("NPB 0x%x\n",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
+
+	debug("FW %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
+	debug("FH %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
+	debug("Stride %d\n",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
+
+	debug("Width0 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
+	debug("Width1 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
+	debug("Width2 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
+	debug("Width3 %d+1, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
+	debug("Offset0 %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
+	debug("Offset1 %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
+	debug("Offset2 %d, ",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
+	debug("Offset3 %d\n",
+		 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
+#endif
+}
+
+static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
+					      int red_width, int red_offset,
+					      int green_width, int green_offset,
+					      int blue_width, int blue_offset,
+					      int alpha_width, int alpha_offset)
+{
+	/* Setup red width and offset */
+	ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
+	ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
+	/* Setup green width and offset */
+	ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
+	ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
+	/* Setup blue width and offset */
+	ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
+	ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
+	/* Setup alpha width and offset */
+	ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
+	ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
+}
+
+static void ipu_ch_param_init(int ch,
+			      uint32_t pixel_fmt, uint32_t width,
+			      uint32_t height, uint32_t stride,
+			      uint32_t u, uint32_t v,
+			      uint32_t uv_stride, dma_addr_t addr0,
+			      dma_addr_t addr1)
+{
+	uint32_t u_offset = 0;
+	uint32_t v_offset = 0;
+	struct ipu_ch_param params;
+
+	memset(&params, 0, sizeof(params));
+
+	ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
+
+	if ((ch == 8) || (ch == 9) || (ch == 10)) {
+		ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
+		ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
+	} else {
+		ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
+		ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
+	}
+
+	ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
+	ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
+
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_GENERIC:
+		/*Represents 8-bit Generic data */
+		ipu_ch_param_set_field(&params, 0, 107, 3, 5);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 6);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 63);	/* burst size */
+
+		break;
+	case IPU_PIX_FMT_GENERIC_32:
+		/*Represents 32-bit Generic data */
+		break;
+	case IPU_PIX_FMT_RGB565:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
+		break;
+	case IPU_PIX_FMT_BGR24:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 1);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 19);	/* burst size */
+
+		ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
+		break;
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_YUV444:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 1);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 19);	/* burst size */
+
+		ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
+		break;
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_BGR32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
+		break;
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_RGB32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+
+		ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
+		break;
+	case IPU_PIX_FMT_ABGR32:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 0);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 7);	/* pix format */
+
+		ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
+		break;
+	case IPU_PIX_FMT_UYVY:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 0xA);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 15);	/* burst size */
+		break;
+	case IPU_PIX_FMT_YUYV:
+		ipu_ch_param_set_field(&params, 0, 107, 3, 3);	/* bits/pixel */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 0x8);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		break;
+	case IPU_PIX_FMT_YUV420P2:
+	case IPU_PIX_FMT_YUV420P:
+		ipu_ch_param_set_field(&params, 1, 85, 4, 2);	/* pix format */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = stride * height;
+		v_offset = u_offset + (uv_stride * height / 2);
+		/* burst size */
+		if ((ch == 8) || (ch == 9) || (ch == 10)) {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 15);
+			uv_stride = uv_stride*2;
+		} else {
+			ipu_ch_param_set_field(&params, 1, 78, 7, 31);
+		}
+		break;
+	case IPU_PIX_FMT_YVU422P:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 1);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		v_offset = (v == 0) ? stride * height : v;
+		u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
+		break;
+	case IPU_PIX_FMT_YUV422P:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 1);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+
+		if (uv_stride < stride / 2)
+			uv_stride = stride / 2;
+
+		u_offset = (u == 0) ? stride * height : u;
+		v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
+		break;
+	case IPU_PIX_FMT_NV12:
+		/* BPP & pixel format */
+		ipu_ch_param_set_field(&params, 1, 85, 4, 4);	/* pix format */
+		ipu_ch_param_set_field(&params, 1, 78, 7, 31);	/* burst size */
+		uv_stride = stride;
+		u_offset = (u == 0) ? stride * height : u;
+		break;
+	default:
+		puts("mxc ipu: unimplemented pixel format\n");
+		break;
+	}
+
+
+	if (uv_stride)
+		ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
+
+	/* Get the uv offset from user when need cropping */
+	if (u || v) {
+		u_offset = u;
+		v_offset = v;
+	}
+
+	/* UBO and VBO are 22-bit */
+	if (u_offset/8 > 0x3fffff)
+		puts("The value of U offset exceeds IPU limitation\n");
+	if (v_offset/8 > 0x3fffff)
+		puts("The value of V offset exceeds IPU limitation\n");
+
+	ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
+	ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
+
+	debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
+	memcpy(ipu_ch_param_addr(ch), &params, sizeof(params));
+};
+
+/*
+ * This function is called to initialize a buffer for logical IPU channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to initialize.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           Input parameter for width of buffer in pixels.
+ *
+ * @param       height          Input parameter for height of buffer in pixels.
+ *
+ * @param       stride          Input parameter for stride length of buffer
+ *                              in pixels.
+ *
+ * @param       phyaddr_0       Input parameter buffer 0 physical address.
+ *
+ * @param       phyaddr_1       Input parameter buffer 1 physical address.
+ *                              Setting this to a value other than NULL enables
+ *                              double buffering mode.
+ *
+ * @param       u		private u offset for additional cropping,
+ *				zero if not used.
+ *
+ * @param       v		private v offset for additional cropping,
+ *				zero if not used.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
+				uint32_t pixel_fmt,
+				uint16_t width, uint16_t height,
+				uint32_t stride,
+				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+				uint32_t u, uint32_t v)
+{
+	uint32_t reg;
+	uint32_t dma_chan;
+
+	dma_chan = channel_2_dma(channel, type);
+	if (!idma_is_valid(dma_chan))
+		return -EINVAL;
+
+	if (stride < width * bytes_per_pixel(pixel_fmt))
+		stride = width * bytes_per_pixel(pixel_fmt);
+
+	if (stride % 4) {
+		printf(
+			"Stride not 32-bit aligned, stride = %d\n", stride);
+		return -EINVAL;
+	}
+	/* Build parameter memory data for DMA channel */
+	ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
+			   phyaddr_0, phyaddr_1);
+
+	if (ipu_is_dmfc_chan(dma_chan)) {
+		ipu_dmfc_set_wait4eot(dma_chan, width);
+	}
+
+	if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
+		ipu_ch_param_set_high_priority(dma_chan);
+
+	ipu_ch_param_dump(dma_chan);
+
+	reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
+	if (phyaddr_1)
+		reg |= idma_mask(dma_chan);
+	else
+		reg &= ~idma_mask(dma_chan);
+	__raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
+
+	/* Reset to buffer 0 */
+	__raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
+
+	return 0;
+}
+
+/*
+ * This function enables a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_enable_channel(ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t in_dma;
+	uint32_t out_dma;
+
+	if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
+		printf("Warning: channel already enabled %d\n",
+			IPU_CHAN_ID(channel));
+	}
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	if (idma_is_valid(in_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(in_dma));
+		__raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+	}
+	if (idma_is_valid(out_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(out_dma));
+		__raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+	}
+
+	if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
+	    (channel == MEM_FG_SYNC))
+		ipu_dp_dc_enable(channel);
+
+	g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
+
+	return 0;
+}
+
+/*
+ * This function clear buffer ready for a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       type            Input parameter which buffer to clear.
+ *
+ * @param       bufNum          Input parameter for which buffer number clear
+ *				ready state.
+ *
+ */
+void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
+		uint32_t bufNum)
+{
+	uint32_t dma_ch = channel_2_dma(channel, type);
+
+	if (!idma_is_valid(dma_ch))
+		return;
+
+	__raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
+	if (bufNum == 0) {
+		if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
+			__raw_writel(idma_mask(dma_ch),
+					IPU_CHA_BUF0_RDY(dma_ch));
+		}
+	} else {
+		if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
+			__raw_writel(idma_mask(dma_ch),
+					IPU_CHA_BUF1_RDY(dma_ch));
+		}
+	}
+	__raw_writel(0x0, IPU_GPR); /* write one to set */
+}
+
+/*
+ * This function disables a logical channel.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       wait_for_stop   Flag to set whether to wait for channel end
+ *                              of frame or return immediately.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int32_t ipu_disable_channel(ipu_channel_t channel)
+{
+	uint32_t reg;
+	uint32_t in_dma;
+	uint32_t out_dma;
+
+	if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
+		debug("Channel already disabled %d\n",
+			IPU_CHAN_ID(channel));
+		return 0;
+	}
+
+	/* Get input and output dma channels */
+	out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
+	in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
+
+	if ((idma_is_valid(in_dma) &&
+		!idma_is_set(IDMAC_CHA_EN, in_dma))
+		&& (idma_is_valid(out_dma) &&
+		!idma_is_set(IDMAC_CHA_EN, out_dma)))
+		return -EINVAL;
+
+	if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
+	    (channel == MEM_DC_SYNC)) {
+		ipu_dp_dc_disable(channel, 0);
+	}
+
+	/* Disable DMA channel(s) */
+	if (idma_is_valid(in_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(in_dma));
+		__raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
+		__raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
+	}
+	if (idma_is_valid(out_dma)) {
+		reg = __raw_readl(IDMAC_CHA_EN(out_dma));
+		__raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
+		__raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
+	}
+
+	g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
+
+	/* Set channel buffers NOT to be ready */
+	if (idma_is_valid(in_dma)) {
+		ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
+		ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
+	}
+	if (idma_is_valid(out_dma)) {
+		ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
+		ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
+	}
+
+	return 0;
+}
+
+uint32_t bytes_per_pixel(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_GENERIC:	/*generic data */
+	case IPU_PIX_FMT_RGB332:
+	case IPU_PIX_FMT_YUV420P:
+	case IPU_PIX_FMT_YUV422P:
+		return 1;
+		break;
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_YUYV:
+	case IPU_PIX_FMT_UYVY:
+		return 2;
+		break;
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+		return 3;
+		break;
+	case IPU_PIX_FMT_GENERIC_32:	/*generic data */
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_ABGR32:
+		return 4;
+		break;
+	default:
+		return 1;
+		break;
+	}
+	return 0;
+}
+
+ipu_color_space_t format_to_colorspace(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_RGB666:
+	case IPU_PIX_FMT_RGB565:
+	case IPU_PIX_FMT_BGR24:
+	case IPU_PIX_FMT_RGB24:
+	case IPU_PIX_FMT_BGR32:
+	case IPU_PIX_FMT_BGRA32:
+	case IPU_PIX_FMT_RGB32:
+	case IPU_PIX_FMT_RGBA32:
+	case IPU_PIX_FMT_ABGR32:
+	case IPU_PIX_FMT_LVDS666:
+	case IPU_PIX_FMT_LVDS888:
+		return RGB;
+		break;
+
+	default:
+		return YCbCr;
+		break;
+	}
+	return RGB;
+}
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
new file mode 100644
index 0000000000000000000000000000000000000000..11cf98d3d5ace6d76b2179b9f5c28f6a4261b972
--- /dev/null
+++ b/drivers/video/ipu_disp.c
@@ -0,0 +1,1359 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include "ipu.h"
+#include "ipu_regs.h"
+
+enum csc_type_t {
+	RGB2YUV = 0,
+	YUV2RGB,
+	RGB2RGB,
+	YUV2YUV,
+	CSC_NONE,
+	CSC_NUM
+};
+
+struct dp_csc_param_t {
+	int mode;
+	void *coeff;
+};
+
+#define SYNC_WAVE 0
+
+/* DC display ID assignments */
+#define DC_DISP_ID_SYNC(di)	(di)
+#define DC_DISP_ID_SERIAL	2
+#define DC_DISP_ID_ASYNC	3
+
+int dmfc_type_setup;
+static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
+int g_di1_tvout;
+
+extern struct clk *g_ipu_clk;
+extern struct clk *g_di_clk[2];
+extern struct clk *g_pixel_clk[2];
+
+extern unsigned char g_ipu_clk_enabled;
+extern unsigned char g_dc_di_assignment[];
+
+void ipu_dmfc_init(int dmfc_type, int first)
+{
+	u32 dmfc_wr_chan, dmfc_dp_chan;
+
+	if (first) {
+		if (dmfc_type_setup > dmfc_type)
+			dmfc_type = dmfc_type_setup;
+		else
+			dmfc_type_setup = dmfc_type;
+
+		/* disable DMFC-IC channel*/
+		__raw_writel(0x2, DMFC_IC_CTRL);
+	} else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
+		printf("DMFC high resolution has set, will not change\n");
+		return;
+	} else
+		dmfc_type_setup = dmfc_type;
+
+	if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
+		/* 1 - segment 0~3;
+		 * 5B - segement 4, 5;
+		 * 5F - segement 6, 7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000088;
+		dmfc_dp_chan = 0x00009694;
+		dmfc_size_28 = 256 * 4;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 128 * 4;
+		dmfc_size_23 = 128 * 4;
+	} else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
+		/* 1 - segment 0, 1;
+		 * 5B - segement 2~5;
+		 * 5F - segement 6,7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000090;
+		dmfc_dp_chan = 0x0000968a;
+		dmfc_size_28 = 128 * 4;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 128 * 4;
+		dmfc_size_23 = 256 * 4;
+	} else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
+		/* 5B - segement 0~3;
+		 * 5F - segement 4~7;
+		 * 1, 1C, 2C and 6B, 6F unused;
+		 */
+		debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
+		dmfc_wr_chan = 0x00000000;
+		dmfc_dp_chan = 0x00008c88;
+		dmfc_size_28 = 0;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 256 * 4;
+		dmfc_size_23 = 256 * 4;
+	} else {
+		/* 1 - segment 0, 1;
+		 * 5B - segement 4, 5;
+		 * 5F - segement 6, 7;
+		 * 1C, 2C and 6B, 6F unused;
+		 */
+		debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
+		dmfc_wr_chan = 0x00000090;
+		dmfc_dp_chan = 0x00009694;
+		dmfc_size_28 = 128 * 4;
+		dmfc_size_29 = 0;
+		dmfc_size_24 = 0;
+		dmfc_size_27 = 128 * 4;
+		dmfc_size_23 = 128 * 4;
+	}
+	__raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
+	__raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
+	__raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
+	/* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
+	__raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
+}
+
+void ipu_dmfc_set_wait4eot(int dma_chan, int width)
+{
+	u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
+
+	if (width >= HIGH_RESOLUTION_WIDTH) {
+		if (dma_chan == 23)
+			ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
+		else if (dma_chan == 28)
+			ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
+	}
+
+	if (dma_chan == 23) { /*5B*/
+		if (dmfc_size_23 / width > 3)
+			dmfc_gen1 |= 1UL << 20;
+		else
+			dmfc_gen1 &= ~(1UL << 20);
+	} else if (dma_chan == 24) { /*6B*/
+		if (dmfc_size_24 / width > 1)
+			dmfc_gen1 |= 1UL << 22;
+		else
+			dmfc_gen1 &= ~(1UL << 22);
+	} else if (dma_chan == 27) { /*5F*/
+		if (dmfc_size_27 / width > 2)
+			dmfc_gen1 |= 1UL << 21;
+		else
+			dmfc_gen1 &= ~(1UL << 21);
+	} else if (dma_chan == 28) { /*1*/
+		if (dmfc_size_28 / width > 2)
+			dmfc_gen1 |= 1UL << 16;
+		else
+			dmfc_gen1 &= ~(1UL << 16);
+	} else if (dma_chan == 29) { /*6F*/
+		if (dmfc_size_29 / width > 1)
+			dmfc_gen1 |= 1UL << 23;
+		else
+			dmfc_gen1 &= ~(1UL << 23);
+	}
+
+	__raw_writel(dmfc_gen1, DMFC_GENERAL1);
+}
+
+static void ipu_di_data_wave_config(int di,
+				     int wave_gen,
+				     int access_size, int component_size)
+{
+	u32 reg;
+	reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
+	    (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
+	__raw_writel(reg, DI_DW_GEN(di, wave_gen));
+}
+
+static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
+				    int up, int down)
+{
+	u32 reg;
+
+	reg = __raw_readl(DI_DW_GEN(di, wave_gen));
+	reg &= ~(0x3 << (di_pin * 2));
+	reg |= set << (di_pin * 2);
+	__raw_writel(reg, DI_DW_GEN(di, wave_gen));
+
+	__raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
+}
+
+static void ipu_di_sync_config(int di, int wave_gen,
+				int run_count, int run_src,
+				int offset_count, int offset_src,
+				int repeat_count, int cnt_clr_src,
+				int cnt_polarity_gen_en,
+				int cnt_polarity_clr_src,
+				int cnt_polarity_trigger_src,
+				int cnt_up, int cnt_down)
+{
+	u32 reg;
+
+	if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
+		(repeat_count >= 0x1000) ||
+		(cnt_up >= 0x400) || (cnt_down >= 0x400)) {
+		printf("DI%d counters out of range.\n", di);
+		return;
+	}
+
+	reg = (run_count << 19) | (++run_src << 16) |
+	    (offset_count << 3) | ++offset_src;
+	__raw_writel(reg, DI_SW_GEN0(di, wave_gen));
+	reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
+	    (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
+	reg |= (cnt_down << 16) | cnt_up;
+	if (repeat_count == 0) {
+		/* Enable auto reload */
+		reg |= 0x10000000;
+	}
+	__raw_writel(reg, DI_SW_GEN1(di, wave_gen));
+	reg = __raw_readl(DI_STP_REP(di, wave_gen));
+	reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
+	reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
+	__raw_writel(reg, DI_STP_REP(di, wave_gen));
+}
+
+static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
+{
+	int ptr = map * 3 + byte_num;
+	u32 reg;
+
+	reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
+	reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
+	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
+	__raw_writel(reg, DC_MAP_CONF_VAL(ptr));
+
+	reg = __raw_readl(DC_MAP_CONF_PTR(map));
+	reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
+	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
+	__raw_writel(reg, DC_MAP_CONF_PTR(map));
+}
+
+static void ipu_dc_map_clear(int map)
+{
+	u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
+	__raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
+		     DC_MAP_CONF_PTR(map));
+}
+
+static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
+			       int wave, int glue, int sync)
+{
+	u32 reg;
+	int stop = 1;
+
+	reg = sync;
+	reg |= (glue << 4);
+	reg |= (++wave << 11);
+	reg |= (++map << 15);
+	reg |= (operand << 20) & 0xFFF00000;
+	__raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
+
+	reg = (operand >> 12);
+	reg |= opcode << 4;
+	reg |= (stop << 9);
+	__raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
+}
+
+static void ipu_dc_link_event(int chan, int event, int addr, int priority)
+{
+	u32 reg;
+
+	reg = __raw_readl(DC_RL_CH(chan, event));
+	reg &= ~(0xFFFF << (16 * (event & 0x1)));
+	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
+	__raw_writel(reg, DC_RL_CH(chan, event));
+}
+
+/* Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
+ * U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
+ * V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;
+ */
+static const int rgb2ycbcr_coeff[5][3] = {
+	{0x4D, 0x96, 0x1D},
+	{0x3D5, 0x3AB, 0x80},
+	{0x80, 0x395, 0x3EB},
+	{0x0000, 0x0200, 0x0200},	/* B0, B1, B2 */
+	{0x2, 0x2, 0x2},	/* S0, S1, S2 */
+};
+
+/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+ * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+ * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
+ */
+static const int ycbcr2rgb_coeff[5][3] = {
+	{0x095, 0x000, 0x0CC},
+	{0x095, 0x3CE, 0x398},
+	{0x095, 0x0FF, 0x000},
+	{0x3E42, 0x010A, 0x3DD6},	/*B0,B1,B2 */
+	{0x1, 0x1, 0x1},	/*S0,S1,S2 */
+};
+
+#define mask_a(a) ((u32)(a) & 0x3FF)
+#define mask_b(b) ((u32)(b) & 0x3FFF)
+
+/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
+static int rgb_to_yuv(int n, int red, int green, int blue)
+{
+	int c;
+	c = red * rgb2ycbcr_coeff[n][0];
+	c += green * rgb2ycbcr_coeff[n][1];
+	c += blue * rgb2ycbcr_coeff[n][2];
+	c /= 16;
+	c += rgb2ycbcr_coeff[3][n] * 4;
+	c += 8;
+	c /= 16;
+	if (c < 0)
+		c = 0;
+	if (c > 255)
+		c = 255;
+	return c;
+}
+
+/*
+ * Row is for BG:	RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ * Column is for FG:	RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
+ */
+static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
+	{
+		{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
+		{0, 0},
+		{0, 0},
+		{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
+		{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
+	},
+	{
+		{0, 0},
+		{DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
+		{DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
+		{0, 0},
+		{DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
+	},
+	{
+		{0, 0},
+		{DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
+		{0, 0},
+		{0, 0},
+		{0, 0}
+	},
+	{
+		{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
+		{0, 0},
+		{0, 0},
+		{0, 0},
+		{0, 0}
+	},
+	{
+		{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
+		{DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
+		{0, 0},
+		{0, 0},
+		{0, 0}
+	}
+};
+
+static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
+static int color_key_4rgb = 1;
+
+void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
+			unsigned char srm_mode_update)
+{
+	u32 reg;
+	const int (*coeff)[5][3];
+
+	if (dp_csc_param.mode >= 0) {
+		reg = __raw_readl(DP_COM_CONF(dp));
+		reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+		reg |= dp_csc_param.mode;
+		__raw_writel(reg, DP_COM_CONF(dp));
+	}
+
+	coeff = dp_csc_param.coeff;
+
+	if (coeff) {
+		__raw_writel(mask_a((*coeff)[0][0]) |
+				(mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
+		__raw_writel(mask_a((*coeff)[0][2]) |
+				(mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
+		__raw_writel(mask_a((*coeff)[1][1]) |
+				(mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
+		__raw_writel(mask_a((*coeff)[2][0]) |
+				(mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
+		__raw_writel(mask_a((*coeff)[2][2]) |
+				(mask_b((*coeff)[3][0]) << 16) |
+				((*coeff)[4][0] << 30), DP_CSC_0(dp));
+		__raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
+				(mask_b((*coeff)[3][2]) << 16) |
+				((*coeff)[4][2] << 30), DP_CSC_1(dp));
+	}
+
+	if (srm_mode_update) {
+		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+		__raw_writel(reg, IPU_SRM_PRI2);
+	}
+}
+
+int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
+		 uint32_t out_pixel_fmt)
+{
+	int in_fmt, out_fmt;
+	int dp;
+	int partial = 0;
+	uint32_t reg;
+
+	if (channel == MEM_FG_SYNC) {
+		dp = DP_SYNC;
+		partial = 1;
+	} else if (channel == MEM_BG_SYNC) {
+		dp = DP_SYNC;
+		partial = 0;
+	} else if (channel == MEM_BG_ASYNC0) {
+		dp = DP_ASYNC0;
+		partial = 0;
+	} else {
+		return -EINVAL;
+	}
+
+	in_fmt = format_to_colorspace(in_pixel_fmt);
+	out_fmt = format_to_colorspace(out_pixel_fmt);
+
+	if (partial) {
+		if (in_fmt == RGB) {
+			if (out_fmt == RGB)
+				fg_csc_type = RGB2RGB;
+			else
+				fg_csc_type = RGB2YUV;
+		} else {
+			if (out_fmt == RGB)
+				fg_csc_type = YUV2RGB;
+			else
+				fg_csc_type = YUV2YUV;
+		}
+	} else {
+		if (in_fmt == RGB) {
+			if (out_fmt == RGB)
+				bg_csc_type = RGB2RGB;
+			else
+				bg_csc_type = RGB2YUV;
+		} else {
+			if (out_fmt == RGB)
+				bg_csc_type = YUV2RGB;
+			else
+				bg_csc_type = YUV2YUV;
+		}
+	}
+
+	/* Transform color key from rgb to yuv if CSC is enabled */
+	reg = __raw_readl(DP_COM_CONF(dp));
+	if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
+		(((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
+		((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
+		((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
+		((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
+		int red, green, blue;
+		int y, u, v;
+		uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) &
+			0xFFFFFFL;
+
+		debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
+			color_key);
+
+		red = (color_key >> 16) & 0xFF;
+		green = (color_key >> 8) & 0xFF;
+		blue = color_key & 0xFF;
+
+		y = rgb_to_yuv(0, red, green, blue);
+		u = rgb_to_yuv(1, red, green, blue);
+		v = rgb_to_yuv(2, red, green, blue);
+		color_key = (y << 16) | (u << 8) | v;
+
+		reg = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
+		__raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(dp));
+		color_key_4rgb = 0;
+
+		debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
+			color_key);
+	}
+
+	ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
+
+	return 0;
+}
+
+void ipu_dp_uninit(ipu_channel_t channel)
+{
+	int dp;
+	int partial = 0;
+
+	if (channel == MEM_FG_SYNC) {
+		dp = DP_SYNC;
+		partial = 1;
+	} else if (channel == MEM_BG_SYNC) {
+		dp = DP_SYNC;
+		partial = 0;
+	} else if (channel == MEM_BG_ASYNC0) {
+		dp = DP_ASYNC0;
+		partial = 0;
+	} else {
+		return;
+	}
+
+	if (partial)
+		fg_csc_type = CSC_NONE;
+	else
+		bg_csc_type = CSC_NONE;
+
+	ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
+}
+
+void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
+{
+	u32 reg = 0;
+
+	if ((dc_chan == 1) || (dc_chan == 5)) {
+		if (interlaced) {
+			ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
+			ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
+			ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
+		} else {
+			if (di) {
+				ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
+				ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
+				ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
+					4, 1);
+			} else {
+				ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
+				ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
+				ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
+					7, 1);
+			}
+		}
+		ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+
+		reg = 0x2;
+		reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+		reg |= di << 2;
+		if (interlaced)
+			reg |= DC_WR_CH_CONF_FIELD_MODE;
+	} else if ((dc_chan == 8) || (dc_chan == 9)) {
+		/* async channels */
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
+
+		reg = 0x3;
+		reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
+	}
+	__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+	__raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
+
+	__raw_writel(0x00000084, DC_GEN);
+}
+
+void ipu_dc_uninit(int dc_chan)
+{
+	if ((dc_chan == 1) || (dc_chan == 5)) {
+		ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
+	} else if ((dc_chan == 8) || (dc_chan == 9)) {
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
+		ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
+	}
+}
+
+int ipu_chan_is_interlaced(ipu_channel_t channel)
+{
+	if (channel == MEM_DC_SYNC)
+		return !!(__raw_readl(DC_WR_CH_CONF_1) &
+			  DC_WR_CH_CONF_FIELD_MODE);
+	else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
+		return !!(__raw_readl(DC_WR_CH_CONF_5) &
+			  DC_WR_CH_CONF_FIELD_MODE);
+	return 0;
+}
+
+void ipu_dp_dc_enable(ipu_channel_t channel)
+{
+	int di;
+	uint32_t reg;
+	uint32_t dc_chan;
+
+	if (channel == MEM_FG_SYNC)
+		dc_chan = 5;
+	if (channel == MEM_DC_SYNC)
+		dc_chan = 1;
+	else if (channel == MEM_BG_SYNC)
+		dc_chan = 5;
+	else
+		return;
+
+	if (channel == MEM_FG_SYNC) {
+		/* Enable FG channel */
+		reg = __raw_readl(DP_COM_CONF(DP_SYNC));
+		__raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
+
+		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+		__raw_writel(reg, IPU_SRM_PRI2);
+		return;
+	}
+
+	di = g_dc_di_assignment[dc_chan];
+
+	/* Make sure other DC sync channel is not assigned same DI */
+	reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
+	if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
+		reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
+		reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
+		__raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
+	}
+
+	reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+	reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
+	__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+	clk_enable(g_pixel_clk[di]);
+}
+
+static unsigned char dc_swap;
+
+void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
+{
+	uint32_t reg;
+	uint32_t csc;
+	uint32_t dc_chan = 0;
+	int timeout = 50;
+
+	dc_swap = swap;
+
+	if (channel == MEM_DC_SYNC) {
+		dc_chan = 1;
+	} else if (channel == MEM_BG_SYNC) {
+		dc_chan = 5;
+	} else if (channel == MEM_FG_SYNC) {
+		/* Disable FG channel */
+		dc_chan = 5;
+
+		reg = __raw_readl(DP_COM_CONF(DP_SYNC));
+		csc = reg & DP_COM_CONF_CSC_DEF_MASK;
+		if (csc == DP_COM_CONF_CSC_DEF_FG)
+			reg &= ~DP_COM_CONF_CSC_DEF_MASK;
+
+		reg &= ~DP_COM_CONF_FG_EN;
+		__raw_writel(reg, DP_COM_CONF(DP_SYNC));
+
+		reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+		__raw_writel(reg, IPU_SRM_PRI2);
+
+		timeout = 50;
+
+		/*
+		 * Wait for DC triple buffer to empty,
+		 * this check is useful for tv overlay.
+		 */
+		if (g_dc_di_assignment[dc_chan] == 0)
+			while ((__raw_readl(DC_STAT) & 0x00000002)
+			       != 0x00000002) {
+				udelay(2000);
+				timeout -= 2;
+				if (timeout <= 0)
+					break;
+			}
+		else if (g_dc_di_assignment[dc_chan] == 1)
+			while ((__raw_readl(DC_STAT) & 0x00000020)
+			       != 0x00000020) {
+				udelay(2000);
+				timeout -= 2;
+				if (timeout <= 0)
+					break;
+			}
+		return;
+	} else {
+		return;
+	}
+
+	if (dc_swap) {
+		/* Swap DC channel 1 and 5 settings, and disable old dc chan */
+		reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+		__raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
+		reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+		reg ^= DC_WR_CH_CONF_PROG_DI_ID;
+		__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+	} else {
+		timeout = 50;
+
+		/* Wait for DC triple buffer to empty */
+		if (g_dc_di_assignment[dc_chan] == 0)
+			while ((__raw_readl(DC_STAT) & 0x00000002)
+				!= 0x00000002) {
+				udelay(2000);
+				timeout -= 2;
+				if (timeout <= 0)
+					break;
+			}
+		else if (g_dc_di_assignment[dc_chan] == 1)
+			while ((__raw_readl(DC_STAT) & 0x00000020)
+				!= 0x00000020) {
+				udelay(2000);
+				timeout -= 2;
+				if (timeout <= 0)
+					break;
+			}
+
+		reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
+		reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
+		__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
+
+		reg = __raw_readl(IPU_DISP_GEN);
+		if (g_dc_di_assignment[dc_chan])
+			reg &= ~DI1_COUNTER_RELEASE;
+		else
+			reg &= ~DI0_COUNTER_RELEASE;
+		__raw_writel(reg, IPU_DISP_GEN);
+
+		/* Clock is already off because it must be done quickly, but
+		   we need to fix the ref count */
+		clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
+	}
+}
+
+void ipu_init_dc_mappings(void)
+{
+	/* IPU_PIX_FMT_RGB24 */
+	ipu_dc_map_clear(0);
+	ipu_dc_map_config(0, 0, 7, 0xFF);
+	ipu_dc_map_config(0, 1, 15, 0xFF);
+	ipu_dc_map_config(0, 2, 23, 0xFF);
+
+	/* IPU_PIX_FMT_RGB666 */
+	ipu_dc_map_clear(1);
+	ipu_dc_map_config(1, 0, 5, 0xFC);
+	ipu_dc_map_config(1, 1, 11, 0xFC);
+	ipu_dc_map_config(1, 2, 17, 0xFC);
+
+	/* IPU_PIX_FMT_YUV444 */
+	ipu_dc_map_clear(2);
+	ipu_dc_map_config(2, 0, 15, 0xFF);
+	ipu_dc_map_config(2, 1, 23, 0xFF);
+	ipu_dc_map_config(2, 2, 7, 0xFF);
+
+	/* IPU_PIX_FMT_RGB565 */
+	ipu_dc_map_clear(3);
+	ipu_dc_map_config(3, 0, 4, 0xF8);
+	ipu_dc_map_config(3, 1, 10, 0xFC);
+	ipu_dc_map_config(3, 2, 15, 0xF8);
+
+	/* IPU_PIX_FMT_LVDS666 */
+	ipu_dc_map_clear(4);
+	ipu_dc_map_config(4, 0, 5, 0xFC);
+	ipu_dc_map_config(4, 1, 13, 0xFC);
+	ipu_dc_map_config(4, 2, 21, 0xFC);
+}
+
+int ipu_pixfmt_to_map(uint32_t fmt)
+{
+	switch (fmt) {
+	case IPU_PIX_FMT_GENERIC:
+	case IPU_PIX_FMT_RGB24:
+		return 0;
+	case IPU_PIX_FMT_RGB666:
+		return 1;
+	case IPU_PIX_FMT_YUV444:
+		return 2;
+	case IPU_PIX_FMT_RGB565:
+		return 3;
+	case IPU_PIX_FMT_LVDS666:
+		return 4;
+	}
+
+	return -1;
+}
+
+/*
+ * This function is called to adapt synchronous LCD panel to IPU restriction.
+ */
+void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
+				      uint16_t width, uint16_t height,
+				      uint16_t h_start_width,
+				      uint16_t h_end_width,
+				      uint16_t v_start_width,
+				      uint16_t *v_end_width)
+{
+	if (*v_end_width < 2) {
+		uint16_t total_width = width + h_start_width + h_end_width;
+		uint16_t total_height_old = height + v_start_width +
+			(*v_end_width);
+		uint16_t total_height_new = height + v_start_width + 2;
+		*v_end_width = 2;
+		*pixel_clk = (*pixel_clk) * total_width * total_height_new /
+			(total_width * total_height_old);
+		printf("WARNING: adapt panel end blank lines\n");
+	}
+}
+
+/*
+ * This function is called to initialize a synchronous LCD panel.
+ *
+ * @param       disp            The DI the panel is attached to.
+ *
+ * @param       pixel_clk       Desired pixel clock frequency in Hz.
+ *
+ * @param       pixel_fmt       Input parameter for pixel format of buffer.
+ *                              Pixel format is a FOURCC ASCII code.
+ *
+ * @param       width           The width of panel in pixels.
+ *
+ * @param       height          The height of panel in pixels.
+ *
+ * @param       hStartWidth     The number of pixel clocks between the HSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
+ *                              clocks.
+ *
+ * @param       hEndWidth       The number of pixel clocks between the end of
+ *                              valid data and the HSYNC signal for next line.
+ *
+ * @param       vStartWidth     The number of lines between the VSYNC
+ *                              signal pulse and the start of valid data.
+ *
+ * @param       vSyncWidth      The width of the VSYNC signal in units of lines
+ *
+ * @param       vEndWidth       The number of lines between the end of valid
+ *                              data and the VSYNC signal for next frame.
+ *
+ * @param       sig             Bitfield of signal polarities for LCD interface.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *              fail.
+ */
+
+int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
+			    uint16_t width, uint16_t height,
+			    uint32_t pixel_fmt,
+			    uint16_t h_start_width, uint16_t h_sync_width,
+			    uint16_t h_end_width, uint16_t v_start_width,
+			    uint16_t v_sync_width, uint16_t v_end_width,
+			    uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
+{
+	uint32_t reg;
+	uint32_t di_gen, vsync_cnt;
+	uint32_t div, rounded_pixel_clk;
+	uint32_t h_total, v_total;
+	int map;
+	struct clk *di_parent;
+
+	debug("panel size = %d x %d\n", width, height);
+
+	if ((v_sync_width == 0) || (h_sync_width == 0))
+		return EINVAL;
+
+	adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
+					 h_start_width, h_end_width,
+					 v_start_width, &v_end_width);
+	h_total = width + h_sync_width + h_start_width + h_end_width;
+	v_total = height + v_sync_width + v_start_width + v_end_width;
+
+	/* Init clocking */
+	debug("pixel clk = %d\n", pixel_clk);
+
+	if (sig.ext_clk) {
+		if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/
+			/*
+			 * Set the  PLL to be an even multiple
+			 * of the pixel clock.
+			 */
+			if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
+				(clk_get_usecount(g_pixel_clk[1]) == 0)) {
+				di_parent = clk_get_parent(g_di_clk[disp]);
+				rounded_pixel_clk =
+					clk_round_rate(g_pixel_clk[disp],
+						pixel_clk);
+				div  = clk_get_rate(di_parent) /
+					rounded_pixel_clk;
+				if (div % 2)
+					div++;
+				if (clk_get_rate(di_parent) != div *
+					rounded_pixel_clk)
+					clk_set_rate(di_parent,
+						div * rounded_pixel_clk);
+				udelay(10000);
+				clk_set_rate(g_di_clk[disp],
+					2 * rounded_pixel_clk);
+				udelay(10000);
+			}
+		}
+		clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
+	} else {
+		if (clk_get_usecount(g_pixel_clk[disp]) != 0)
+			clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
+	}
+	rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
+	clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
+	udelay(5000);
+	/* Get integer portion of divider */
+	div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
+		rounded_pixel_clk;
+
+	ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
+	ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
+
+	map = ipu_pixfmt_to_map(pixel_fmt);
+	if (map < 0) {
+		debug("IPU_DISP: No MAP\n");
+		return -EINVAL;
+	}
+
+	di_gen = __raw_readl(DI_GENERAL(disp));
+
+	if (sig.interlaced) {
+		/* Setup internal HSYNC waveform */
+		ipu_di_sync_config(
+				disp,		/* display */
+				1,		/* counter */
+				h_total / 2 - 1,/* run count */
+				DI_SYNC_CLK,	/* run_resolution */
+				0,		/* offset */
+				DI_SYNC_NONE,	/* offset resolution */
+				0,		/* repeat count */
+				DI_SYNC_NONE,	/* CNT_CLR_SEL */
+				0,		/* CNT_POLARITY_GEN_EN */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				0		/* COUNT DOWN */
+				);
+
+		/* Field 1 VSYNC waveform */
+		ipu_di_sync_config(
+				disp,		/* display */
+				2,		/* counter */
+				h_total - 1,	/* run count */
+				DI_SYNC_CLK,	/* run_resolution */
+				0,		/* offset */
+				DI_SYNC_NONE,	/* offset resolution */
+				0,		/* repeat count */
+				DI_SYNC_NONE,	/* CNT_CLR_SEL */
+				0,		/* CNT_POLARITY_GEN_EN */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				4		/* COUNT DOWN */
+				);
+
+		/* Setup internal HSYNC waveform */
+		ipu_di_sync_config(
+				disp,		/* display */
+				3,		/* counter */
+				v_total * 2 - 1,/* run count */
+				DI_SYNC_INT_HSYNC,	/* run_resolution */
+				1,		/* offset */
+				DI_SYNC_INT_HSYNC,	/* offset resolution */
+				0,		/* repeat count */
+				DI_SYNC_NONE,	/* CNT_CLR_SEL */
+				0,		/* CNT_POLARITY_GEN_EN */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				4		/* COUNT DOWN */
+				);
+
+		/* Active Field ? */
+		ipu_di_sync_config(
+				disp,		/* display */
+				4,		/* counter */
+				v_total / 2 - 1,/* run count */
+				DI_SYNC_HSYNC,	/* run_resolution */
+				v_start_width,	/*  offset */
+				DI_SYNC_HSYNC,	/* offset resolution */
+				2,		/* repeat count */
+				DI_SYNC_VSYNC,	/* CNT_CLR_SEL */
+				0,		/* CNT_POLARITY_GEN_EN */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				0		/* COUNT DOWN */
+				);
+
+		/* Active Line */
+		ipu_di_sync_config(
+				disp,		/* display */
+				5,		/* counter */
+				0,		/* run count */
+				DI_SYNC_HSYNC,	/* run_resolution */
+				0,		/*  offset */
+				DI_SYNC_NONE,	/* offset resolution */
+				height / 2,	/* repeat count */
+				4,		/* CNT_CLR_SEL */
+				0,		/* CNT_POLARITY_GEN_EN */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				0		/* COUNT DOWN */
+				);
+
+		/* Field 0 VSYNC waveform */
+		ipu_di_sync_config(
+				disp,		/* display */
+				6,		/* counter */
+				v_total - 1,	/* run count */
+				DI_SYNC_HSYNC,	/* run_resolution */
+				0,		/* offset */
+				DI_SYNC_NONE,	/* offset resolution */
+				0,		/* repeat count */
+				DI_SYNC_NONE,	/* CNT_CLR_SEL  */
+				0,		/* CNT_POLARITY_GEN_EN */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				0		/* COUNT DOWN */
+				);
+
+		/* DC VSYNC waveform */
+		vsync_cnt = 7;
+		ipu_di_sync_config(
+				disp,		/* display */
+				7,		/* counter */
+				v_total / 2 - 1,/* run count */
+				DI_SYNC_HSYNC,	/* run_resolution  */
+				9,		/* offset  */
+				DI_SYNC_HSYNC,	/* offset resolution */
+				2,		/* repeat count */
+				DI_SYNC_VSYNC,	/* CNT_CLR_SEL */
+				0,		/* CNT_POLARITY_GEN_EN */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				0		/* COUNT DOWN */
+				);
+
+		/* active pixel waveform */
+		ipu_di_sync_config(
+				disp,		/* display */
+				8,		/* counter */
+				0,		/* run count  */
+				DI_SYNC_CLK,	/* run_resolution */
+				h_start_width,	/* offset  */
+				DI_SYNC_CLK,	/* offset resolution */
+				width,		/* repeat count  */
+				5,		/* CNT_CLR_SEL  */
+				0,		/* CNT_POLARITY_GEN_EN  */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL  */
+				0,		/* COUNT UP  */
+				0		/* COUNT DOWN */
+				);
+
+		ipu_di_sync_config(
+				disp,		/* display */
+				9,		/* counter */
+				v_total - 1,	/* run count */
+				DI_SYNC_INT_HSYNC,/* run_resolution */
+				v_total / 2,	/* offset  */
+				DI_SYNC_INT_HSYNC,/* offset resolution  */
+				0,		/* repeat count */
+				DI_SYNC_HSYNC,	/* CNT_CLR_SEL */
+				0,		/* CNT_POLARITY_GEN_EN  */
+				DI_SYNC_NONE,	/* CNT_POLARITY_CLR_SEL  */
+				DI_SYNC_NONE,	/* CNT_POLARITY_TRIGGER_SEL */
+				0,		/* COUNT UP */
+				4		/* COUNT DOWN */
+				);
+
+		/* set gentime select and tag sel */
+		reg = __raw_readl(DI_SW_GEN1(disp, 9));
+		reg &= 0x1FFFFFFF;
+		reg |= (3 - 1)<<29 | 0x00008000;
+		__raw_writel(reg, DI_SW_GEN1(disp, 9));
+
+		__raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
+
+		/* set y_sel = 1 */
+		di_gen |= 0x10000000;
+		di_gen |= DI_GEN_POLARITY_5;
+		di_gen |= DI_GEN_POLARITY_8;
+	} else {
+		/* Setup internal HSYNC waveform */
+		ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
+				0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
+				0, DI_SYNC_NONE,
+				DI_SYNC_NONE, 0, 0);
+
+		/* Setup external (delayed) HSYNC waveform */
+		ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
+				DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
+				0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
+				DI_SYNC_CLK, 0, h_sync_width * 2);
+		/* Setup VSYNC waveform */
+		vsync_cnt = DI_SYNC_VSYNC;
+		ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
+				DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
+				DI_SYNC_NONE, 1, DI_SYNC_NONE,
+				DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
+		__raw_writel(v_total - 1, DI_SCR_CONF(disp));
+
+		/* Setup active data waveform to sync with DC */
+		ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
+				v_sync_width + v_start_width, DI_SYNC_HSYNC,
+				height,
+				DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
+				DI_SYNC_NONE, 0, 0);
+		ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
+				h_sync_width + h_start_width, DI_SYNC_CLK,
+				width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
+				0);
+
+		/* reset all unused counters */
+		__raw_writel(0, DI_SW_GEN0(disp, 6));
+		__raw_writel(0, DI_SW_GEN1(disp, 6));
+		__raw_writel(0, DI_SW_GEN0(disp, 7));
+		__raw_writel(0, DI_SW_GEN1(disp, 7));
+		__raw_writel(0, DI_SW_GEN0(disp, 8));
+		__raw_writel(0, DI_SW_GEN1(disp, 8));
+		__raw_writel(0, DI_SW_GEN0(disp, 9));
+		__raw_writel(0, DI_SW_GEN1(disp, 9));
+
+		reg = __raw_readl(DI_STP_REP(disp, 6));
+		reg &= 0x0000FFFF;
+		__raw_writel(reg, DI_STP_REP(disp, 6));
+		__raw_writel(0, DI_STP_REP(disp, 7));
+		__raw_writel(0, DI_STP_REP(disp, 9));
+
+		/* Init template microcode */
+		if (disp) {
+		   ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+		   ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+		   ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+		} else {
+		   ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+		   ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+		   ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+		}
+
+		if (sig.Hsync_pol)
+			di_gen |= DI_GEN_POLARITY_2;
+		if (sig.Vsync_pol)
+			di_gen |= DI_GEN_POLARITY_3;
+
+		if (sig.clk_pol)
+			di_gen |= DI_GEN_POL_CLK;
+
+	}
+
+	__raw_writel(di_gen, DI_GENERAL(disp));
+
+	__raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
+			0x00000002, DI_SYNC_AS_GEN(disp));
+
+	reg = __raw_readl(DI_POL(disp));
+	reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
+	if (sig.enable_pol)
+		reg |= DI_POL_DRDY_POLARITY_15;
+	if (sig.data_pol)
+		reg |= DI_POL_DRDY_DATA_POLARITY;
+	__raw_writel(reg, DI_POL(disp));
+
+	__raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
+
+	return 0;
+}
+
+/*
+ * This function sets the foreground and background plane global alpha blending
+ * modes. This function also sets the DP graphic plane according to the
+ * parameter of IPUv3 DP channel.
+ *
+ * @param	channel		IPUv3 DP channel
+ *
+ * @param       enable          Boolean to enable or disable global alpha
+ *                              blending. If disabled, local blending is used.
+ *
+ * @param       alpha           Global alpha value.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
+				  uint8_t alpha)
+{
+	uint32_t reg;
+	uint32_t flow;
+
+	unsigned char bg_chan;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
+	    channel == MEM_BG_ASYNC1)
+		bg_chan = 1;
+	else
+		bg_chan = 0;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+
+	if (bg_chan) {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+	} else {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
+	}
+
+	if (enable) {
+		reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
+		__raw_writel(reg | ((uint32_t) alpha << 24),
+			     DP_GRAPH_WIND_CTRL(flow));
+
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+	} else {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
+	}
+
+	reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+	__raw_writel(reg, IPU_SRM_PRI2);
+
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	return 0;
+}
+
+/*
+ * This function sets the transparent color key for SDC graphic plane.
+ *
+ * @param       channel         Input parameter for the logical channel ID.
+ *
+ * @param       enable          Boolean to enable or disable color key
+ *
+ * @param       colorKey        24-bit RGB color for transparent color key.
+ *
+ * @return      Returns 0 on success or negative error code on fail
+ */
+int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
+			       uint32_t color_key)
+{
+	uint32_t reg, flow;
+	int y, u, v;
+	int red, green, blue;
+
+	if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
+		flow = DP_SYNC;
+	else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
+		flow = DP_ASYNC0;
+	else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
+		flow = DP_ASYNC1;
+	else
+		return -EINVAL;
+
+	if (!g_ipu_clk_enabled)
+		clk_enable(g_ipu_clk);
+
+	color_key_4rgb = 1;
+	/* Transform color key from rgb to yuv if CSC is enabled */
+	if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
+		((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
+		((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
+		((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
+
+		debug("color key 0x%x need change to yuv fmt\n", color_key);
+
+		red = (color_key >> 16) & 0xFF;
+		green = (color_key >> 8) & 0xFF;
+		blue = color_key & 0xFF;
+
+		y = rgb_to_yuv(0, red, green, blue);
+		u = rgb_to_yuv(1, red, green, blue);
+		v = rgb_to_yuv(2, red, green, blue);
+		color_key = (y << 16) | (u << 8) | v;
+
+		color_key_4rgb = 0;
+
+		debug("color key change to yuv fmt 0x%x\n", color_key);
+	}
+
+	if (enable) {
+		reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
+		__raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow));
+
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+	} else {
+		reg = __raw_readl(DP_COM_CONF(flow));
+		__raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
+	}
+
+	reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
+	__raw_writel(reg, IPU_SRM_PRI2);
+
+	if (!g_ipu_clk_enabled)
+		clk_disable(g_ipu_clk);
+
+	return 0;
+}
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..36f07bbee3368c01acf64003f415545c51bdaaf9
--- /dev/null
+++ b/drivers/video/ipu_regs.h
@@ -0,0 +1,418 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IPU_REGS_INCLUDED__
+#define __IPU_REGS_INCLUDED__
+
+#define IPU_DISP0_BASE		0x00000000
+#define IPU_MCU_T_DEFAULT	8
+#define IPU_DISP1_BASE		(IPU_MCU_T_DEFAULT << 25)
+#define IPU_CM_REG_BASE		0x1E000000
+#define IPU_STAT_REG_BASE	0x1E000200
+#define IPU_IDMAC_REG_BASE	0x1E008000
+#define IPU_ISP_REG_BASE	0x1E010000
+#define IPU_DP_REG_BASE		0x1E018000
+#define IPU_IC_REG_BASE		0x1E020000
+#define IPU_IRT_REG_BASE	0x1E028000
+#define IPU_CSI0_REG_BASE	0x1E030000
+#define IPU_CSI1_REG_BASE	0x1E038000
+#define IPU_DI0_REG_BASE	0x1E040000
+#define IPU_DI1_REG_BASE	0x1E048000
+#define IPU_SMFC_REG_BASE	0x1E050000
+#define IPU_DC_REG_BASE		0x1E058000
+#define IPU_DMFC_REG_BASE	0x1E060000
+#define IPU_CPMEM_REG_BASE	0x1F000000
+#define IPU_LUT_REG_BASE	0x1F020000
+#define IPU_SRM_REG_BASE	0x1F040000
+#define IPU_TPM_REG_BASE	0x1F060000
+#define IPU_DC_TMPL_REG_BASE	0x1F080000
+#define IPU_ISP_TBPR_REG_BASE	0x1F0C0000
+#define IPU_VDI_REG_BASE	0x1E068000
+
+
+extern u32 *ipu_dc_tmpl_reg;
+
+#define DC_EVT_NF		0
+#define DC_EVT_NL		1
+#define DC_EVT_EOF		2
+#define DC_EVT_NFIELD		3
+#define DC_EVT_EOL		4
+#define DC_EVT_EOFIELD		5
+#define DC_EVT_NEW_ADDR		6
+#define DC_EVT_NEW_CHAN		7
+#define DC_EVT_NEW_DATA		8
+
+#define DC_EVT_NEW_ADDR_W_0	0
+#define DC_EVT_NEW_ADDR_W_1	1
+#define DC_EVT_NEW_CHAN_W_0	2
+#define DC_EVT_NEW_CHAN_W_1	3
+#define DC_EVT_NEW_DATA_W_0	4
+#define DC_EVT_NEW_DATA_W_1	5
+#define DC_EVT_NEW_ADDR_R_0	6
+#define DC_EVT_NEW_ADDR_R_1	7
+#define DC_EVT_NEW_CHAN_R_0	8
+#define DC_EVT_NEW_CHAN_R_1	9
+#define DC_EVT_NEW_DATA_R_0	10
+#define DC_EVT_NEW_DATA_R_1	11
+
+/* Software reset for ipu */
+#define SW_IPU_RST	8
+
+enum {
+	IPU_CONF_DP_EN = 0x00000020,
+	IPU_CONF_DI0_EN = 0x00000040,
+	IPU_CONF_DI1_EN = 0x00000080,
+	IPU_CONF_DMFC_EN = 0x00000400,
+	IPU_CONF_DC_EN = 0x00000200,
+
+	DI0_COUNTER_RELEASE = 0x01000000,
+	DI1_COUNTER_RELEASE = 0x02000000,
+
+	DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
+	DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
+
+	DI_GEN_DI_CLK_EXT = 0x100000,
+	DI_GEN_POLARITY_1 = 0x00000001,
+	DI_GEN_POLARITY_2 = 0x00000002,
+	DI_GEN_POLARITY_3 = 0x00000004,
+	DI_GEN_POLARITY_4 = 0x00000008,
+	DI_GEN_POLARITY_5 = 0x00000010,
+	DI_GEN_POLARITY_6 = 0x00000020,
+	DI_GEN_POLARITY_7 = 0x00000040,
+	DI_GEN_POLARITY_8 = 0x00000080,
+	DI_GEN_POL_CLK = 0x20000,
+
+	DI_POL_DRDY_DATA_POLARITY = 0x00000080,
+	DI_POL_DRDY_POLARITY_15 = 0x00000010,
+	DI_VSYNC_SEL_OFFSET = 13,
+
+	DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
+	DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
+	DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
+	DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
+	DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
+	DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
+
+	DP_COM_CONF_FG_EN = 0x00000001,
+	DP_COM_CONF_GWSEL = 0x00000002,
+	DP_COM_CONF_GWAM = 0x00000004,
+	DP_COM_CONF_GWCKE = 0x00000008,
+	DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
+	DP_COM_CONF_CSC_DEF_OFFSET = 8,
+	DP_COM_CONF_CSC_DEF_FG = 0x00000300,
+	DP_COM_CONF_CSC_DEF_BG = 0x00000200,
+	DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
+	DP_COM_CONF_GAMMA_EN = 0x00001000,
+	DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
+};
+
+enum di_pins {
+	DI_PIN11 = 0,
+	DI_PIN12 = 1,
+	DI_PIN13 = 2,
+	DI_PIN14 = 3,
+	DI_PIN15 = 4,
+	DI_PIN16 = 5,
+	DI_PIN17 = 6,
+	DI_PIN_CS = 7,
+
+	DI_PIN_SER_CLK = 0,
+	DI_PIN_SER_RS = 1,
+};
+
+enum di_sync_wave {
+	DI_SYNC_NONE = -1,
+	DI_SYNC_CLK = 0,
+	DI_SYNC_INT_HSYNC = 1,
+	DI_SYNC_HSYNC = 2,
+	DI_SYNC_VSYNC = 3,
+	DI_SYNC_DE = 5,
+};
+
+struct ipu_cm {
+	u32 conf;
+	u32 sisg_ctrl0;
+	u32 sisg_ctrl1;
+	u32 sisg_set[6];
+	u32 sisg_clear[6];
+	u32 int_ctrl[15];
+	u32 sdma_event[10];
+	u32 srm_pri1;
+	u32 srm_pri2;
+	u32 fs_proc_flow[3];
+	u32 fs_disp_flow[2];
+	u32 skip;
+	u32 disp_alt_conf;
+	u32 disp_gen;
+	u32 disp_alt[4];
+	u32 snoop;
+	u32 mem_rst;
+	u32 pm;
+	u32 gpr;
+	u32 reserved0[26];
+	u32 ch_db_mode_sel[2];
+	u32 reserved1[16];
+	u32 alt_ch_db_mode_sel[2];
+	u32 reserved2[2];
+	u32 ch_trb_mode_sel[2];
+};
+
+struct ipu_idmac {
+	u32 conf;
+	u32 ch_en[2];
+	u32 sep_alpha;
+	u32 alt_sep_alpha;
+	u32 ch_pri[2];
+	u32 wm_en[2];
+	u32 lock_en[2];
+	u32 sub_addr[5];
+	u32 bndm_en[2];
+	u32 sc_cord[2];
+	u32 reserved[45];
+	u32 ch_busy[2];
+};
+
+struct ipu_com_async {
+	u32 com_conf_async;
+	u32 graph_wind_ctrl_async;
+	u32 fg_pos_async;
+	u32 cur_pos_async;
+	u32 cur_map_async;
+	u32 gamma_c_async[8];
+	u32 gamma_s_async[4];
+	u32 dp_csca_async[4];
+	u32 dp_csc_async[2];
+};
+
+struct ipu_dp {
+	u32 com_conf_sync;
+	u32 graph_wind_ctrl_sync;
+	u32 fg_pos_sync;
+	u32 cur_pos_sync;
+	u32 cur_map_sync;
+	u32 gamma_c_sync[8];
+	u32 gamma_s_sync[4];
+	u32 csca_sync[4];
+	u32 csc_sync[2];
+	u32 cur_pos_alt;
+	struct ipu_com_async async[2];
+};
+
+struct ipu_di {
+	u32 general;
+	u32 bs_clkgen0;
+	u32 bs_clkgen1;
+	u32 sw_gen0[9];
+	u32 sw_gen1[9];
+	u32 sync_as;
+	u32 dw_gen[12];
+	u32 dw_set[48];
+	u32 stp_rep[4];
+	u32 stp_rep9;
+	u32 ser_conf;
+	u32 ssc;
+	u32 pol;
+	u32 aw0;
+	u32 aw1;
+	u32 scr_conf;
+	u32 stat;
+};
+
+struct ipu_stat {
+	u32 int_stat[15];
+	u32 cur_buf[2];
+	u32 alt_cur_buf_0;
+	u32 alt_cur_buf_1;
+	u32 srm_stat;
+	u32 proc_task_stat;
+	u32 disp_task_stat;
+	u32 triple_cur_buf[4];
+	u32 ch_buf0_rdy[2];
+	u32 ch_buf1_rdy[2];
+	u32 alt_ch_buf0_rdy[2];
+	u32 alt_ch_buf1_rdy[2];
+	u32 ch_buf2_rdy[2];
+};
+
+struct ipu_dc_ch {
+	u32 wr_ch_conf;
+	u32 wr_ch_addr;
+	u32 rl[5];
+};
+
+struct ipu_dc {
+	struct ipu_dc_ch dc_ch0_1_2[3];
+	u32 cmd_ch_conf_3;
+	u32 cmd_ch_conf_4;
+	struct ipu_dc_ch dc_ch5_6[2];
+	struct ipu_dc_ch dc_ch8;
+	u32 rl6_ch_8;
+	struct ipu_dc_ch dc_ch9;
+	u32 rl6_ch_9;
+	u32 gen;
+	u32 disp_conf1[4];
+	u32 disp_conf2[4];
+	u32 di0_conf[2];
+	u32 di1_conf[2];
+	u32 dc_map_ptr[15];
+	u32 dc_map_val[12];
+	u32 udge[16];
+	u32 lla[2];
+	u32 r_lla[2];
+	u32 wr_ch_addr_5_alt;
+	u32 stat;
+};
+
+struct ipu_dmfc {
+	u32 rd_chan;
+	u32 wr_chan;
+	u32 wr_chan_def;
+	u32 dp_chan;
+	u32 dp_chan_def;
+	u32 general[2];
+	u32 ic_ctrl;
+	u32 wr_chan_alt;
+	u32 wr_chan_def_alt;
+	u32 general1_alt;
+	u32 stat;
+};
+
+#define IPU_CM_REG		((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
+				IPU_CM_REG_BASE))
+#define IPU_CONF		(&IPU_CM_REG->conf)
+#define IPU_SRM_PRI1		(&IPU_CM_REG->srm_pri1)
+#define IPU_SRM_PRI2		(&IPU_CM_REG->srm_pri2)
+#define IPU_FS_PROC_FLOW1	(&IPU_CM_REG->fs_proc_flow[0])
+#define IPU_FS_PROC_FLOW2	(&IPU_CM_REG->fs_proc_flow[1])
+#define IPU_FS_PROC_FLOW3	(&IPU_CM_REG->fs_proc_flow[2])
+#define IPU_FS_DISP_FLOW1	(&IPU_CM_REG->fs_disp_flow[0])
+#define IPU_DISP_GEN		(&IPU_CM_REG->disp_gen)
+#define IPU_MEM_RST		(&IPU_CM_REG->mem_rst)
+#define IPU_GPR			(&IPU_CM_REG->gpr)
+#define IPU_CHA_DB_MODE_SEL(ch)	(&IPU_CM_REG->ch_db_mode_sel[ch / 32])
+
+#define IPU_STAT		((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
+				IPU_STAT_REG_BASE))
+#define IPU_CHA_CUR_BUF(ch)	(&IPU_STAT->cur_buf[ch / 32])
+#define IPU_CHA_BUF0_RDY(ch)	(&IPU_STAT->ch_buf0_rdy[ch / 32])
+#define IPU_CHA_BUF1_RDY(ch)	(&IPU_STAT->ch_buf1_rdy[ch / 32])
+
+#define IPU_INT_CTRL(n)		(&IPU_CM_REG->int_ctrl[(n) - 1])
+
+#define IDMAC_REG		((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
+				IPU_IDMAC_REG_BASE))
+#define IDMAC_CONF		(&IDMAC_REG->conf)
+#define IDMAC_CHA_EN(ch)	(&IDMAC_REG->ch_en[ch / 32])
+#define IDMAC_CHA_PRI(ch)	(&IDMAC_REG->ch_pri[ch / 32])
+
+#define DI_REG(di)		((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
+				((di == 1) ? IPU_DI1_REG_BASE : \
+				IPU_DI0_REG_BASE)))
+#define DI_GENERAL(di)		(&DI_REG(di)->general)
+#define DI_BS_CLKGEN0(di)	(&DI_REG(di)->bs_clkgen0)
+#define DI_BS_CLKGEN1(di)	(&DI_REG(di)->bs_clkgen1)
+
+#define DI_SW_GEN0(di, gen)	(&DI_REG(di)->sw_gen0[gen - 1])
+#define DI_SW_GEN1(di, gen)	(&DI_REG(di)->sw_gen1[gen - 1])
+#define DI_STP_REP(di, gen)	(&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_SYNC_AS_GEN(di)	(&DI_REG(di)->sync_as)
+#define DI_DW_GEN(di, gen)	(&DI_REG(di)->dw_gen[gen])
+#define DI_DW_SET(di, gen, set)	(&DI_REG(di)->dw_set[gen + 12 * set])
+#define DI_POL(di)		(&DI_REG(di)->pol)
+#define DI_SCR_CONF(di)		(&DI_REG(di)->scr_conf)
+
+#define DMFC_REG		((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
+				IPU_DMFC_REG_BASE))
+#define DMFC_WR_CHAN		(&DMFC_REG->wr_chan)
+#define DMFC_WR_CHAN_DEF	(&DMFC_REG->wr_chan_def)
+#define DMFC_DP_CHAN		(&DMFC_REG->dp_chan)
+#define DMFC_DP_CHAN_DEF	(&DMFC_REG->dp_chan_def)
+#define DMFC_GENERAL1		(&DMFC_REG->general[0])
+#define DMFC_IC_CTRL		(&DMFC_REG->ic_ctrl)
+
+
+#define DC_REG			((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
+				IPU_DC_REG_BASE))
+#define DC_MAP_CONF_PTR(n)	(&DC_REG->dc_map_ptr[n / 2])
+#define DC_MAP_CONF_VAL(n)	(&DC_REG->dc_map_val[n / 2])
+
+
+static inline struct ipu_dc_ch *dc_ch_offset(int ch)
+{
+	switch (ch) {
+	case 0:
+	case 1:
+	case 2:
+		return &DC_REG->dc_ch0_1_2[ch];
+	case 5:
+	case 6:
+		return &DC_REG->dc_ch5_6[ch - 5];
+	case 8:
+		return &DC_REG->dc_ch8;
+	case 9:
+		return &DC_REG->dc_ch9;
+	default:
+		printf("%s: invalid channel %d\n", __func__, ch);
+		return NULL;
+	}
+
+}
+
+#define DC_RL_CH(ch, evt)	(&dc_ch_offset(ch)->rl[evt / 2])
+
+#define DC_WR_CH_CONF(ch)	(&dc_ch_offset(ch)->wr_ch_conf)
+#define DC_WR_CH_ADDR(ch)	(&dc_ch_offset(ch)->wr_ch_addr)
+
+#define DC_WR_CH_CONF_1		DC_WR_CH_CONF(1)
+#define DC_WR_CH_CONF_5		DC_WR_CH_CONF(5)
+
+#define DC_GEN			(&DC_REG->gen)
+#define DC_DISP_CONF2(disp)	(&DC_REG->disp_conf2[disp])
+#define DC_STAT			(&DC_REG->stat)
+
+#define DP_SYNC 0
+#define DP_ASYNC0 0x60
+#define DP_ASYNC1 0xBC
+
+#define DP_REG			((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
+				IPU_DP_REG_BASE))
+#define DP_COM_CONF(flow)	(&DP_REG->com_conf_sync)
+#define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync)
+#define DP_CSC_A_0(flow)	(&DP_REG->csca_sync[0])
+#define DP_CSC_A_1(flow)	(&DP_REG->csca_sync[1])
+#define DP_CSC_A_2(flow)	(&DP_REG->csca_sync[2])
+#define DP_CSC_A_3(flow)	(&DP_REG->csca_sync[3])
+
+#define DP_CSC_0(flow)		(&DP_REG->csc_sync[0])
+#define DP_CSC_1(flow)		(&DP_REG->csc_sync[1])
+
+/* DC template opcodes */
+#define WROD(lf)		(0x18 | (lf << 1))
+
+#endif
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
new file mode 100644
index 0000000000000000000000000000000000000000..a66981c27c9f86bedaf3d719aedc4ad8352f120d
--- /dev/null
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -0,0 +1,642 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * MX51 Linux framebuffer:
+ *
+ * (C) Copyright 2004-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+#include <common.h>
+#include <asm/errno.h>
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <lcd.h>
+#include "videomodes.h"
+#include "ipu.h"
+#include "mxcfb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base;			/* Start of framebuffer memory	*/
+void *lcd_console_address;	/* Start of console buffer	*/
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+vidinfo_t panel_info;
+
+static int mxcfb_map_video_memory(struct fb_info *fbi);
+static int mxcfb_unmap_video_memory(struct fb_info *fbi);
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+void fb_videomode_to_var(struct fb_var_screeninfo *var,
+			 const struct fb_videomode *mode)
+{
+	var->xres = mode->xres;
+	var->yres = mode->yres;
+	var->xres_virtual = mode->xres;
+	var->yres_virtual = mode->yres;
+	var->xoffset = 0;
+	var->yoffset = 0;
+	var->pixclock = mode->pixclock;
+	var->left_margin = mode->left_margin;
+	var->right_margin = mode->right_margin;
+	var->upper_margin = mode->upper_margin;
+	var->lower_margin = mode->lower_margin;
+	var->hsync_len = mode->hsync_len;
+	var->vsync_len = mode->vsync_len;
+	var->sync = mode->sync;
+	var->vmode = mode->vmode & FB_VMODE_MASK;
+}
+
+/*
+ * Structure containing the MXC specific framebuffer information.
+ */
+struct mxcfb_info {
+	int blank;
+	ipu_channel_t ipu_ch;
+	int ipu_di;
+	u32 ipu_di_pix_fmt;
+	unsigned char overlay;
+	unsigned char alpha_chan_en;
+	dma_addr_t alpha_phy_addr0;
+	dma_addr_t alpha_phy_addr1;
+	void *alpha_virt_addr0;
+	void *alpha_virt_addr1;
+	uint32_t alpha_mem_len;
+	uint32_t cur_ipu_buf;
+	uint32_t cur_ipu_alpha_buf;
+
+	u32 pseudo_palette[16];
+};
+
+enum {
+	BOTH_ON,
+	SRC_ON,
+	TGT_ON,
+	BOTH_OFF
+};
+
+static unsigned long default_bpp = 16;
+static unsigned char g_dp_in_use;
+static struct fb_info *mxcfb_info[3];
+static int ext_clk_used;
+
+static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+{
+	uint32_t pixfmt = 0;
+
+	debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel);
+
+	if (fbi->var.nonstd)
+		return fbi->var.nonstd;
+
+	switch (fbi->var.bits_per_pixel) {
+	case 24:
+		pixfmt = IPU_PIX_FMT_BGR24;
+		break;
+	case 32:
+		pixfmt = IPU_PIX_FMT_BGR32;
+		break;
+	case 16:
+		pixfmt = IPU_PIX_FMT_RGB565;
+		break;
+	}
+	return pixfmt;
+}
+
+/*
+ * Set fixed framebuffer parameters based on variable settings.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_fix(struct fb_info *info)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	struct fb_var_screeninfo *var = &info->var;
+
+	fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+
+	fix->type = FB_TYPE_PACKED_PIXELS;
+	fix->accel = FB_ACCEL_NONE;
+	fix->visual = FB_VISUAL_TRUECOLOR;
+	fix->xpanstep = 1;
+	fix->ypanstep = 1;
+
+	return 0;
+}
+
+static int setup_disp_channel1(struct fb_info *fbi)
+{
+	ipu_channel_params_t params;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	memset(&params, 0, sizeof(params));
+	params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
+
+	debug("%s called\n", __func__);
+	/*
+	 * Assuming interlaced means yuv output, below setting also
+	 * valid for mem_dc_sync. FG should have the same vmode as BG.
+	 */
+	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+		params.mem_dp_bg_sync.interlaced = 1;
+		params.mem_dp_bg_sync.out_pixel_fmt =
+			IPU_PIX_FMT_YUV444;
+	} else {
+		if (mxc_fbi->ipu_di_pix_fmt) {
+			params.mem_dp_bg_sync.out_pixel_fmt =
+				mxc_fbi->ipu_di_pix_fmt;
+		} else {
+			params.mem_dp_bg_sync.out_pixel_fmt =
+				IPU_PIX_FMT_RGB666;
+		}
+	}
+	params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
+	if (mxc_fbi->alpha_chan_en)
+		params.mem_dp_bg_sync.alpha_chan_en = 1;
+
+	ipu_init_channel(mxc_fbi->ipu_ch, &params);
+
+	return 0;
+}
+
+static int setup_disp_channel2(struct fb_info *fbi)
+{
+	int retval = 0;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+
+	mxc_fbi->cur_ipu_buf = 1;
+	if (mxc_fbi->alpha_chan_en)
+		mxc_fbi->cur_ipu_alpha_buf = 1;
+
+	fbi->var.xoffset = fbi->var.yoffset = 0;
+
+	debug("%s: %x %d %d %d %lx %lx\n",
+		__func__,
+		mxc_fbi->ipu_ch,
+		fbi->var.xres,
+		fbi->var.yres,
+		fbi->fix.line_length,
+		fbi->fix.smem_start,
+		fbi->fix.smem_start +
+		(fbi->fix.line_length * fbi->var.yres));
+
+	retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
+					 bpp_to_pixfmt(fbi),
+					 fbi->var.xres, fbi->var.yres,
+					 fbi->fix.line_length,
+					 fbi->fix.smem_start +
+					 (fbi->fix.line_length * fbi->var.yres),
+					 fbi->fix.smem_start,
+					 0, 0);
+	if (retval)
+		printf("ipu_init_channel_buffer error %d\n", retval);
+
+	return retval;
+}
+
+/*
+ * Set framebuffer parameters and change the operating mode.
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_set_par(struct fb_info *fbi)
+{
+	int retval = 0;
+	u32 mem_len;
+	ipu_di_signal_cfg_t sig_cfg;
+	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+	uint32_t out_pixel_fmt;
+
+	ipu_disable_channel(mxc_fbi->ipu_ch);
+	ipu_uninit_channel(mxc_fbi->ipu_ch);
+	mxcfb_set_fix(fbi);
+
+	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
+	if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
+		if (fbi->fix.smem_start)
+			mxcfb_unmap_video_memory(fbi);
+
+		if (mxcfb_map_video_memory(fbi) < 0)
+			return -ENOMEM;
+	}
+
+	setup_disp_channel1(fbi);
+
+	memset(&sig_cfg, 0, sizeof(sig_cfg));
+	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
+		sig_cfg.interlaced = 1;
+		out_pixel_fmt = IPU_PIX_FMT_YUV444;
+	} else {
+		if (mxc_fbi->ipu_di_pix_fmt)
+			out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
+		else
+			out_pixel_fmt = IPU_PIX_FMT_RGB666;
+	}
+	if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
+		sig_cfg.odd_field_first = 1;
+	if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used)
+		sig_cfg.ext_clk = 1;
+	if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
+		sig_cfg.Hsync_pol = 1;
+	if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
+		sig_cfg.Vsync_pol = 1;
+	if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
+		sig_cfg.clk_pol = 1;
+	if (fbi->var.sync & FB_SYNC_DATA_INVERT)
+		sig_cfg.data_pol = 1;
+	if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
+		sig_cfg.enable_pol = 1;
+	if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
+		sig_cfg.clkidle_en = 1;
+
+	debug("pixclock = %ul Hz\n",
+		(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+
+	if (ipu_init_sync_panel(mxc_fbi->ipu_di,
+				(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
+				fbi->var.xres, fbi->var.yres,
+				out_pixel_fmt,
+				fbi->var.left_margin,
+				fbi->var.hsync_len,
+				fbi->var.right_margin,
+				fbi->var.upper_margin,
+				fbi->var.vsync_len,
+				fbi->var.lower_margin,
+				0, sig_cfg) != 0) {
+		puts("mxcfb: Error initializing panel.\n");
+		return -EINVAL;
+	}
+
+	retval = setup_disp_channel2(fbi);
+	if (retval)
+		return retval;
+
+	if (mxc_fbi->blank == FB_BLANK_UNBLANK)
+		ipu_enable_channel(mxc_fbi->ipu_ch);
+
+	return retval;
+}
+
+/*
+ * Check framebuffer variable parameters and adjust to valid values.
+ *
+ * @param       var      framebuffer variable parameters
+ *
+ * @param       info     framebuffer information pointer
+ */
+static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+	u32 vtotal;
+	u32 htotal;
+
+	if (var->xres_virtual < var->xres)
+		var->xres_virtual = var->xres;
+	if (var->yres_virtual < var->yres)
+		var->yres_virtual = var->yres;
+
+	if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+	    (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
+		var->bits_per_pixel = default_bpp;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		var->red.length = 3;
+		var->red.offset = 5;
+		var->red.msb_right = 0;
+
+		var->green.length = 3;
+		var->green.offset = 2;
+		var->green.msb_right = 0;
+
+		var->blue.length = 2;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 16:
+		var->red.length = 5;
+		var->red.offset = 11;
+		var->red.msb_right = 0;
+
+		var->green.length = 6;
+		var->green.offset = 5;
+		var->green.msb_right = 0;
+
+		var->blue.length = 5;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 24:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		var->transp.msb_right = 0;
+		break;
+	case 32:
+		var->red.length = 8;
+		var->red.offset = 16;
+		var->red.msb_right = 0;
+
+		var->green.length = 8;
+		var->green.offset = 8;
+		var->green.msb_right = 0;
+
+		var->blue.length = 8;
+		var->blue.offset = 0;
+		var->blue.msb_right = 0;
+
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		var->transp.msb_right = 0;
+		break;
+	}
+
+	if (var->pixclock < 1000) {
+		htotal = var->xres + var->right_margin + var->hsync_len +
+		    var->left_margin;
+		vtotal = var->yres + var->lower_margin + var->vsync_len +
+		    var->upper_margin;
+		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
+		var->pixclock = KHZ2PICOS(var->pixclock);
+		printf("pixclock set for 60Hz refresh = %u ps\n",
+			var->pixclock);
+	}
+
+	var->height = -1;
+	var->width = -1;
+	var->grayscale = 0;
+
+	return 0;
+}
+
+static int mxcfb_map_video_memory(struct fb_info *fbi)
+{
+	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {
+		fbi->fix.smem_len = fbi->var.yres_virtual *
+				    fbi->fix.line_length;
+	}
+
+	fbi->screen_base = (char *)lcd_base;
+	fbi->fix.smem_start = (unsigned long)lcd_base;
+	if (fbi->screen_base == 0) {
+		puts("Unable to allocate framebuffer memory\n");
+		fbi->fix.smem_len = 0;
+		fbi->fix.smem_start = 0;
+		return -EBUSY;
+	}
+
+	debug("allocated fb @ paddr=0x%08X, size=%d.\n",
+		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+
+	fbi->screen_size = fbi->fix.smem_len;
+
+	/* Clear the screen */
+	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+
+	return 0;
+}
+
+static int mxcfb_unmap_video_memory(struct fb_info *fbi)
+{
+	fbi->screen_base = 0;
+	fbi->fix.smem_start = 0;
+	fbi->fix.smem_len = 0;
+	return 0;
+}
+
+/*
+ * Initializes the framebuffer information pointer. After allocating
+ * sufficient memory for the framebuffer structure, the fields are
+ * filled with custom information passed in from the configurable
+ * structures.  This includes information such as bits per pixel,
+ * color maps, screen width/height and RGBA offsets.
+ *
+ * @return      Framebuffer structure initialized with our information
+ */
+static struct fb_info *mxcfb_init_fbinfo(void)
+{
+#define BYTES_PER_LONG 4
+#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+	char *p;
+	int size = sizeof(struct mxcfb_info) + PADDING +
+		sizeof(struct fb_info);
+
+	debug("%s: %d %d %d %d\n",
+		__func__,
+		PADDING,
+		size,
+		sizeof(struct mxcfb_info),
+		sizeof(struct fb_info));
+	/*
+	 * Allocate sufficient memory for the fb structure
+	 */
+
+	p = malloc(size);
+	if (!p)
+		return NULL;
+
+	memset(p, 0, size);
+
+	fbi = (struct fb_info *)p;
+	fbi->par = p + sizeof(struct fb_info) + PADDING;
+
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+	debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n",
+		(unsigned int)fbi, (unsigned int)mxcfbi);
+
+	fbi->var.activate = FB_ACTIVATE_NOW;
+
+	fbi->flags = FBINFO_FLAG_DEFAULT;
+	fbi->pseudo_palette = mxcfbi->pseudo_palette;
+
+	return fbi;
+}
+
+/*
+ * Probe routine for the framebuffer driver. It is called during the
+ * driver binding process.      The following functions are performed in
+ * this routine: Framebuffer initialization, Memory allocation and
+ * mapping, Framebuffer registration, IPU initialization.
+ *
+ * @return      Appropriate error code to the kernel common code
+ */
+static int mxcfb_probe(u32 interface_pix_fmt, struct fb_videomode *mode)
+{
+	struct fb_info *fbi;
+	struct mxcfb_info *mxcfbi;
+	int ret = 0;
+
+	/*
+	 * Initialize FB structures
+	 */
+	fbi = mxcfb_init_fbinfo();
+	if (!fbi) {
+		ret = -ENOMEM;
+		goto err0;
+	}
+	mxcfbi = (struct mxcfb_info *)fbi->par;
+
+	if (!g_dp_in_use) {
+		mxcfbi->ipu_ch = MEM_BG_SYNC;
+		mxcfbi->blank = FB_BLANK_UNBLANK;
+	} else {
+		mxcfbi->ipu_ch = MEM_DC_SYNC;
+		mxcfbi->blank = FB_BLANK_POWERDOWN;
+	}
+
+	mxcfbi->ipu_di = 0;
+
+	ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
+	ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);
+	strcpy(fbi->fix.id, "DISP3 BG");
+
+	g_dp_in_use = 1;
+
+	mxcfb_info[mxcfbi->ipu_di] = fbi;
+
+	/* Need dummy values until real panel is configured */
+	fbi->var.xres = 640;
+	fbi->var.yres = 480;
+	fbi->var.bits_per_pixel = 16;
+
+	mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
+	fb_videomode_to_var(&fbi->var, mode);
+
+	mxcfb_check_var(&fbi->var, fbi);
+
+	/* Default Y virtual size is 2x panel size */
+	fbi->var.yres_virtual = fbi->var.yres * 2;
+
+	mxcfb_set_fix(fbi);
+
+	/* alocate fb first */
+	if (mxcfb_map_video_memory(fbi) < 0)
+		return -ENOMEM;
+
+	mxcfb_set_par(fbi);
+
+	/* Setting panel_info for lcd */
+	panel_info.cmap = NULL;
+	panel_info.vl_col = fbi->var.xres;
+	panel_info.vl_row = fbi->var.yres;
+	panel_info.vl_bpix = LCD_BPP;
+
+	lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+
+	debug("MXC IPUV3 configured\n"
+		"XRES = %d YRES = %d BitsXpixel = %d\n",
+		panel_info.vl_col,
+		panel_info.vl_row,
+		panel_info.vl_bpix);
+
+	ipu_dump_registers();
+
+	return 0;
+
+err0:
+	return ret;
+}
+
+int overwrite_console(void)
+{
+	/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
+	return 1;
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	u32 mem_len = panel_info.vl_col *
+		panel_info.vl_row *
+		NBITS(panel_info.vl_bpix) / 8;
+
+	/*
+	 * We rely on lcdbase being a physical address, i.e., either MMU off,
+	 * or 1-to-1 mapping. Might want to add some virt2phys here.
+	 */
+	if (!lcdbase)
+		return;
+
+	memset(lcdbase, 0, mem_len);
+}
+
+int mx51_fb_init(struct fb_videomode *mode)
+{
+	int ret;
+
+	ret = ipu_probe();
+	if (ret)
+		puts("Error initializing IPU\n");
+
+	lcd_base += 56;
+
+	debug("Framebuffer at 0x%x\n", (unsigned int)lcd_base);
+	ret = mxcfb_probe(IPU_PIX_FMT_RGB666, mode);
+
+	return ret;
+}
diff --git a/drivers/video/mxcfb.h b/drivers/video/mxcfb.h
new file mode 100644
index 0000000000000000000000000000000000000000..d508196603bc943aed047dddbadb0a5078629017
--- /dev/null
+++ b/drivers/video/mxcfb.h
@@ -0,0 +1,68 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Linux IPU driver for MX51:
+ *
+ * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXCFB_H__
+#define __ASM_ARCH_MXCFB_H__
+
+#define FB_SYNC_OE_LOW_ACT	0x80000000
+#define FB_SYNC_CLK_LAT_FALL	0x40000000
+#define FB_SYNC_DATA_INVERT	0x20000000
+#define FB_SYNC_CLK_IDLE_EN	0x10000000
+#define FB_SYNC_SHARP_MODE	0x08000000
+#define FB_SYNC_SWAP_RGB	0x04000000
+
+struct mxcfb_gbl_alpha {
+	int enable;
+	int alpha;
+};
+
+struct mxcfb_loc_alpha {
+	int enable;
+	int alpha_in_pixel;
+	unsigned long alpha_phy_addr0;
+	unsigned long alpha_phy_addr1;
+};
+
+struct mxcfb_color_key {
+	int enable;
+	__u32 color_key;
+};
+
+struct mxcfb_pos {
+	__u16 x;
+	__u16 y;
+};
+
+struct mxcfb_gamma {
+	int enable;
+	int constk[16];
+	int slopek[16];
+};
+
+#endif
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index 3fc79909eaadfea2ebd6b140e8e8a9e3299b35d7..1cc31a968dd92b40d737e465c0b5113942020962 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -121,7 +121,7 @@ static int __init compr_init(struct ubifs_compressor *compr)
 {
 	ubifs_compressors[compr->compr_type] = compr;
 
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 	ubifs_compressors[compr->compr_type]->name += gd->reloc_off;
 	ubifs_compressors[compr->compr_type]->capi_name += gd->reloc_off;
 	ubifs_compressors[compr->compr_type]->decompress += gd->reloc_off;
diff --git a/include/asm-offsets.h b/include/asm-offsets.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad3bf1f0bd43044a0ba552c8d655ce4a5ed145bf
--- /dev/null
+++ b/include/asm-offsets.h
@@ -0,0 +1,6 @@
+#ifndef	DO_DEPS_ONLY
+
+#include <generated/generic-asm-offsets.h>
+/* #include <generated/asm-offsets.h> */
+
+#endif
diff --git a/include/command.h b/include/command.h
index 5c146162337c9ef08161167639cde0868c6f5cf3..46a9ec4c4cac859c7c261cb39f15eceae4d5b01d 100644
--- a/include/command.h
+++ b/include/command.h
@@ -125,7 +125,7 @@ cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
 
 #endif	/* CONFIG_SYS_LONGHELP */
 
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
 void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
 #endif
 #endif	/* __COMMAND_H */
diff --git a/include/common.h b/include/common.h
index 0686a173d52bc5120a2a281dd3d31c682b94f78c..189ad8122b6445797a55bb597a0f581694057925 100644
--- a/include/common.h
+++ b/include/common.h
@@ -35,6 +35,7 @@ typedef volatile unsigned short vu_short;
 typedef volatile unsigned char	vu_char;
 
 #include <config.h>
+#include <asm-offsets.h>
 #include <linux/bitops.h>
 #include <linux/types.h>
 #include <linux/string.h>
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
index 26d4d8a31cdf103098714eed99ed884470b7be23..3d6014176c0597bfede7a9c917eb048be85356cd 100644
--- a/include/configs/A3000.h
+++ b/include/configs/A3000.h
@@ -172,11 +172,9 @@
  */
 
 /* #define CONFIG_SYS_MONITOR_BASE	   CONFIG_SYS_TEXT_BASE */
-/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
-#define CONFIG_SYS_GBL_DATA_SIZE      128
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 
 /*
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
index 56109148cfe855ecedc2f47ab109b349e9f68f55..6f12c8ddc01363a1593630f99ee2aa8a4505ab09 100644
--- a/include/configs/ADCIOP.h
+++ b/include/configs/ADCIOP.h
@@ -114,9 +114,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
-#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
index aa35cbca963059ba22ab0abd95db7c847bad266a..e7c6f968368598942af3dc302621a5a12aa9c52d 100644
--- a/include/configs/AMX860.h
+++ b/include/configs/AMX860.h
@@ -138,9 +138,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h
index f1ae16c436a2153875d6fdb9caaf75cd9b336f2e..9e5490d1df436c9cb60131bff995bd672b1577b0 100644
--- a/include/configs/AP1000.h
+++ b/include/configs/AP1000.h
@@ -209,9 +209,8 @@
  */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x400000  /* inside of SDRAM			 */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index b846afcc0b517d9427be8fb1b87cfbb940886d62..0adf3ed2a0237a31939411f498afa2ffdfd4060d 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -420,9 +420,8 @@
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* reserved bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
 
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index b4ff7188de538bfc192a7e33829b28d54d3a55ce..4963e9f688ec915563b77f421f1746b6ef799a1c 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -266,9 +266,8 @@
 #define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 480051b16bde2c033fed15e1a5b183870816456e..ee80d9d8f23c06146f6869ad081253ad662d339b 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -324,10 +324,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index dda6baa7ff6a9d7a12579cb616c60cb4c2c6b1d5..78757ecced285027d2d0a8e54bdc7d838318b0b9 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -191,12 +191,11 @@
 /* Memory */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index a1c530b71b4ad4bbdced4d740ce90b4e8ba5930c..48e6df5c279168d312ffcb00fba1626f3f46ffc3 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -170,9 +170,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
index b5c904987b85812a7c891f8f6ab336c42d329d69..e05099281728fb24b792ce8a5099de65f4edb122 100644
--- a/include/configs/Alaska8220.h
+++ b/include/configs/Alaska8220.h
@@ -246,10 +246,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in DPRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/B2.h b/include/configs/B2.h
index ca7350dc40dcc6d2885bcbee6cb9176ef9b5a277..7846a925c8649d5fa5f84f32b97d3eeaaa842add 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -53,7 +53,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CONFIG_ENV_SIZE		1024		/* 1024 bytes may be used for env vars*/
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024 )
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index 9250ef3d4cdf7c8b88a084054226e73aebaf1aaa..1497cae095422ecb11cea4ef4c35e9626becbc4e 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -199,9 +199,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
-#define CONFIG_SYS_INIT_RAM_END        0x4000
-#define CONFIG_SYS_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE        0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index d0517043cb0d554aac87bf6d3c6f08ae519bbcce..a833893728180b9622ebaea6c0107d79d6fbc877 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -384,13 +384,12 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-# define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif /*CONFIG_POST*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* Bytes reserved for initial data  */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index 7d928eb6d5f469418e47872d7dd5c97fb4ce11cd..8398b290bf28c88f718b18ad581a113af84cbc68 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -150,9 +150,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
-#define CONFIG_SYS_GBL_DATA_SIZE  128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE   0x2F00  /* Size of used area in DPRAM  */
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index 9c55805f1353624795215be53ba8d47ac7c17377..b27ef64fbe4cc3db19b0da03f9347a521d269f18 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -223,9 +223,8 @@
  * Definitions for initial stack pointer and data area (in RAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
-#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index ad36a14c6d0ef44bac980aba772fc7ea9d2cb1ce..ac70d158e7eb4a03887b639138ec279803e68ede 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -514,10 +514,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 3e973f2cc0273216f204f88ca7ddf527b6763cea..daaf62440c5b1a43f51a2e151835937594db6a54 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -286,10 +286,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index 486a4e0535c7bb2f18c927bae67c46e029b46f43..6a88d26511d67f3d45d966741f4ede66e0310f74 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -153,11 +153,10 @@
 
 /* Size in bytes reserved for initial data
  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index e4d8f9c5f9ad5ddaf8438561d528acb1bee04d80..99ace67a2f3fa07957aa462f6efbee435c3abc1e 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -259,9 +259,8 @@
 #define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 6b2986de896c68c9a76259f523a13949358de86b..426fc57a650017101da5df6f4f887e86afaa7e7a 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -335,9 +335,8 @@
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
 #endif
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 908b872e60ba46e1400e559538460b9883ecfa14..8f48ded2385e32c0c72e88cd316736f5e37ef74e 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -396,9 +396,8 @@
 #define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index a2b8d7235e57da6e8176d55fe62c753aceb5e379..a042abf1574da90a6914d6814dd4bcec968f2166 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -388,9 +388,8 @@
 #define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 7fea5e315e6cc5d8016be8e4be66aee5e65533f7..9b99ba8664f3ed241e900b30b46dcdb179fe731b 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -391,9 +391,8 @@
 #define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 37341cbb990f1a93f770690bd0291e74913f388a..92ffaaaf19e6a19b3d860c1382ccd8863f556ee1 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -266,9 +266,8 @@
 /* #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
 /* #define CONFIG_SYS_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
 #define CONFIG_SYS_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 5aff74c9d09855eac5a16aeed252b731ec77b9a3..b2ee87329544083a6fb3519cf6820012febd81a5 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -249,9 +249,8 @@
  */
 #define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 233d36b6d6797c002580d7c43e7999ddd8fff471..ab64adae0e995ab4edb5763806259ba5eaef20b5 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -296,9 +296,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 560e4491ab1bce20ecaa20ef219c32986eaf9c96..2b1716afeefd64f7b54f492c62b8f94703cdb339 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -311,9 +311,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 6ababa1c50017fc5460f81fecc96edb386717e93..885d42b337ef2c0c50e114de6636cd90c232985a 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -228,17 +228,15 @@
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE      256  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 #else
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of On Chip SRAM	     */
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	     */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #endif
 
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index 8e19aeb35cbe03a2d42bce4cb2a0fc9010e73341..a5c2ce5e87931f7793483035f2bd305770609fce 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -141,11 +141,10 @@
 
 	/* Size in bytes reserved for initial data
 	 */
-#define CONFIG_SYS_GBL_DATA_SIZE    128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
index fc2727ef4731102c5f1915a283ba005cb487c9b3..3706071c996131274a85be34910c8ffc68101bf2 100644
--- a/include/configs/DASA_SIM.h
+++ b/include/configs/DASA_SIM.h
@@ -115,9 +115,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
-#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
index 26bb6490a608504adb470ab3511f83bb6c07ae08..dbd224cc2c6354f843912a79a9c7bd46dde2801d 100644
--- a/include/configs/DB64360.h
+++ b/include/configs/DB64360.h
@@ -352,9 +352,8 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 */
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
index 74312cd9550db41600b768aff2f817bed9d7e058..321692bc5095a76928bc9ac86606481fdb13ddcf 100644
--- a/include/configs/DB64460.h
+++ b/include/configs/DB64460.h
@@ -290,9 +290,8 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 */
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index cb110e35ae7d62b482073eca7c9fa730ae5a3f85..ecdf93ffc0742d2d411f403ccdcdedb4bc300f4a 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -228,10 +228,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index d99b8409375a2aef9efaba199971c74bade4e013..1493f750db579ccaa06a02c4b5aa92038d43d5e9 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -286,9 +286,8 @@
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index e6e2b300caaef922954efa233c0b848a14e649ef..ceab60485885af1d1f6df7a4b3097710da533085 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -79,9 +79,8 @@
 #define CONFIG_SYS_INIT_RAM_OCM	1		/* OCM as init ram	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index af57fb9662cd737c589b91870d161ba63c848399..0333925792a6836bc40bc6dc3c130a151208f064 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -153,10 +153,9 @@
  *-----------------------------------------------------------------------*/
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END		0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE	64
+#define CONFIG_SYS_INIT_RAM_SIZE		0x10000
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -209,9 +208,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index 7e940b8db4bdbb9f4677922d43bf9901df4beb90..8cce70c11b86ec903e25d33f573d1e6d35665087 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -176,9 +176,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
-#define CONFIG_SYS_INIT_RAM_END        0x4000
-#define CONFIG_SYS_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE        0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
index f38160a2ba9c75342a7c9484a6f4b729774a9d9a..c6a17b039baa8f0b9dcda879d67de19798a8cc74 100644
--- a/include/configs/ELPT860.h
+++ b/include/configs/ELPT860.h
@@ -169,9 +169,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h
index ec1cc4eb117c1ae0f39ec52f8ce12177f5c37de6..a0acfd2697ee3d1c573eeec3b23127abd3e43292 100644
--- a/include/configs/EP88x.h
+++ b/include/configs/EP88x.h
@@ -171,9 +171,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index 42465da9b249bc209a71d0be63726fbf5ee33c20..8a0f850b7a87221811a7541c305d81ef9724d02e 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -352,9 +352,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000  /* inside of SDRAM		       */
-#define CONFIG_SYS_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
index d5a3cd3d76d00353daa4e9b4aabb5c83a4928338..841bf11cfc73d492454b1983b70d0ca6df8f8bbd 100644
--- a/include/configs/ESTEEM192E.h
+++ b/include/configs/ESTEEM192E.h
@@ -120,9 +120,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
index e890a9733285e2cb782089c772463447e50b3eac..c4270936a6e2be32a7f0913b8541407d7ecf83aa 100644
--- a/include/configs/ETX094.h
+++ b/include/configs/ETX094.h
@@ -138,9 +138,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
index d312811efd69b271e990cf80d0088729c751b814..3fda551a0bd9ed35c43f8572f250612150116982 100644
--- a/include/configs/EVB64260.h
+++ b/include/configs/EVB64260.h
@@ -162,9 +162,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define	CONFIG_SYS_INIT_RAM_END	0x1000
-#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_RAM_LOCK
 
 
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index 1489d3001ba863cb5694ce5e1332dcfa7295b6ab..f7b5bc9605af29496295191d75d08fce116df811 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -200,9 +200,8 @@
 
 /* Global info and initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM	*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index 97958342bbba7738f42abe0732552d04b0469cfa..57336f9fc80178a0e0281945ff3d8afc1f5b35c3 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -170,9 +170,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
index 9e2b1a45485a898010064d5e979762e04b9e2fac..438d19ecf420373ac68986c7b8b4137e14c71060 100644
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@@ -117,9 +117,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
index 12144cdb1a01938b1fb35332af2c028149339246..339bb59e7973e44152a997119096107bdd0e08f7 100644
--- a/include/configs/FLAGADM.h
+++ b/include/configs/FLAGADM.h
@@ -128,9 +128,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index 1a3d2f8f22d81aa9c8b32112474ad6e5456870f2..38d905ad458381473d48c94ca72c1d75157e3742 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -167,9 +167,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index 20e618fa4f5b6b5345e789d592979338842c1808..ca0b1ccd458e78b49c2a4099b4f7256eb75bb5f3 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -167,9 +167,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index 00f27ccfb9f6700e52031ad6123d9c937655bc51..af602ffeaab5983e3b73e2db09a1afc2ec99caaf 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -354,10 +354,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index 915aff3f1f90b680c6bdf2b3e9b77a47b569301e..68a0cfdf7f266afc847d6be6dbbf83a3da2686fe 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -382,9 +382,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
+#define	CONFIG_SYS_INIT_RAM_SIZE		0x2F00	/* Size of used area in DPRAM		*/
 #define	CONFIG_SYS_INIT_DATA_SIZE		64	/* # bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index dc925af6d5d3e304ae1e466149fd17acb547214b..c5ca279d7d6771e681d0ceeb4bf7ef0d2e458b04 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -161,9 +161,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 8a313240e2060b209d8073b2b8aae7b6608bd6f3..a15e686d28fafa324d66cb3cc791ce97b8b48aa2 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -450,10 +450,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
index 6cb19c5f70c7783b8d40c6bf87f32345ab9e7efc..c684cb847886f6736a76a36a2f85310459c53895 100644
--- a/include/configs/HIDDEN_DRAGON.h
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -126,20 +126,18 @@
 #define CONFIG_SYS_MONITOR_BASE	0x00090000
 #define CONFIG_SYS_RAMBOOT		1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END	0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_MONITOR_LEN		0x00030000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #endif
 
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index 863204e426d1ed6b27bd60dac33cb73481a039c9..827ecf26e447944d18322777f89fa1654e975700 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -323,10 +323,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
index 56331770890c5fa8a412036531edc078915ec450..27bd146e39e0bd22f53f77525ed3136545a36b0a 100644
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@@ -183,9 +183,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index 3fa6130c02dce3221b899a1067ec49808902f38f..b011d50efe2d977f9bc2a35df855831602f1219e 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -187,9 +187,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 1b90a6bf00c136c9184b91de1f4b8682607798ca..85522504129c29710eb2e701d2b5a22de1c75c0d 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -293,9 +293,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index df7ea9ac2e8d9ba7e526fc5ec5e229d7f7e66d03..ba8d6337500a15c59ab11f6c993706bf443c1db2 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -151,9 +151,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index 281d0bd3078e39497017e8e1b3e9f662756939f7..0af43b667d25e365f1a9b1bb07c10612cb356846 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -246,9 +246,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index e651658f324026af7b72293f41c24b5f690e9b7c..49c65107032cc65bf68ee8dd9b66a895ed3c505e 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -231,9 +231,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
index 6444bd1915413e494d92c80f2a201a80439e3fe0..b82795479ac18c41295346c0adb17f34daae3377 100644
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@@ -147,15 +147,14 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
 
 #if defined (CONFIG_IVML24_16M)
-# define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
 #elif defined (CONFIG_IVML24_32M)
-# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
 #elif defined (CONFIG_IVML24_64M)
-# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
 #endif
 
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 1ebbc4521c05549c8129fda60c5740bad5dc4040..9b0c32ab713d2f96d4a5215120eb24f273cdecce 100644
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -143,15 +143,14 @@
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
 #if defined (CONFIG_IVMS8_16M)
-# define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
 #elif defined (CONFIG_IVMS8_32M)
-# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
 #elif defined (CONFIG_IVMS8_64M)
-# define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
 #endif
 
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index f54a3937a0f034b314e0ac875c32f4cb885e42f4..bc5d761f8abc4468ef1acafdad851812009ca0a7 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -275,11 +275,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index 2a1cc5838fe303e454653164dddac0d5d08cb18b..c38e0d26dcd24722d8375fc4c42069415fe8ddb8 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -59,10 +59,9 @@
   /* ... place INIT RAM in the OCM address */
 # define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
   /* ... give it the whole init ram */
-# define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
   /* ... Shave a bit off the end for global data */
-# define CONFIG_SYS_GBL_DATA_SIZE	128
-# define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+# define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
   /* ... and place the stack pointer at the top of what's left. */
 # define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index 46b91754849b36800ea5a8104651355b53ab1e29..fcf66b7bc7a13acad742279cc3aa7e9bd2c9ec7f 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -80,10 +80,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM    1
 #define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END      0x2000	     /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 #define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index 9702d63eb8114ea4dd09e9b1137069c2a0d81af0..c0035e65deeb7e650a786693b9a98d6495c4d1b5 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -139,9 +139,9 @@
 
 /* List of I2C addresses to be verified by POST */
 
-#define I2C_ADDR_LIST	{CONFIG_SYS_I2C_PICIO_ADDR,	\
-			CONFIG_SYS_I2C_RTC_ADDR,	\
-			}
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					}
 
 #define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
 
@@ -211,9 +211,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
index 9613ed9a824f757ffb43e4f01267b09cd8eec021..5084cccad81f915381c5923dbc3073e0ce8c45c7 100644
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -149,9 +149,9 @@
 
 /* List of I2C addresses to be verified by POST */
 
-#define I2C_ADDR_LIST	{CONFIG_SYS_I2C_PICIO_ADDR,	\
-			CONFIG_SYS_I2C_RTC_ADDR,	\
-			}
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					}
 
 
 #define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
@@ -227,9 +227,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
index 7c58f684b8a3529a2ee36fb17a571fed2f83d68d..0f4ea418a71151fe1f7285d8dfca451b9a5a5362 100644
--- a/include/configs/LANTEC.h
+++ b/include/configs/LANTEC.h
@@ -155,9 +155,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index e6632acbe797a5cf6f7934bfa25f8d11b5cb2d36..a45cdc1bb96eb513fdfbedc3902afe4d835d1983 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -146,10 +146,9 @@
  */
 /* Definitions for initial stack pointer and data area (in DPRAM) */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END		0x4000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -208,9 +207,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 887bd635d6ad958b770aceaa25daaa5c3dfc872d..bb3b474bd8c1f3a27265c36eb043f638b42cae43 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -207,12 +207,11 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
 
 /*
  * Start addresses for the final memory configuration
@@ -303,9 +302,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 5c0dc842aadacfb96cc422e1e70865ba8ebff5a2..cd12d2b7a4f3c1755e5158b6a79dfd21ffd55e60 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -167,10 +167,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x21
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -238,9 +237,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 33ac2859dfb17afb20377b5230150c5757444b60..104fcdeb8d71ffa7b3de87944c3f5bde03649779 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -109,9 +109,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -167,9 +166,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
 					 CF_ADDRMASK(2) | \
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index b5af493b804ee755c4b94966b7c48186d63708f4..f2f315940cdcca8f80e1d22eabc15bf469766a09 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -167,9 +167,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -228,9 +227,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
 					 CF_ADDRMASK(8) | \
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index 206d1152ee47f0d16b0b9712e022f82cded231a6..dd8a56011f78876f8199cf0f1e66b1d18b9ca898 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -135,9 +135,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -181,9 +180,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
 					 CF_ADDRMASK(2) | \
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 798949cc5608cb3838860e04d93838be199a8647..992d738cbd4dd672c414e1125d178a741feb89d6 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -187,9 +187,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -231,9 +230,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index f704bb3ff7c6ba8f82ef36160f47f31aca5f85fc..b3c774f9c74757bdd0ad0b5195de1bb3ca3203cd 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -163,9 +163,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -213,9 +212,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 981670ac069bde2084da8670c2eb7b494a408a52..56a760fc8f0701fac0717574bb0ebbb26cf7673c 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -173,9 +173,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	1000	/* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -222,9 +221,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 46f60bf517a3a92681a3ebd223c292a9574ce397..0c104805d749764e763439373c21615c47faf335 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -154,9 +154,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -211,9 +210,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index d983a8fedb7060b8d75a6502996f232931023f62..d205e7c1749ee868bb3255619ddd7ca0c03ed583 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -167,10 +167,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END		0x20000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -234,9 +233,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 159b178f401757e3104912d951ee69a1a5c09918..7ae0faddac03d9f540b844884d8f16caa8202d8e 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -162,10 +162,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -238,9 +237,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index af1988ce0a45745eba35bf3b7c3b94aa4325f3d9..7086a1bdb712eb485877719742304a1045ebe01d 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -162,10 +162,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -238,9 +237,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 1ff80ee0d679eb6f68e874e754a3f19c834ad099..37715c50c2492f9923a8dad97b6532cf43256e16 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -220,12 +220,11 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -310,9 +309,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
 #define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
 #define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 1cdc37350b5af04cd47d8230d67c1690bf6eca54..86faa3df8f4da23ba3d8b7413eba0b17cf1a76e1 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -279,12 +279,11 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -409,9 +408,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
 #define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
 #define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index d0077667f3ac1b996284bf577628bf15b6a20a60..5f6eb553ebe936c1152c92ed88ecc7b201aaf944 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -210,13 +210,12 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 #define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM1_CTRL	0x21
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -287,9 +286,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
 					 CF_CACR_IDCM)
 #define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index f23b8b0efaeeca48394fc3df3403e0ebf70637db..e178e3509726f3f7e86ed10e4844b3631f4fb885 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -196,13 +196,12 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 #define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM1_CTRL	0x21
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -273,9 +272,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
 					 CF_CACR_IDCM)
 #define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index 3b4d60c45086a72019816bae1d9df04c862d064a..cb5b023b58fed55c7255c3e540ba8842e78a335a 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -144,9 +144,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
 #define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h
index 6964bec1be9ea6e68dd3e0482bb31ea208b18097..969ba7e245f00ea6f557a19acc97eeae470efcbf 100644
--- a/include/configs/MBX860T.h
+++ b/include/configs/MBX860T.h
@@ -98,9 +98,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
 #define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index d79b7029a2de9cebf444fd335c9f12460033a6fd..9b83e21a1f70e5956154aadeed740cbb91d4d4c9 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -142,10 +142,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM    1
 #define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END      0x2000	     /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 #define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
index 6ad0658cdac25640f5859fab575ca08eca8e8a4e..b9c163856bbb2caa0c46f065036b6a03c1928fe7 100644
--- a/include/configs/MHPC.h
+++ b/include/configs/MHPC.h
@@ -179,9 +179,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 58764d0dfbd2b63c7342f9dfec1829ca2accdc7c..ce9273b6f7d06cb3299759dcc7a71f39739d2814 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -308,9 +308,8 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for POST and BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
 
diff --git a/include/configs/ML2.h b/include/configs/ML2.h
index 8579f96d286208c59725701d70f0e9fa0230e659..ed783876efbbefc6fed17a1815475222634cbf86 100644
--- a/include/configs/ML2.h
+++ b/include/configs/ML2.h
@@ -211,9 +211,8 @@
  */
 
 #define CONFIG_SYS_INIT_RAM_ADDR       0x800000  /* inside of SDRAM                     */
-#define CONFIG_SYS_INIT_RAM_END        0x2000  /* End of used area in RAM             */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM             */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
index 69c0cab1869edbb9f1392cf57e462e223e4178b8..9529c8750386b62782a51da345ed64c60023cf80 100644
--- a/include/configs/MOUSSE.h
+++ b/include/configs/MOUSSE.h
@@ -157,9 +157,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
-#define CONFIG_SYS_GBL_DATA_SIZE  64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE   0x2F00  /* Size of used area in DPRAM  */
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 05caf21644d723b1fc07363ac52639c76d0c0607..2225b46b281eb05250e320f8806dbf791f7524d9 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -348,9 +348,8 @@
 #define BCSR_PCI_MODE		0x01000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #ifdef CONFIG_SYS_LOWBOOT
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 97202df1602cabb2b500b4b0c71e90f7f87a270e..579447336868c3541754de43745128b809d37b48 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -382,9 +382,8 @@
 #define FETH_RST		0x04000004
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 2eab1c4db7e0675173d3c6374244b1b1a9a6d2dd..3ff175c6ded81cd372025096afd54e3cd3ed5b2d 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -212,10 +212,9 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END		0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000 /* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 1b2bebb1cc441aca4a55e718368e8ece979af392..1201133e2b0bf06a8c03d5702799c739d7a406d4 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -208,10 +208,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 17ce3bc58467bf2f8a514b7bb53c05c66062fcdf..6476c4c430459a9b6980751be2024d2481415d6c 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -191,9 +191,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index abbb92a71e9214f65ad10c92e51493238036baec..1191eea106c00dcfd66a6db22060ae0e948b6a00 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -165,9 +165,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 6009d44be0630062e459fda1c811de84b8057f80..affa3a9cf8dacf3e5dc00ccfd6104f7c42e669e0 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -152,9 +152,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 5682787c8b950ca46627ba6683c008dcf534510e..45b6b5f8545885cdba8cbd9a2c466405482acbf9 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -193,10 +193,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000			/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024)		/* Reserve 384 kB for Mon */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 5d10a5e060f04807cf9fc3833fa97d33f39af7bf..de233ffe627a3ed8243f7133ae98e72367c478c2 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -306,10 +306,9 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index bc644bab05f90e0670b1c311ac9aac7a6abc56cf..7b82c43dd287eb0ca91a6ac0bd93840b55c019e9 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -181,9 +181,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index e9a64004e8d449ddfc1c3469d30461e392336280..b0cdc02c1dea4f344dd4f081cdc0c75ad6541af0 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -172,9 +172,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index fa0da48c258ab8435ec26c9e0e977a4d8bf91204..c237991adc55b666959d13f7b4b0c099eb8ffc7f 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -215,9 +215,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 9d99a9360bf6b16e470d249ef318499d14bd6ce1..385c7c321b06af129fd567edad3b8a65c52be1a3 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -238,9 +238,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 8b8f4674cd3b52380abeaf77c871c8e4e6e9fa21..8410bb77ebcf58e9042c7581e44d700e0ce0f8cf 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -303,11 +303,10 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-		(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index b1ee07bfc2c78ab51c9ca0acccc55d5e8c83980b..9386f648859075f162f87f2013bab6882033b96f 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -232,10 +232,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index cc52a67cec22cc0271b4c288b086966948c60c87..a968949814945660e9e471092d94512634eb2289 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -164,10 +164,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 037aae75e92270aa9e933102474519f5e3e7fe4e..12ce6f7e66b9953546f32b3fbc614b42ce57ab3a 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -254,10 +254,9 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 0b69885fcc31c592eda8430e2e3561137b15f42c..e94822e5b83e120766cbcbc16d8d9b6992ec4787 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -203,11 +203,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_INIT_RAM_LOCK      1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END       0x00004000      /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 5d21d116f99f0128be09e7b87e53667d1a267835..b221a5cc9a9ec5f2139386f0a4f5e84a71d3f909 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -273,12 +273,11 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 006868421752ecfbb9b20bcfa8b5900cdede3a4c..334a4106d2d337abfbfeff84ae95f1e580f0b3fd 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -252,10 +252,9 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 96f7383060c487c4a618b34228979b46e2f62c81..744e4a395f889afa69880827e76ee9bfed833229 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -229,10 +229,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index d6171b4683c05726b20044b8957ddcb850bea655..281918bdc9ec7c1e6061bf2a90380f05f3d79230 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -235,10 +235,9 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index e3a997e87a21367463e34e978c07d64112e66eb3..6a15da50c8254e690833cc8ba502eb8faf0e3bf9 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -268,11 +268,10 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index e8206ea8e6e64001096ba94fca2e56b15772d0ca..f949cc2b6f43f011782a8aaf5a99911e5360c81d 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -268,10 +268,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index c876e989498852535c0b43669a80a26c5aeeac0f..17dac6c74f02d3212dd1822a8bcebd7782868ad8 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -213,10 +213,9 @@
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
 #endif
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 9009e3c48733811230fd7a9c4637915f389ffc46..ab3ae5b2e3837388cbc1bb5f64dd3f913015ff6f 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -271,10 +271,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
 #endif
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
index e0bfd0881c5fe7894a5c3991d27675acaf8b58ba..27ebceb01f249743be26a7e2ff1162c3408f72cf 100644
--- a/include/configs/MUSENKI.h
+++ b/include/configs/MUSENKI.h
@@ -155,11 +155,9 @@
  */
 
 /* #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE */
-/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
-#define CONFIG_SYS_GBL_DATA_SIZE      128
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 
 /*
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index acc7187b22c33632a0504d16097ad87ea7d7706c..6f4d187595b1b08a3e15cf8e1d17150b6f01d61b 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -235,10 +235,9 @@
 #define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 04d97cd1dcdd406600605559bdae5ba9a6fd3c64..c201310f268179c8e8595f27df73806656082ac6 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -123,10 +123,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
@@ -324,7 +323,7 @@
 #define CONFIG_SYS_SCCR_TSEC1CM	1
 #define CONFIG_SYS_SCCR_TSEC2CM	1
 
-#define CONFIG_SYS_SICRH	0x1fff8003
+#define CONFIG_SYS_SICRH	0x1fef0003
 #define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
 
 #define CONFIG_SYS_HID0_INIT	0x000000000
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index dd392d0c0d0afe03737bd91b27574db379473d1e..3aed447e17aa10c13527efddd5d073cae5fd73a9 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -214,9 +214,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE     128
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Low Level Configuration Settings
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
index 9bf7fcbf8e32744f5375d70098f3a5c1520190a3..46151daf967b436ed5b9f74cc32b7eac836c7059 100644
--- a/include/configs/MVS1.h
+++ b/include/configs/MVS1.h
@@ -140,9 +140,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
index c125157449c631a7ab2a45f69d63e266f3f476dc..f7fd9b2eb039d3e7e58c0b03e7eedc231d897ad4 100644
--- a/include/configs/MVSMR.h
+++ b/include/configs/MVSMR.h
@@ -204,11 +204,10 @@
 #define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-						CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 60838925d4ca2e8741dbdc9a7c693b0070d6a4ab..8a6b8d06b4bb465539d3fcc74fa361d578da3d25 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -99,7 +99,6 @@
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* FLASH */
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index 62eef4631d356239e261cf952e16add5661f9707..04f0f0bc53e4b43ef7fbf234b4aff5cd15235d64 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -172,9 +172,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index db22ba3f2d9109d282c172ab4c9ca275ecc49f09..795c0f61fe6dadf95eabbc728b588f2d93d5d879 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -185,9 +185,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index 87000e6ddb0488d640625fd413d4fb5e27671a51..d02dca98fdb3df289da33d229ce15867fcbc3d48 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -173,9 +173,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index b7119fd3988b91de6f85ae6c86e1cfe0f302c726..a92e3a6261ad091b06ffc7dbb4f02e7278edb6c4 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -153,9 +153,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
index 4f76ca1b1a61e33ee75fa1c2568781f69c16991c..7e3ba2a1110b631897cd3f4698d03767b18b4ee0 100644
--- a/include/configs/NSCU.h
+++ b/include/configs/NSCU.h
@@ -175,9 +175,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
index e588ea3c0ae681222e7946af78ba26a4115260e7..bb0d3a3022e07d00ac95341954e04d836c7cf57a 100644
--- a/include/configs/NX823.h
+++ b/include/configs/NX823.h
@@ -117,9 +117,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 03430439cff9f535e252e60f5ce4db8b3889c0bf..65a366ab041869a292f06d11aa8f6ab9b7bd0ba6 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -297,9 +297,8 @@
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index cef1117578ec74b4cda9dff123bfb6cf63e8c55c..c2e3b2bcc1e272650e83324dc8d1e0417baef04b 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -293,9 +293,8 @@
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
index 9a0c558ecefc224a2064d9164ec02ce6ae43c1a0..bc8e718f17f7e189cde7d6716ac21a7fb33687cc 100644
--- a/include/configs/OXC.h
+++ b/include/configs/OXC.h
@@ -148,10 +148,9 @@
 #endif
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 1a4632fc8f1f5d3a29af35006996ece5123a7282..6c8579f9ec1b2361350bb758075baba9ba6e662c 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -153,11 +153,10 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_END		0x00004000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index cff0ed341c88b92161884382cfa12e69395bef10..b99f383ec1e58681986b6a9cc9171ded16281f9f 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -211,11 +211,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000	/* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
-						- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon*/
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 8c7d5287c819f720b5210fb1eeadb1ea1aec53b3..0af21528d9a82345bc132825cd85e1108dc1f445 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -272,10 +272,9 @@
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
-#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index 47b75580ddaf9b544a56978eabbc8e9451e57b25..eb641f556f132526d990e1e500d0d73a437b0150 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -185,9 +185,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define	CONFIG_SYS_INIT_RAM_END	0x1000
-#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_RAM_LOCK
 
 
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index b07cac11f4249ae717a374f686a92a3b4362145a..da2d60250660d6fbbd23cc4e0dc826870ed5d9c3 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -132,9 +132,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
-#define	CONFIG_SYS_INIT_RAM_END	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	128			/* Size in bytes reserved for initial global data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CONFIG_SYS_INIT_RAM_SIZE	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 #define	CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
 /*
  * Start addresses for the final memory configuration
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 28769b3abcc0e28a85b0d6e435ae6e43f18d01aa..6be5c2570a0204d7d680b72ed14253091ec5c6f5 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -307,10 +307,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 3e7e74bcf4fc99a37d1348be47dbec22a49c1bfe..70775e75fbbd632971f14c817c32fa83d68fa055 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -60,12 +60,11 @@
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index d0ce92487ef39ac5ddfe7946e2e5350218feeae5..e778c5956635778023b2eac9a7f92c274a017b6f 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -140,11 +140,10 @@
 
 /* Size in bytes reserved for initial data
  */
-#define CONFIG_SYS_GBL_DATA_SIZE    128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x8000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x8000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_INIT_RAM_LOCK
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index 8f7ec023d3c9eaf8d076dce053e2973fc68a949c..48911b7be44917c57ed4a980a079c07016be989b 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -142,11 +142,10 @@
 
 /* Size in bytes reserved for initial data
  */
-#define CONFIG_SYS_GBL_DATA_SIZE    128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x8000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x8000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_INIT_RAM_LOCK
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index e3cf94376c06194ba1ede59fa1b2797a2267ac8b..2dc6057f80a960c0c4ec4af3bfa1a602126c2f57 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -258,9 +258,8 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /***********************************************************************
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 8e8c0491eecc97a045d6e3e99a3b25207f17f7ee..b466c4b05a28b01deef2eabe7b2f0b9a589c387b 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -62,12 +62,11 @@
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*------------------------------------------------------------------------
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 3844e48c485268cb1c433674d4f8e1488b9f12da..dcf62934045b7515ff89f0ebe9ac136c15a1f89d 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -368,10 +368,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM  */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM  */
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 5832307f6da6b980bcd847f3f6829fd48666c1d3..8354e70fd0706b55b4d5779ceb36ffe034effd37 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -233,11 +233,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index d26254f04baa1b5bde5b312b19d999af6a288712..501f691ea523c2ec0f0ab18e4412ffeafdb13c23 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -293,9 +293,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 3053ad4745c12d5bf06e1c787d4ea5e77b17052a..1af043df332fc92389546b33d63d7ac3ba206bf6 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -287,9 +287,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 59633348996febabda2ffdcc5fe8b9ae1945df45..1e2089fb5a9eabff9d2af155e90e180dfce0032a 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -165,10 +165,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 1559fd660c45b660bcc72a4ed5f9a27707d7c77a..d3e8f412e21356b88956de5d9998bb233933785a 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -168,10 +168,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)    /* Reserve 512 kB for Mon */
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index b1d0ea5c729571695469bd0d670dfa8ea602a9c7..c2db5ea5ddaebd846bdb10b04bf59c1b546994b9 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -328,12 +328,11 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
 
 /* End of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_OCM_DATA_SIZE
 
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_OF_LIBFDT
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 74b656c7613536ef132e418983fe6af6824cf8f3..83cee9654939fbd05095b9618efbfbbcc053d2c4 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -270,11 +270,10 @@
 /* inside SDRAM */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
 /* End of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_OCM_DATA_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* bytes res. for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 7585e6ec15945d0b4fffc07004fee085ac92489c..4eb0735fcffe5462b2ca07cf52d6b73397b61f77 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -88,9 +88,8 @@
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM                  */
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index 01878abe8bab8248d13e248ee34020545bb2e16a..7f2f1131b0acb386600e0b68caead17017eec4a3 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -152,12 +152,10 @@
 #define CONFIG_SYS_MONITOR_LEN		0x00030000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 
-/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 
 #define CONFIG_SYS_NO_FLASH		1		/* There is no FLASH memory	*/
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 3bc3d70bdcb1a3bafe78d7f3d60ed94a365954bc..a14bd0e65d322296c035e4889aa4cef22dd7007e 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -531,10 +531,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index ec2e0c938e9ab5a72ea1c472027643ff930eaca0..36efbf2e0d58fbf03cfd86e5c8247091f7c6bd15 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -272,9 +272,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 3d455c4b0f7547e294f638eb74977aa478762772..5c6ed07ba66edbdc227a4dbd7b9601abb296e140 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -272,9 +272,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index 99ccf08b405bc9ec9ec8856415a20f53cd79127a..b0bee82dff7dfd496b1b914dcc7141197ef05015 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -181,9 +181,8 @@ CONFIG_SPI
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
index a0355f10564240c383c1574a430acf39d726545e..a8e9a4a31a57132ee28e24ac547bc2ffd0055535 100644
--- a/include/configs/R360MPI.h
+++ b/include/configs/R360MPI.h
@@ -195,9 +195,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 5a23e56dec51525663cb8884bdd7eeab24498dcf..40980fe5026ab4fdf1a7995b0be36f7dd3ab74b9 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -167,9 +167,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index e8e8a5d94390697ff5f200878b35fc7b922aabfb..267ece16c900de566bde1e9642376e1435c2fc17 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -183,9 +183,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
index a7609cae69d19f2d036d16b42cd1bb61d488699b..74926d8d2a79528c143bfa3a168692f2e0846bea 100644
--- a/include/configs/RPXlite.h
+++ b/include/configs/RPXlite.h
@@ -119,9 +119,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
index b895f05aa40359ef4dc7dbace197a048a271013c..7b561cbd1493b8692a12f521bcaea0553beea1eb 100644
--- a/include/configs/RPXlite_DW.h
+++ b/include/configs/RPXlite_DW.h
@@ -194,9 +194,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index 2ac764dd268a09535ef1f32769c67100ebdda3cd..5c19bd36e4ff2b52b9357c9f67633f1fd651e448 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -265,9 +265,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 9530381f5a05b4e346b2d5e2b38da35096f2ebe8..7dcc14c82080c0dc2ca6eb622d4104775c99e863 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -196,9 +196,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index cdfce6aec6af901fdbce8952e3c9106b3b54af3f..4844fba885fa5ea70bed24aeb2dc51324867a112 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -241,9 +241,8 @@
 #define CONFIG_SYS_IMMR		0xF0000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index b91dc4bd26d5688a50edb45b020c521335b254ae..fd9bacc499445a67e1e95f5cdab946d78b421a42 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -193,10 +193,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
index edad4595ccbdb353dd12322509c1161235259040..ec26290be0e4e098e23e44cc6ec8fa55fdaafee1 100644
--- a/include/configs/SCM.h
+++ b/include/configs/SCM.h
@@ -325,9 +325,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 15d99f99875fe26ee1d1df60596a9c7e226edce7..30a8e41e62a1ba539c1e9fa77cdd0dca497afd4e 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -103,10 +103,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END		0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
index 259f8ab5e16482c2ebd16103ea9a06310e920182..833b18a8fdd75eb5b4fa602410d1ee5f2d4229f0 100644
--- a/include/configs/SM850.h
+++ b/include/configs/SM850.h
@@ -125,9 +125,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h
index ba3ada13a5a5a868257c260f2d1812cc173aa48d..4a8acabf72c6261024f801496c0e36bd9186d315 100644
--- a/include/configs/SMN42.h
+++ b/include/configs/SMN42.h
@@ -31,7 +31,6 @@
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
 #undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * High Level Configuration Options
@@ -48,7 +47,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index b132a780735b1420d07222d5939fa912600132b7..fba5b5e2aaa60c4bdb182f3a74bdab0ade8dc911 100644
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -137,9 +137,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/SX1.h b/include/configs/SX1.h
index 61492766f638e4147905796505d6531dd3b6518d..01c2b3d50ce5f6720500dabfe181b412d333962e 100644
--- a/include/configs/SX1.h
+++ b/include/configs/SX1.h
@@ -47,7 +47,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index 7c3f8745cc012b168698717e955743178cd18e9a..774c98faec0f6e728dc90bb70b8357a629bcf3b6 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -205,9 +205,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
index f6107cec13e0f7b18c43b385748c38be925dec76..f98414160db5e2a483538a83e9916dada74b17ea 100644
--- a/include/configs/Sandpoint8240.h
+++ b/include/configs/Sandpoint8240.h
@@ -154,21 +154,18 @@
 #define CONFIG_SYS_MONITOR_BASE	0x00090000
 #define CONFIG_SYS_RAMBOOT		1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END	0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_MONITOR_LEN		0x00030000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 
-/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #endif
 
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
index 66a98c19c6a906bb13a5ef0b210603e40a37b43c..b47adcc3a9d54968787248403d5c9918b3d0a970 100644
--- a/include/configs/Sandpoint8245.h
+++ b/include/configs/Sandpoint8245.h
@@ -124,21 +124,18 @@
 #define CONFIG_SYS_MONITOR_BASE	0x00090000
 #define CONFIG_SYS_RAMBOOT		1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END	0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_MONITOR_LEN		0x00030000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 
-/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #endif
 
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index b69f015c7cd2c02e795c13d1bd794ec1e518c39f..c93b12ebf1c46f2191a72891f4f31b29700e265e 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -189,9 +189,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH	1
@@ -253,9 +252,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
 #define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index ad86e2e23a3f01ed7a93a26c6dfa49c74c724a1f..feaadf3649b929b6de7e5e8645d3f63d0e6cdbe7 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -251,10 +251,10 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 
 /* List of I2C addresses to be verified by POST */
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST	{	CONFIG_SYS_I2C_EEPROM_ADDR,	\
-				CONFIG_SYS_I2C_RTC_ADDR,	\
-				CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_SLAVE}
 
 /*
  * Flash configuration
@@ -327,14 +327,13 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h
index d849dbc2b9fc066b645555197a6de26f6ed11f94..72c652347f2a54882b4a63782aff9b58f814a794 100644
--- a/include/configs/TK885D.h
+++ b/include/configs/TK885D.h
@@ -221,9 +221,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index ab1773c3659eb6acd96310a6efe3a8c4f5ed27f6..2267d59d750000596defa8695b0fce49ae25df35 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -297,11 +297,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
index a9d9bed1d316826249da1f93b30750e8f189bd1d..d6ea22d746495f0a0d9b90d52503ab0f2aa02981 100644
--- a/include/configs/TOP860.h
+++ b/include/configs/TOP860.h
@@ -230,9 +230,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
 #define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 2612c7a50ba28f9415a9b1ac7b23adec50152d4a..c11fe8a3557658d3216fbd728c6aa95b1b39bc8e 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -370,10 +370,10 @@
 
 /* List of I2C addresses to be verified by POST */
 #if defined (CONFIG_MINIFAP)
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST	{	CONFIG_SYS_I2C_EEPROM_ADDR,	\
-				CONFIG_SYS_I2C_HWMON_ADDR,	\
-				CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_HWMON_ADDR,	\
+					 CONFIG_SYS_I2C_SLAVE}
 #endif
 
 /*
@@ -487,14 +487,13 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index b68d7a7bc112bf07280d7ccd033347fe13bf789c..f2a2e33664b2fee6becc49c172339f6e55b59f43 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -182,9 +182,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index 374300b1f69f09e5e34e9760e006e20a1184e930..f6b856c4b97945a084b02cfcd5c02a56ff8ca324 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -177,9 +177,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index 2104e03c22b90b40c991f93e2332edc058d0a262..36ecbd8b5227c1074f93497765cbdec452173c63 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -362,9 +362,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 063ca230dba8a391153a26e5f68007c2317e5e37..d1d9e8e68d3fe2700bc51c5406de6596be35e91f 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -488,9 +488,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 36399caac5604dd42c4cd534f72a5a057c55915c..7c9dd79e3d2163d803f940cab137bdd522e83bfd 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -151,10 +151,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index c97bf66c9b298ab63c4ccb756c786bb7cfb6fd8c..6114bb0104822956c91d227aa25482c6a9217d4d 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -167,9 +167,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 3e13f61ea598aa1e2b3e10289e91e060d5463428..3b520254a035e6f9daed6627b8217f700a820d71 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -166,9 +166,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 1bc286148cd6aed90c1c00234fa87b34ff699743..fd90501e36a05128413c7855e4096edc2729475a 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -171,9 +171,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 197ffdebeaa2c6f45fed2c7e61df011b971e2b13..3e3f6de20888d2c52ab0fab1c1472eb41195a3ad 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -205,9 +205,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index d5c116f5b8a0a970c7bf62b49f585efddce7256b..890d6d9d4ccf6f0e0b67aa2c0981d5fddecbe12c 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -243,10 +243,9 @@
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_CCSRBAR \
 				 + 0x04010000)	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor	*/
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index d3d0db4f176c5d4a8d0e977e01ea18a3d7bf336d..cdf4885b8c99e94ae25987d1f48a6e78eee68cb5 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -170,9 +170,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 0854d9544bf296e727223872feec7d4ef3aaefad..7ccc61470645df6ddec0f318cbc2e17fde6fe996 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -171,9 +171,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index c247737d62e35a374fa3ee39c06fee2da42739fa..0082e71e3a2d94900fc709769ea04327f2c60d06 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -174,9 +174,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 1b6d9cb73a5e39bd39a8236110c6849c287b97b3..6e891e7f1252d60bb75dca26982cbfa816eaabde 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -174,9 +174,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index a5018d5836dfefef4b6bdcf5a320fcebde40655e..8636ff4c19e66c2f435e8335ee8352d1c4556d82 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -217,9 +217,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 507fb2ffa746ec9726a9dae7a5f5e4551f414337..5204771e00335ccb40bc468e8aa1422b2d058b4f 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -219,9 +219,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index c518d6e747d9da4197014fbc48406dfafff8cca2..717b5cdd804ade55dfd129d738f2c2da5d6f08dc 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -246,10 +246,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index ebc81c40034f5ff798cc08e349c34aa79520dc31..ebe9e424c329ff25419dc6fd21f899e7b50d3019 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -101,7 +101,6 @@
  * Size of malloc() pool
  */
 /*#define CONFIG_MALLOC_SIZE	(CONFIG_ENV_SIZE + 128*1024)*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* BUNZIP2 needs a lot of RAM */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 026d2a4316700a56f28d71115764bd7051503860..f0c0bd9662c78917670059a1ef967ee05e3cb8da 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -377,10 +377,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index fddefb29ff86355dfa29d19b0ba11265550409a5..fec9df0da5ec390d82acaea5f8790d535cc214d1 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -258,10 +258,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index 6243afee0a919abf4cc1619fef4d1e1b0c5e0a19..c06909fccd7bae5900d517ec5028236a3e0e212b 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -298,9 +298,8 @@
 
 /* definitions for initial stack pointer and data area (in DPRAM) */
 #define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END		0x2000
-#define CONFIG_SYS_GBL_DATA_SIZE		128
-#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
+#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 9eacd82323afd2ac745be6bdf69642683a4e64d1..5d1c188499c3fd68e2b6457b426f6b06456f21e0 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -313,9 +313,8 @@
  * Definitions for initial stack pointer and data area (in RAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 6591d02bd26f45138f1f5d3819bd2e3a87737765..422a781a5cabb23a3c066f1e4461d64e653c4ec4 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -316,9 +316,8 @@
  * Definitions for initial stack pointer and data area (in RAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #if defined(CONFIG_CMD_KGDB)
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index e23ad4170af01cc1737246d92d50ea8aeb992e00..027a904ee22d10b299a319d0ad44c77f4f988de7 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -321,10 +321,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
index a0fca032f4706ff5c50658456d357b6279be31b0..0e340e898e099e34b6d894fe21d7faea42b10d69 100644
--- a/include/configs/Yukon8220.h
+++ b/include/configs/Yukon8220.h
@@ -257,10 +257,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in DPRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 0eabf37e58f6288e7a24d9b0933185dd4d292da2..265b1112fe694ffa05e5c38c96afb19d0c99da01 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -195,9 +195,8 @@
 #define BCSR_PCI_MODE		0x01
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
index 17ada0d9a528e1d57a62b3a01c53d740e1be16ae..5489bd831d5b725530fd34061d51e619ba22af27 100644
--- a/include/configs/ZUMA.h
+++ b/include/configs/ZUMA.h
@@ -180,9 +180,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_RAM_LOCK
 
 
diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h
index fcc556321ba5c41d4a797a6be76cf07db10282f8..f67cf067b90de4630c19571095e22dce9c44f0e3 100644
--- a/include/configs/a320evb.h
+++ b/include/configs/a320evb.h
@@ -110,7 +110,6 @@
 /*-----------------------------------------------------------------------
  * size in bytes reserved for initial data
 */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*-----------------------------------------------------------------------
  * SDRAM controller configuration
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index 24a04ebefb539f4f804d93d110ea5c459499b544..b5d20bd7b25d1386b2c58e2de042d28417041f19 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -79,7 +79,7 @@
 #define CONFIG_SYS_XLB_PIPELINING	1
 
 #undef CONFIG_NET_MULTI
-#undef CONFIG_EEPRO100 
+#undef CONFIG_EEPRO100
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -147,27 +147,43 @@
 #define CONFIG_PREBOOT				"run try_update"
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0"	\
-	"cf1=diskboot 200000 0:1\0"	\
-	"bootcmd_cf1=run bcf1\0"	\
-	"bcf=setenv bootargs root=/dev/hda3\0"	\
-	"bootcmd_nfs=run bnfs\0"	\
-	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0"	\
-	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0"	\
-	"bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
-	"try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0"	\
-	"env_addr=FE060000\0"	\
-	"kernel_addr=FE100000\0"	\
-	"rootfs_addr=FE200000\0"	\
-	"add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"	\
-	"bcf1=run cf1; run bcf; run addip; run bk\0"	\
-	"add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0"	\
-	"addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0"	\
-	"hostname=CPUP0\0"	\
-	"ethaddr=00:00:00:00:00:00\0"	\
-	"netdev=eth0\0"	\
-	"bootcmd=run bootcmd_nor\0" \
+	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0"		\
+	"cf1=diskboot 200000 0:1\0"					\
+	"bootcmd_cf1=run bcf1\0"					\
+	"bcf=setenv bootargs root=/dev/hda3\0"				\
+	"bootcmd_nfs=run bnfs\0"					\
+	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
+		"panic=1\0"						\
+	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"		\
+			"run norargs addip; run bk\0"			\
+	"bnfs=nfs 200000 ${rootpath}/boot/uImage;"			\
+			"run nfsargs addip ; run bk\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+				"nfsroot=${serverip}:${rootpath}\0"	\
+	"try_update=usb start;sleep 2;usb start;sleep 1;"		\
+			"fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"	\
+			"source 2F0000\0"				\
+	"env_addr=FE060000\0"						\
+	"kernel_addr=FE100000\0"					\
+	"rootfs_addr=FE200000\0"					\
+	"add_mtd=setenv bootargs ${bootargs} mtdparts="			\
+		"phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"	\
+	"bcf1=run cf1; run bcf; run addip; run bk\0"			\
+	"add_consolespec=setenv bootargs ${bootargs} "			\
+				"console=/dev/null quiet\0"		\
+	"addip=if test -n ${ethaddr};"					\
+		"then if test -n ${ipaddr};"				\
+			"then setenv bootargs ${bootargs} "		\
+				"ip=${ipaddr}:${serverip}:${gatewayip}:"\
+				"${netmask}:${hostname}:${netdev}:off;"	\
+			"fi;"						\
+		"else;"							\
+			"setenv bootargs ${bootargs} no_ethaddr;"	\
+		"fi\0"							\
+	"hostname=CPUP0\0"						\
+	"ethaddr=00:00:00:00:00:00\0"					\
+	"netdev=eth0\0"							\
+	"bootcmd=run bootcmd_nor\0" 					\
 	""
 /*
  * IPB Bus clocking configuration.
@@ -212,6 +228,7 @@
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS0_START}
+#define CONFIG_SYS_FLASH_BANKS_SIZES	{CONFIG_SYS_CS0_SIZE}
 
 /*
  * Environment settings
@@ -233,11 +250,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index c1bd4be9441cfde9f216338f11896ac4a146887b..5573dc7a32f73a9397efac5e97e927a2b9837988 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -84,10 +84,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xf8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of SRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128			/* size for initial data	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/actux1.h b/include/configs/actux1.h
index 91f6ff03f971b87aa8f9233f18dac3ab51b1adba..8886eff9e5625b83422759754f4a8aad751362cd 100644
--- a/include/configs/actux1.h
+++ b/include/configs/actux1.h
@@ -55,7 +55,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/actux2.h b/include/configs/actux2.h
index b9369383593c61dc28c1224ab9e50acd26e47ef2..756279e398dd4ba868a31e3ba6cafb9a0f49782b 100644
--- a/include/configs/actux2.h
+++ b/include/configs/actux2.h
@@ -46,7 +46,6 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/actux3.h b/include/configs/actux3.h
index f5ee8991023d3d4b0e8b9720149efb43c2960f4b..ad9173f347940f636f993f17be10c24db08c07d7 100644
--- a/include/configs/actux3.h
+++ b/include/configs/actux3.h
@@ -46,7 +46,6 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/actux4.h b/include/configs/actux4.h
index 8d70a268ce54d38952b4a02e8f349ff40e167ee3..04145c35c311eedff22de407d551037845c7a888 100644
--- a/include/configs/actux4.h
+++ b/include/configs/actux4.h
@@ -46,7 +46,6 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE		128
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 10ffb2e113b8df7140838acd91778e24474d5fe9..fb958fd943a57c4bef86b29c51984b4d46dde8ef 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -271,14 +271,13 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 24484fd0c87565dda50bf21ecaa1bdf6831baab2..36a2a461d16fb94071dc0b89f186b1d32483515c 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -42,7 +42,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -167,7 +166,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
 
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index dfe7802119f7df75ac519b53f23f3ef3d55738c6..d93e505907c9b112da73958bf88fca9e0e3b7fc0 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -64,10 +64,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM  1
 #define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 #define CONFIG_SYS_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index a9045d8bade79b8dc295559fc64f948b11eac9c3..9a9ba8890771410f12c5e45911d362f29ee6ea70 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -61,7 +61,6 @@
  */
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 /*
  * DDR related
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index 80a5797493da1960605cf4d6f6a4e5d66dbce812..e7f37f59fdebda69ad9ecb26dd653f25e9476019 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -112,7 +112,6 @@
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* FLASH */
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index c1295de36d2e8cb1026496ec8c96aaf87771a961..aa7446233c0ee4524eb41128970e9faa38ea169b 100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -79,7 +79,6 @@
 #define CONFIG_ENV_SIZE_FLEX SZ_256K
 #define	CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_1M)
 /* bytes reserved for initial data */
-#define	CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
diff --git a/include/configs/aria.h b/include/configs/aria.h
index a63c45334a807ae84f627cfc2b8c9f3ff88a5b7f..b3ca8d23f8c715ab74ee32093e6a5f27b0526f22 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -300,11 +300,10 @@
 
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index 49ea3a16685979c34e61cd8619ecc0b789331585..d0d0998d6efbc80038353b6502d2992ed1517056 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -51,7 +51,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
index 58cdbd59043cd2920e1bccb01b1312a82f38eff9..5cd1836434f43029840701d844ba288563be58c1 100644
--- a/include/configs/assabet.h
+++ b/include/configs/assabet.h
@@ -48,7 +48,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE       128	/* size rsrvd for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index f2bc26aab818adea5b541a3d322c380d8833a593..d468e498fa49b503294c9367bff0b1debf2a28e7 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -300,11 +300,10 @@
  * Definitions for initial stack pointer and data area (in internal SRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END		0x8000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -387,9 +386,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index 44c287033ff3acb66938699c6fc8f98d6d61e737..49c923f163dc66a769061b7ad2ed3432bb67fdc6 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -44,7 +44,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -209,7 +208,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index d39e8f28a960e02338758326c502f9ce9d410406..15de3103048f4ce086a86aa73741318152890bf9 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -69,14 +69,11 @@
 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
 
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index b386057c0efb16a3def2b8d0dad7cc36bbb8c8de..14559f5ccca093389ccae5d8982b3958afa4da72 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -205,10 +205,9 @@
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
 					     SZ_4K)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
-					- CONFIG_SYS_GBL_DATA_SIZE)
+					- GENERATED_GBL_DATA_SIZE)
 
 #define CONFIG_STACKSIZE		SZ_32K	/* regular stack */
 #define CONFIG_STACKSIZE_IRQ		SZ_4K	/* Unsure if to big or to small*/
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index b89242b3a17631ac6fa10d9565dc57dbbaaf65e4..5e7dee5299fed0438174957fe4a2473cdab8eaa1 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -49,7 +49,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -213,7 +212,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index df8181b755ba7bcd8337e2154810347257339f46..401478b270571d2e127af55a37b4a99dfbeab9e1 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -47,7 +47,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -231,7 +230,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 5cafa1ef4ac3df80f1c8192d2332667bc7be3e4a..f6cb40684fdbea5f4d10d19ffef119c793a12cd0 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -43,7 +43,6 @@
 
 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 
 /*
@@ -341,7 +340,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 44c5496b631cf675fd8214b91b499acc2eb2d92c..de74dcf18b5533f41a0be2cade699847513546e2 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -47,7 +47,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -217,7 +216,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index e8fcd66c940673bed9cd06e035520f93034da67e..8dbd0825b522080620a01ff14de0ced5d4e555f1 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -44,7 +44,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -176,7 +175,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/atc.h b/include/configs/atc.h
index 62e38e1cf14464a6270f35e71b77b241c1064991..53da0f7e2c6c4ca5049fd08b8c6fccc72bd51de4 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -244,9 +244,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
index ae60f2eb3c17f0a49f18e821f51ee446c4bb3e42..63e6d6e5834dbeb1b5dca713c21f9419da0bbc7b 100644
--- a/include/configs/balloon3.h
+++ b/include/configs/balloon3.h
@@ -33,7 +33,6 @@
  */
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define	CONFIG_SYS_GBL_DATA_SIZE	128
 #define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_BOOTCOMMAND						\
 	"fpga load 0x0 0x50000 0x62638; "				\
@@ -133,7 +132,7 @@
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define	CONFIG_SYS_INIT_SP_ADDR		\
-	(PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048)
+	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
 
 /*
  * NOR FLASH
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 1bdfd9da2f081edf722c49a545945638a79341f8..7b66fc092a73a316539ace3e3aa6720766074c0f 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -80,9 +80,8 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache       */
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/barco.h b/include/configs/barco.h
index b656c01597f532397433f1826a2e08251df4f7e9..dcba0cbcc788537659c1ad00ddb27d53e4485c97 100644
--- a/include/configs/barco.h
+++ b/include/configs/barco.h
@@ -151,20 +151,18 @@
 #define CONFIG_SYS_MONITOR_BASE	0x00090000
 #define CONFIG_SYS_RAMBOOT		1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END	0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_MONITOR_LEN		0x00030000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #endif
 
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index 09691d37377410b04f739cb039053471452e8b52..608ab9f41a4dfe8047b0cf9963b986a13301cdb5 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -11,7 +11,7 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+#define CONFIG_BFIN_BOOT_MODE	    BFIN_BOOT_BYPASS
 
 
 /*
@@ -21,11 +21,11 @@
  */
 /* CONFIG_CLKIN_HZ is any value in Hz					*/
 #define CONFIG_CLKIN_HZ			16384000
-/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
-/*                                                1 = CLKIN / 2		*/
+/* CLKIN_HALF controls the DF bit in PLL_CTL	  0 = CLKIN		*/
+/*						  1 = CLKIN / 2		*/
 #define CONFIG_CLKIN_HALF		0
 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
-/*                                                1 = bypass PLL	*/
+/*						  1 = bypass PLL	*/
 #define CONFIG_PLL_BYPASS		0
 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
 /* Values can range from 0-63 (where 0 means 64)			*/
@@ -36,7 +36,7 @@
 /* SCLK_DIV controls the system clock divider				*/
 /* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			3
-#define CONFIG_VR_CTL_VAL       (VLEV_110 | GAIN_20 | FREQ_1000)
+#define CONFIG_VR_CTL_VAL	(VLEV_110 | GAIN_20 | FREQ_1000)
 
 
 /*
@@ -111,13 +111,13 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-        arch/blackfin/cpu/traps.o            (.text .text.*); \
-        arch/blackfin/cpu/interrupt.o        (.text .text.*); \
-        arch/blackfin/cpu/serial.o           (.text .text.*); \
-        common/dlmalloc.o               (.text .text.*); \
-        lib/crc32.o             (.text .text.*); \
-        . = DEFINED(env_offset) ? env_offset : .; \
-        common/env_embedded.o           (.text .text.*);
+	arch/blackfin/cpu/traps.o	     (.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	     (.text .text.*); \
+	arch/blackfin/cpu/serial.o	     (.text .text.*); \
+	common/dlmalloc.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o		(.text .text.*);
 #endif
 
 
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 4412177ff09c42c36ec77eff5f486191256cc8ce..1c035cfcadad70948244e0ba5851a0048de5d51e 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -180,6 +180,7 @@
  * Misc Settings
  */
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 608788a66f9f72fc264e4d404c9bc2d819b1d9d5..03c64339d624026e00530500dc8543781ed646c5 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -295,6 +295,9 @@
 /*
  * Misc Settings
  */
+#ifndef CONFIG_BOARD_SIZE_LIMIT
+# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 ))
+#endif
 #define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
 #define CONFIG_LZMA
 
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
index 8b2bdc715d6a36eb909787c7aa59c45fae5959c7..e4688a27b4a81c791fec1bbc7e9e7e313bdd6736 100644
--- a/include/configs/blackvme.h
+++ b/include/configs/blackvme.h
@@ -126,9 +126,9 @@
  * AX88180  WEN = 5 clocks  REN 6 clocks @ SCLK = 100 MHz
  * One extra clock needed because AX88180 is asynchronous to CPU.
  */
-                           /* bank 1   0 */
+			   /* bank 1   0 */
 #define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
-                           /* bank 3   2 */
+			   /* bank 3   2 */
 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
 
 /* memory layout */
diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h
index 0bb97d9ea44a0ff9506ee03870e5ce35132beee3..3e691fdcf411f19ba7f274413f25d4d7cd59dc26 100644
--- a/include/configs/bluestone.h
+++ b/include/configs/bluestone.h
@@ -66,10 +66,9 @@
  * Initial RAM & stack pointer (placed in OCM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM    */
-#define CONFIG_SYS_INIT_RAM_END		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 7262b3e8a092441948cf409f801d6515d9c04cf5..da67ae3b5a2be7a9f89a64e34b2e77b9b2d4a299 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -238,10 +238,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
index 1351f297a969013350b88548becf6b74aa90441d..f325d2b439326bc05645889174a2b95d7447ff34 100644
--- a/include/configs/c2mon.h
+++ b/include/configs/c2mon.h
@@ -143,9 +143,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
index 5547d55eecd25c24d53b69ce6fc3f5d9e44e8aff..63f003db23f25215cff161d6c2db8311bc005fc8 100644
--- a/include/configs/ca9x4_ct_vxp.h
+++ b/include/configs/ca9x4_ct_vxp.h
@@ -45,7 +45,6 @@
 
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define SCTL_BASE			0x10001000
 #define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
@@ -116,10 +115,10 @@
 
 /* additions for new relocation code */
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_END		0x1000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Basic environment settings */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index e1ee158d4c79a9531138cb464430567c3cef16c0..d4c5bbd5c9f1059663c0072a12179b7e463fb0f6 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -157,11 +157,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index fcc7d0e3ed513f0512582b1fddabd36819cef75f..8c03582c8ddc149249eb3e67a6827b3ad62c5f82 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -124,9 +124,8 @@
  * Initial RAM & stack pointer (placed in OCM)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 98b69e37127bccd95a753d794430cd8aea8028c3..9696487907dd029b500de3b2c793448c3d64f20d 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -38,6 +38,7 @@
 #define CONFIG_CERF250		1	/* on Cerf PXA Board	    */
 #define BOARD_LATE_INIT		1
 #define CONFIG_BAUDRATE		38400
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
@@ -48,7 +49,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -140,15 +140,9 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	4			/* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
-#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
 
 #define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
 #define PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */
@@ -162,7 +156,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * GPIO settings
@@ -187,6 +181,9 @@
 
 #define CONFIG_SYS_PSSR_VAL		0x20
 
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+#define	CONFIG_SYS_CKEN			0x0
+
 /*
  * Memory settings
  */
@@ -196,6 +193,8 @@
 #define CONFIG_SYS_MDCNFG_VAL		0x00001AC9
 #define CONFIG_SYS_MDREFR_VAL		0x03CDC017
 #define CONFIG_SYS_MDMRS_VAL		0x00000000
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
index 7ea1a46033ba2fa2ec3eabdaf7ab0afabf5e49d1..6e4a3b45156dfabbfe6b91c8c1d439275e7c48b7 100644
--- a/include/configs/cm4008.h
+++ b/include/configs/cm4008.h
@@ -43,7 +43,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
index ea374da86e88cbd5315ea0f2c2bf753e52ad18d3..dca7d54c6b5525145789bc56fb5183898bd7512f 100644
--- a/include/configs/cm41xx.h
+++ b/include/configs/cm41xx.h
@@ -43,7 +43,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 1b129a2e667ec446838df0ad988462539a359d8f..0abe090c14a0f3b762bd92ed5164a7b34f5d0910 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -80,7 +80,9 @@
 #define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
 #define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
 /* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST		{ CONFIG_SYS_I2C_SLAVE, CONFIG_SYS_I2C_IO, CONFIG_SYS_I2C_EEPROM }
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_SLAVE,	\
+					 CONFIG_SYS_I2C_IO,	\
+					 CONFIG_SYS_I2C_EEPROM}
 
 /* display image timestamps */
 #define CONFIG_TIMESTAMP	1
@@ -160,13 +162,12 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_BOARD_TYPES	1	/* we use board_type */
 
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index ffe83f091c0596b4cc020cd36b07636dd6659419..a1976350e4fdb8297455fc9cf6ab627775b4251f 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -68,15 +68,12 @@
 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE		9600
 
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index 88a45c324995f0ff0c40efdbd22fdd4393f488ee..198f3423e8ddca0a9599ff0b4ac8259d39be52f8 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -129,9 +129,8 @@
  * Definitions for initial stack pointer and data area
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
-#define	CONFIG_SYS_INIT_RAM_END	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64			/* Size in bytes reserved for initial global data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CONFIG_SYS_INIT_RAM_SIZE	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 #define	CONFIG_SYS_INIT_SP_ADDR	0x013fa000		/* Physical start adress of inital stack */
 
 /*
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 18710fbe5aed435bb2f20aa321e20bfd4d3970b5..5348ad126b54359dfb69ec3c39bbecba1934a86a 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -276,9 +276,8 @@ from which user programs will be started */
  * Definitions for initial stack pointer and data area (in internal SRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -332,9 +331,9 @@ from which user programs will be started */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
index 8bfd7022c0399e8a75f3e5e39f52f39bf30457d7..d77af0defdff24fe8618d67251aa7cfbc1946f4d 100644
--- a/include/configs/cogent_mpc8260.h
+++ b/include/configs/cogent_mpc8260.h
@@ -224,9 +224,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
index 3cc95b4a4a2cc3fcb2f6f2c1e3c0340058aab001..3ee4a40a3eadb61a5b8791164bc0b381b58ade48 100644
--- a/include/configs/cogent_mpc8xx.h
+++ b/include/configs/cogent_mpc8xx.h
@@ -171,9 +171,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 5f457f80debc08db9ebe67595af63da38cbebb2c..23bfbeb1d7cef4f4266980b74ede0769be908873 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -29,7 +29,6 @@
 #define	CONFIG_VPAC270		1	/* Toradex Colibri PXA270 board */
 
 #undef	BOARD_LATE_INIT
-#undef	CONFIG_SKIP_RELOCATE_UBOOT
 #undef	CONFIG_USE_IRQ
 #undef	CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -38,8 +37,7 @@
  */
 #define	CONFIG_ENV_SIZE			0x4000
 #define	CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define	CONFIG_SYS_GBL_DATA_SIZE	128
-
+#define	CONFIG_SYS_TEXT_BASE		0x0
 #define	CONFIG_ENV_OVERWRITE		/* override default environment */
 
 #define	CONFIG_BOOTCOMMAND						\
@@ -170,7 +168,7 @@
 #define	CONFIG_SYS_LOAD_ADDR		(0xa1000000)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * NOR FLASH
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 85147d00219a964bee3baee0eda5a5d60428a396..2ac59e54b61ad516f1dbb427e678c519cf886e4f 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -211,10 +211,9 @@
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
-#define CONFIG_SYS_INIT_RAM_END		0x00004000	/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index a865296fdf997df4874896a4d77dc5cc823ff589..c1742c1a693c8a0e649e8ec679452c801eaeb6de 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -235,10 +235,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index fb6f79a42300260b24320211f075e4d67ab3841d..d2394235f193f109340c76a63f5ad5b8780f9ee2 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -445,7 +445,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		\
 		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_STACKSIZE		(32 * 1024)
 
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 9ef4523de427dbc124d1c09c5f8d9e957d7a0da4..f31081dbf37b25d76674e8eaad3fe0e1114225e3 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -28,7 +28,6 @@
 
 #ifdef CONFIG_CPUAT91_RAM
 #define CONFIG_SKIP_LOWLEVEL_INIT	1
-#define CONFIG_SKIP_RELOCATE_UBOOT	1
 #else
 #define CONFIG_BOOTDELAY		1
 #endif
@@ -200,7 +199,6 @@
 #define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
 
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_STACKSIZE		(32 * 1024)
 
 #if defined(CONFIG_USE_IRQ)
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index d1c1a48e0c9f625fe38ace8664816ab97d22d75e..c21af3817f431ea16b810348f31ba17c7fc079e2 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -39,12 +39,11 @@
 
 /* we will never enable dcache, because we have to setup MMU first */
 #define CONFIG_SYS_NO_DCACHE
-
+#define	CONFIG_SYS_TEXT_BASE		0x0
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -126,15 +125,9 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
-#define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 
 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
@@ -146,7 +139,7 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * FLASH and environment organization
@@ -289,9 +282,9 @@
  * Clocks, power control and interrupts
  */
 #define CONFIG_SYS_PSSR_VAL        0x00000020
-#define CONFIG_SYS_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
-#define CONFIG_SYS_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
-#define CONFIG_SYS_ICMR_VAL        0x00000000  /* No interrupts enabled        */
+#define CONFIG_SYS_CCCR        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
+#define CONFIG_SYS_CKEN        0x00000060  /* FFUART and STUART enabled    */
+#define CONFIG_SYS_ICMR        0x00000000  /* No interrupts enabled        */
 
 /* FIXME
  *
@@ -319,6 +312,8 @@
 #define CONFIG_SYS_MDMRS_VAL       0x00000000
 #define CONFIG_SYS_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
 #endif
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index ae05734a09eb04b14e1852575900b3818f18c89e..505740c4d41e2302099170613366025a93f056ae 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -45,7 +45,7 @@
 
 /* we will never enable dcache, because we have to setup MMU first */
 #define CONFIG_SYS_NO_DCACHE
-
+#define	CONFIG_SYS_TEXT_BASE	0x0
 /*
  * Hardware drivers
  */
@@ -117,7 +117,6 @@
  *
  */
 #define CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
 
 #define CONFIG_SYS_LONGHELP				/* undef to save memory         */
 #define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
@@ -182,7 +181,7 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 # if 0
 /* FIXME: switch to _documented_ registers */
@@ -458,6 +457,9 @@
 
 #define CONFIG_SYS_PSSR_VAL        0x20
 
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+#define	CONFIG_SYS_CKEN			0x0
+
 /*
  * Memory settings
  */
@@ -468,6 +470,8 @@
 #define CONFIG_SYS_MDCNFG_VAL          0x09a909a9
 #define CONFIG_SYS_MDREFR_VAL          0x038ff030
 #define CONFIG_SYS_MDMRS_VAL           0x00220022
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index acd9c93efd992b358f65066ba964ee8698bac95c..0ea34b89d85185971f2c52c2c13ced19a415160a 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -293,9 +293,8 @@
  *
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 69abb167625cbdf79e37d4fe395b196ae0e2195c..23731676f25da36f4565299e4730ed83f592cc47 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -292,9 +292,8 @@
  *
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index efa27809920415fb7a187f58b112e43dc31fd12a..7a85d65302060ba1211b6da43938964d407d4c8d 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -69,14 +69,11 @@
 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
 
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 160ece2bf9cf8d20097d38178ea6e4aea98e80e6..1feada926321272f1206cf40dba86496ff147b79 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -41,13 +41,12 @@
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
 
 /*
  * Memory Info
  */
 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* reserved for initial data */
 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1 /* memtest start addr */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 7bf6336b1312544958874f6dd37395fd5992b853..7b04be05b9be408af3991fb99a47db2b738b7c5f 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -40,12 +40,12 @@
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
 
 /*
  * Memory Info
  */
 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* reserved for initial data */
 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
@@ -192,5 +192,5 @@
 /* additions for new relocation code, must added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
-					CONFIG_SYS_GBL_DATA_SIZE)
+					GENERATED_GBL_DATA_SIZE)
 #endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index 37011c0935c4b0ba6c2b605e34ef8df018ad13ef..8a6905241c74d1979ecde5448f0227998d774bfb 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -24,7 +24,6 @@
 #define DAVINCI_DM355EVM
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_DISPLAY_CPUINFO
@@ -151,7 +150,6 @@
 /* U-Boot memory configuration */
 #define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* for initial data */
 #define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
 #define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
 
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index e09fb751894d1e6419ea43246c6a65852020e949..c9530327c65f9b7d22818f8ab1edbddbb0f7411f 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -23,7 +23,6 @@
 #define DAVINCI_DM355LEOPARD
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_DISPLAY_CPUINFO
@@ -134,7 +133,6 @@
 /* U-Boot memory configuration */
 #define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* for initial data */
 #define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
 #define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
 
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index 2c3d88dc174740a35c88d79bb399cf0cf9a98eb3..b78fe83867182a8e68fbe21fee10965b54467e7a 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -24,7 +24,6 @@
 #define DAVINCI_DM365EVM
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 
@@ -183,7 +182,6 @@
 /* U-Boot memory configuration */
 #define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* for initial data */
 #define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
 #define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
 
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index ddc5990cef5f09d53ab1b9983611e24936b83986..f0a8e98c36a8fec7482b456fb5d55c8d8f0b8deb 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -24,7 +24,6 @@
 #define DAVINCI_DM6467EVM
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /* SoC Configuration */
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
@@ -41,7 +40,6 @@
 
 /* Memory Info */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* initial data */
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS		1
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index aab2afa962b22ad81084366f0e754668cbbbb445..186726d3a6759944e790d1ced74a95a52c416ae9 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -72,7 +72,6 @@
 /* Memory Info */
 /*=============*/
 #define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
 #define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
 #define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
@@ -134,7 +133,6 @@
 #define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
 #endif
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #define CONFIG_SYS_NAND_BASE		0x02000000
 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_HW_ECC
@@ -144,10 +142,8 @@
 #elif defined(CONFIG_SYS_USE_NOR)
 #ifdef CONFIG_NOR_UART_BOOT
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #else
 #undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 #define CONFIG_ENV_IS_IN_FLASH
 #undef CONFIG_SYS_NO_FLASH
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 04cdc210e62b3a81522159c29cfedbcf786314dd..967ebcc98a502de4a9f24d2f42f99dc638bfb2cb 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -39,7 +39,6 @@
 /* Memory Info */
 /*=============*/
 #define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
 #define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
 #define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
@@ -89,7 +88,6 @@
 #define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
 #define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #define CONFIG_SYS_NAND_BASE		0x02000000
 #define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index f4e17f8cc227e8a9ef5e70517d5fb9cc2bce9a17..4d866d0eb207fb76466462182324376e39ac3e30 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -42,7 +42,6 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
 /* Memory Info */
 #define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
 #define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
 #define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
@@ -84,7 +83,6 @@
 #define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
 #define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #define CONFIG_SYS_NAND_BASE		0x02000000
 #define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 1746495e9a791478732369e8eb845f8f2d65ea24..0dc89ef41e2c2b329105c255a323ced809380843 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -72,7 +72,6 @@
 /* Memory Info */
 /*=============*/
 #define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
 #define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
 #define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
@@ -123,7 +122,6 @@
 #define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
 #define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #define CONFIG_SYS_NAND_BASE		0x02000000
 #define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
@@ -132,10 +130,8 @@
 #elif defined(CONFIG_SYS_USE_NOR)
 #ifdef CONFIG_NOR_UART_BOOT
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #else
 #undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 #define CONFIG_ENV_IS_IN_FLASH
 #undef CONFIG_SYS_NO_FLASH
diff --git a/include/configs/debris.h b/include/configs/debris.h
index 188061e9c19416b1895476887729554a5f7a0a6e..7ad36a1ce882e851d80c7f62f1a309d08a6c119f 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -199,21 +199,18 @@
 #define CONFIG_SYS_MONITOR_BASE	0x00090000
 #define CONFIG_SYS_RAMBOOT		1
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_END	0x10000
-#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_MONITOR_LEN		0x00040000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 
-/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #endif
 
diff --git a/include/configs/delta.h b/include/configs/delta.h
deleted file mode 100644
index d53acbfebcf15bd321c87098a352786a750d188e..0000000000000000000000000000000000000000
--- a/include/configs/delta.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * Configuation settings for the Delta board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_MONAHANS	1	/* Intel Monahan CPU    */
-#define	CONFIG_CPU_PXA320
-#define CONFIG_DELTA		1	/* Delta board       */
-
-/* #define CONFIG_LCD		1 */
-#ifdef CONFIG_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-#define BOARD_LATE_INIT		1
-
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#undef TURN_ON_ETHERNET
-#ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
-# define CONFIG_SMC91111_BASE   0x14000300
-# define CONFIG_SMC91111_EXT_PHY
-# define CONFIG_SMC_USE_32_BIT
-# undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
-#endif
-
-#define CONFIG_HARD_I2C		1	/* required for DA9030 access */
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE		1	/* I2C controllers address */
-#define DA9030_I2C_ADDR		0x49	/* I2C address of DA9030 */
-#define CONFIG_SYS_DA9030_EXTON_DELAY	100000	/* wait x us after DA9030 reset via EXTON */
-#define CONFIG_SYS_I2C_INIT_BOARD	1
-/* #define CONFIG_HW_WATCHDOG	1	/\* Required for hitting the DA9030 WD *\/ */
-
-#define DELTA_CHECK_KEYBD	1	/* check for keys pressed during boot */
-#define CONFIG_PREBOOT		"\0"
-
-#ifdef DELTA_CHECK_KEYBD
-# define KEYBD_DATALEN		4	/* we have four keys */
-# define KEYBD_KP_DKIN0		0x1	/* vol+ */
-# define KEYBD_KP_DKIN1		0x2	/* vol- */
-# define KEYBD_KP_DKIN2		0x3	/* multi */
-# define KEYBD_KP_DKIN5		0x4	/* SWKEY_GN */
-#endif /* DELTA_CHECK_KEYBD */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART		1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#ifdef TURN_ON_ETHERNET
-
-#define CONFIG_CMD_PING
-
-#else
-
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-
-#endif
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW	1
-#define CONFIG_USB_STORAGE      1
-#define CONFIG_DOS_PARTITION    1
-
-#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	OHCI_REGS_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"delta"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
-
-#define CONFIG_BOOTDELAY	-1
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_IPADDR		192.168.0.21
-#define CONFIG_SERVERIP		192.168.0.250
-#define CONFIG_BOOTCOMMAND	"bootm 80000"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_TIMESTAMP
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER		1
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
-#endif
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_DEVICE_NULLDEV	1
-
-#define CONFIG_SYS_MEMTEST_START	0x80400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x80800000	/* 4 ... 8 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-
-#define CONFIG_SYS_HZ			1000
-
-/* Monahans Core Frequency */
-#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO		16 /* valid values: 8, 16, 24, 31 */
-#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO	1  /* valid values: 1, 2 */
-
-
-						/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE		0xF0000000
-#endif
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1		0x80000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x1000000  /* 64 MB */
-#define PHYS_SDRAM_2		0x81000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x1000000  /* 64 MB */
-#define PHYS_SDRAM_3		0x82000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x1000000  /* 64 MB */
-#define PHYS_SDRAM_4		0x83000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x1000000  /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE		0x80000000 /* at CS0 */
-#define CONFIG_SYS_DRAM_SIZE		0x04000000 /* 64 MB Ram */
-
-#undef CONFIG_SYS_SKIP_DRAM_SCRUB
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * NAND Flash
- */
-#define CONFIG_SYS_NAND0_BASE		0x0 /* 0x43100040 */ /* 0x10000000 */
-#undef CONFIG_SYS_NAND1_BASE
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-
-/* nand timeout values */
-#define CONFIG_SYS_NAND_PROG_ERASE_TO	3000
-#define CONFIG_SYS_NAND_OTHER_TO	100
-#define CONFIG_SYS_NAND_SENDCMD_RETRY	3
-#undef NAND_ALLOW_ERASE_ALL	/* Allow erasing bad blocks - don't use */
-
-/* NAND Timing Parameters (in ns) */
-#define NAND_TIMING_tCH		10
-#define NAND_TIMING_tCS		0
-#define NAND_TIMING_tWH		20
-#define NAND_TIMING_tWP		40
-
-#define NAND_TIMING_tRH		20
-#define NAND_TIMING_tRP		40
-
-#define NAND_TIMING_tR		11123
-#define NAND_TIMING_tWHR	100
-#define NAND_TIMING_tAR		10
-
-/* NAND debugging */
-#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
-#undef CONFIG_SYS_DFC_DEBUG2  /* noisy */
-#undef CONFIG_SYS_DFC_DEBUG3  /* extremly noisy  */
-
-#define CONFIG_MTD_DEBUG
-#define CONFIG_MTD_DEBUG_VERBOSE 1
-
-#define CONFIG_SYS_NO_FLASH		1
-
-#define CONFIG_ENV_IS_IN_NAND	1
-#define CONFIG_ENV_OFFSET		0x40000
-#define CONFIG_ENV_OFFSET_REDUND	0x44000
-#define CONFIG_ENV_SIZE		0x4000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index c47e17c7798d6733860fa158fc24f765f4a55793..fa7a6c7d8e12060406dcaf8536622ff959ac8966 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -65,7 +65,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
 /* Hardware drivers */
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 2e9a13f7e4a609941a847544a87a7b55206a20d0..d541160bd39b153f2f48c95bdddada6b061cf98c 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -308,11 +308,10 @@
  *  Use SRAM until RAM will be available
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	4096
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index 0d44eda867043549ba2831b13b5241f39e7580c8..c490ff67da411e20dd7ce6d8cacacd9350029507 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -191,11 +191,10 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index e48e20f6853f3d549fe85240dd4b092e9f81bb1f..69c6420fe9d916b6c95f47730f9ea23c2bc265be 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -32,7 +32,6 @@
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
 #define CONFIG_SKIP_LOWLEVEL_INIT	1
-#undef  CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * High Level Configuration Options
@@ -49,7 +48,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
index 637cc55e0687980eb8625e7c1668f529315182c4..61f34ddc446221a34c8134aea8720515036a31be 100644
--- a/include/configs/eXalion.h
+++ b/include/configs/eXalion.h
@@ -119,11 +119,10 @@
 #define CONFIG_SYS_INIT_DATA_SIZE	128
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 
-#define CONFIG_SYS_GBL_DATA_SIZE	 256	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 8d8af93792fb7ccbea8f86ebcd8a8a6f03f16af6..754fc8bf8b61dd74af507eee9332541599917828 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -91,7 +91,6 @@
  */
 
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 520*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * sdram
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index a0d38696607034162e5434020dbf0ac3180779a7..d6b655122a584854913acb79e1683d521c54e06e 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -73,10 +73,9 @@
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE  128		    /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index ff25ee2754642f0b1a2f01880b4224bf83c79983..19b76321e656b3500d031bcd1f87e762df5f0773 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -218,7 +218,6 @@
 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
 
 /* Run-time memory allocatons */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_STACKSIZE		(128 * 1024)
 
 #if defined(CONFIG_USE_IRQ)
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 43e5e870f009df4f48807d93a305569e5028fe3f..a75f06aa5950d7c940a933b92d4c3511476332cd 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -205,7 +205,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN	(1024 * 128) /* 128kB for malloc() */
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Other required minimal configurations
@@ -226,6 +225,6 @@
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_SYS_INIT_SP_ADDR	\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
 
 #endif /* _CONFIG_EDMINIV2_H */
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
index e151faa9655ab916cffd88d2cf320ce77e6e591c..fdb98b5cbcc83c3fdf1b915300145f206dd5a6c7 100644
--- a/include/configs/ep7312.h
+++ b/include/configs/ep7312.h
@@ -42,7 +42,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index 5f083bda177a0269dc79adf1ee2ce93a07d6e475..bb87d3623cd398bd6d6dbd41defe741998d683a8 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -218,9 +218,8 @@
 #define CONFIG_SYS_IMMR		0xF0000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index cbf55dba89eacd619430b49fe46b721de127e9b8..b15659d918d62ebc4554ed401f4dad7b7443e7b2 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -429,9 +429,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 48985a06ca2f3aedf71178a6ae6da7e09cd154b2..692f0ec77a69b71cbcf6b4d5251e0f16275f23a9 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -346,9 +346,8 @@
 #define CONFIG_SYS_IMMR		0xF0000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 2ec907c1f1321fac73f4b1af6ba8dbe829afca5c..26389ed02535c074596c9c27b999f677785bce1c 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -85,7 +85,6 @@
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 #define CONFIG_SYS_FLASH_CFI
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
index 0f415d9c8b9ade0268c900b305bba65c478cddcc..fb05727cde15fa7e3f2c5f865959edeb0008bce9 100644
--- a/include/configs/evb4510.h
+++ b/include/configs/evb4510.h
@@ -53,7 +53,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index d95144d589c37842c726f7d6e555258e58653735..9535eb9edec9a038cb400755ff7b1680595b64ec 100644
--- a/include/configs/galaxy5200.h
+++ b/include/configs/galaxy5200.h
@@ -207,13 +207,12 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 
 /* End of used area in SPRAM */
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
 
 /* Size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-						CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index 41294b9be62a64505dbfa50c0770820c24af105d..fd39ab4a033849665668055b5ea2b14518fb939e 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -39,7 +39,6 @@
  * we use lowlevel_init (!CONFIG_SKIP_LOWLEVEL_INIT) to remedy that problem.
  */
 #undef  CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT	1
 
 /*
  * High Level Configuration Options
@@ -60,7 +59,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size rsrvd for initial data */
 
 
 /*
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 282afbcc6100e24cacfb0362166ff9a5081e6bcb..3c59ff4922c86948373869f045146ce259f5a607 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -72,10 +72,9 @@
  */
 #define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache             */
-#define CONFIG_SYS_INIT_RAM_END		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes init data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
-					 - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+					 - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index bb4ea7921d08b17871c729af9494391386bb9885..dc62ea30c26c40e0c1a3f68903fa3bbbaf52d4ea 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -261,10 +261,9 @@
 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 #endif
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 35c4a083530927abec72a73afeac245deed7ec68..5efe676bce2441bd3af8ac7052ff4cb5f4720a5b 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -229,10 +229,9 @@
 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 92fbbbb5582c090839844f1c93a4caa7079242fa..505db10a0f7ba7eb2b2599a59a4e401c1c779922 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -206,10 +206,9 @@
 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 5dfdf5156ff91246d569465d5335079eb858d1e1..bbd2f91abd312f24bfc110b51342cf29dd0e3c38 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -231,10 +231,9 @@
 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 39af8feb43fad49ba0fa65b8b87f7399ffb79807..294d6c4f870dcaf0907b976176b9e58aace48dab 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -229,10 +229,9 @@
 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_PROM_SIZE		(8192-CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
 
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 2c2682cfadf0c1bbdaafe49dc6ca5e3e2c571a0f..f449da9354491990b8047f75b1eb34363d542466 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -72,8 +72,8 @@
  * it has to be rounded to sector size
  */
 #define CONFIG_ENV_SIZE			0x20000	/* 128k */
-#define CONFIG_ENV_ADDR			0x40000
-#define CONFIG_ENV_OFFSET		0x40000	/* env starts here */
+#define CONFIG_ENV_ADDR			0x60000
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
 
 /*
  * Default environment variables
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 6c1ddac85d59339c814274c2a0e1029c7bc92c26..35e6944d5487381c9011a94beb32096908fee89c 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -438,9 +438,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR    CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END     0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE   128 /* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE     0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET   CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index dd5e5a20c642487b59ebaa090065dd7eff5fa10f..c56efde7e0befe3d7afb5a06d16f2e86c7662382 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -71,9 +71,8 @@
 #define CONFIG_SYS_TEMP_STACK_OCM 1
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* OCM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index a2edf51e202e2fcfb3ec1c5d75dd1357c851e5d3..0c8fdf504cccc71b0606ef768af899aedf504697 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -82,9 +82,8 @@
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
index 58fc4ce76f927cb8d445d3363944cd8aa9df0589..d849b5cc81a503e269d740421f90375f447f5c49 100644
--- a/include/configs/hermes.h
+++ b/include/configs/hermes.h
@@ -122,9 +122,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index 60e5c2b4bb527313578bad10cc39b0fd8d545e1d..354072a8e67957bcd22f0d60480a976e585a4ca2 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -196,13 +196,12 @@
 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 
 #ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index ccfc3dfdfb1d43e2153d15d0a18bca5303996f6f..7c4c2ba4ea9b63a1269b519f14622eb2335ea72a 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -377,9 +377,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/icon.h b/include/configs/icon.h
index 8d98d57f88ec6bfbaaaa06bd17e16368a5b902a3..2fac0efe13051902c9946497bc4678371b963e5a 100644
--- a/include/configs/icon.h
+++ b/include/configs/icon.h
@@ -97,11 +97,10 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Init RAM */
-#define CONFIG_SYS_INIT_RAM_END		0x2000		/* end used area */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* sizeof init data */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* size of used area */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 8105876e4ead49843dbf095548c1d60f48958bc8..fc046d60556869960a48d43a5c96f0580cc5e7fc 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -180,9 +180,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -225,9 +224,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 8)
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_END - 4)
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
 #define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
index 34e8a57b9636b29c15c14302bc80e0d9078eaa11..16d92793afbc88504f806371fd3f068ab45ce92c 100644
--- a/include/configs/igep0020.h
+++ b/include/configs/igep0020.h
@@ -210,7 +210,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* bytes for initial data */
 
 /*
  * SMSC911x Ethernet
@@ -223,6 +222,6 @@
 #endif /* (CONFIG_CMD_NET) */
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h
index 5e2e0ed7bf6317f92bfb7bd98883e9c13edcbee3..d6fbec7b1f18abbdee05570985e59357b39131c9 100644
--- a/include/configs/igep0030.h
+++ b/include/configs/igep0030.h
@@ -207,9 +207,8 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* bytes for initial data */
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
index fdfa022c0b0d3e3c7f18d415ee32b5d26d4b904c..3328e639a9c5d1ed420cba786026f3f65ac8e5d5 100644
--- a/include/configs/impa7.h
+++ b/include/configs/impa7.h
@@ -42,7 +42,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 88e8d3db104b1e8400742f05bae64ccad8501017..b8dc5aac5daadafb36c4fb99f2b5caebef0309d6 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -89,7 +89,6 @@
 /* malloc() len */
 #define CONFIG_SYS_MALLOC_LEN		(0x10000 + 512 * 1024)
 /* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 /* memtest start address */
 #define CONFIG_SYS_MEMTEST_START	0xA0000000
 #define CONFIG_SYS_MEMTEST_END		0xA1000000	/* 16MB RAM test */
@@ -238,5 +237,5 @@
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
-					CONFIG_SYS_GBL_DATA_SIZE)
+					GENERATED_GBL_DATA_SIZE)
 #endif /* __IMX27LITE_COMMON_CONFIG_H */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 94252371bc339a2c3d60c4ea8c21132286ca033e..50236380704236b079baef9f4fdd1689b22a1c11 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -54,7 +54,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -147,11 +146,10 @@
 #define PHYS_SDRAM_1		CSD0_BASE
 #define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
 
-#undef CONFIG_SYS_ARM_WITHOUT_RELOC
 #define CONFIG_SYS_SDRAM_BASE		CSD0_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_END		IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 62944a93f6ee7301ea206aac50bdb3f6913cd9e4..4d11f97d6f5251faf91871271aa4d20aa33fb34b 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -52,7 +52,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 3636d12509d46b1fe297bfcee0d40dad1bd402fa..9b116e690ecc4b00f5383ac4f10cbf94fd2187ac 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -211,13 +211,12 @@
 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 
 #ifdef CONFIG_POST
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 007ccebf436e2de76a7397498883b412e28a78b8..d8fcbdb42199f3a5ec520b12935a22b6cde7609e 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -40,6 +40,8 @@
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
 					/* for timer/console/ethernet       */
 
+#define	CONFIG_SYS_TEXT_BASE	0x0
+
 /* we will never enable dcache, because we have to setup MMU first */
 #define CONFIG_SYS_NO_DCACHE
 
@@ -108,7 +110,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
 
 #define CONFIG_SYS_LONGHELP				/* undef to save memory         */
 #define CONFIG_SYS_PROMPT		"uboot> "	/* Monitor Command Prompt       */
@@ -193,7 +194,7 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * JFFS2 partitions
@@ -347,6 +348,9 @@
  */
 #define CONFIG_SYS_PSSR_VAL		0x37
 
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+#define	CONFIG_SYS_CKEN			0x0
+
 /*
  * Memory settings
  *
@@ -480,6 +484,9 @@
 #define CONFIG_SYS_MCIO0_VAL		0x00000000
 #define CONFIG_SYS_MCIO1_VAL		0x00000000
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
 #define CSB226_USER_LED0	0x00000008
 #define CSB226_USER_LED1	0x00000010
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index e0e82583410516c1c0f4fca9a6da2aaf8821d3bb..32ff1932c6eea84658dcaebd12258f85b5f4a70e 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -53,7 +53,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * PL010 Configuration
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index caafc93116ce2f277851162c3d9a060643118125..2c8ca2ddc59bd04502bbd44e8e2510cde703bb75 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -48,7 +48,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 56d2be2afe71662237ee9adfe57079a71272e954..3ff4a86ab963deb2a83e8bc2a1c677c07129f3b1 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -106,10 +106,9 @@
  * Initial RAM & stack pointer (placed in OCM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/io.h b/include/configs/io.h
new file mode 100644
index 0000000000000000000000000000000000000000..a66c7043611ed987c09f736f86332830e5cf7a78
--- /dev/null
+++ b/include/configs/io.h
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_4xx		1	/*  member of PPC4xx family */
+#define CONFIG_IO	        1	/*  on a Io board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		io
+#define CONFIG_IDENT_STRING	" io 0.04"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT		/* call last_stage_init */
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	/* our MDIO is GPIO0 */
+#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	/* our MDC  is GPIO7 */
+
+#define CONFIG_SYS_GBIT_MII_BUSNAME	"io_miiphy"
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0xa382a880
+/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1CR		0x7f318000
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CONFIG_SYS_FPGA_BASE		0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x02025080
+/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB2CR		0x7f11a000
+
+#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
+#define CONFIG_SYS_FPGA_RFL_HIGH	0x3ffe
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
+#define CONFIG_SYS_EBC_PB3AP		0xa2015480
+/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
+
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffbf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
new file mode 100644
index 0000000000000000000000000000000000000000..5e61b11372a6bc98da033717549f6ea5cc32424e
--- /dev/null
+++ b/include/configs/iocon.h
@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_4xx		1	/*  member of PPC4xx family */
+#define CONFIG_IOCON		1	/*  on a IoCon board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		iocon
+#define CONFIG_IDENT_STRING	" iocon 0.03"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX		1	/* Use UART0 */
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED		400000
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#ifndef __ASSEMBLY__
+void fpga_gpio_set(int pin);
+void fpga_gpio_clear(int pin);
+int fpga_gpio_get(int pin);
+#endif
+
+#define I2C_ACTIVE	{ }
+#define I2C_TRISTATE	{ }
+#define I2C_READ	fpga_gpio_get(0x0040) ? 1 : 0
+#define I2C_SDA(bit)	if (bit) fpga_gpio_set(0x0040); \
+			else fpga_gpio_clear(0x0040)
+#define I2C_SCL(bit)	if (bit) fpga_gpio_set(0x0020); \
+			else fpga_gpio_clear(0x0020)
+#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0xa382a880
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFB858000
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CONFIG_SYS_FPGA_BASE		0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x02825080
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
+#define CONFIG_SYS_FPGA_RFL_HIGH	0x00fe
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
+#define CONFIG_SYS_EBC_PB3AP		0x02025080
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
+
+#define CONFIG_SYS_LATCH0_RESET		0xffef
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffff
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index c37b83b09593d84e96fab950d47e8e2e5ab7accd..d3821389fd5025f64cc12a42436216f7d5aabc31 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -264,13 +264,12 @@
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 /* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
 
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
index 768e8366bda2d6a584f82f747278ad3077d0a3bb..28d41e29254a27acc3d6bb5f74d5a51502d17bca 100644
--- a/include/configs/ixdp425.h
+++ b/include/configs/ixdp425.h
@@ -46,7 +46,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN      (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index 0c092347ca794abd9cb6c1a253b4d99190e71b86..637fd7d4f89b80bb1c2a08decaa00965f6937e5f 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -68,7 +68,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(256 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
index a5d8764b519cae58160bf784f80e07b5fd2c9f56..c1193926bde8f22e6bc43d989848faaeeb90ed6f 100644
--- a/include/configs/jadecpu.h
+++ b/include/configs/jadecpu.h
@@ -197,7 +197,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(0x400000 - 0x8000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
diff --git a/include/configs/jornada.h b/include/configs/jornada.h
index 69a045cc324fae2693143accae1f7eb16e803820..41b09aad9f1cf0689c5d8410fc9bb5fc3da78545 100644
--- a/include/configs/jornada.h
+++ b/include/configs/jornada.h
@@ -28,7 +28,6 @@
 #define CONFIG_SA1110			1	/* This is an SA110 CPU */
 #define CONFIG_JORNADA700		1	/* on an HP Jornada 700 series */
 #define CONFIG_SYS_FLASH_PROTECTION	1
-#define CONFIG_SYS_ARM_WITHOUT_RELOC	1
 
 #define CONFIG_SYS_TEXT_BASE		0xC1F00000
 
@@ -46,7 +45,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size for initial data */
 
 /*
  * select serial console configuration
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 6f5ac942f4e1594e0a386d1608ad378ca27375fa..8d27c0b2d10dcbc7ca72a5c896772a1691c4288e 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -225,11 +225,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 135a4c26aa4cc80a2aa07e2885204026a662d5ab..3ed8dc7f3ea2a8ce251006ef500b10db9497ef27 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -96,10 +96,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 41ec1d52e39b0309000952756e3ec2d5ab9d29e8..cfb7ceacc1dac6232c91b6fe189f412da70b4f2f 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -53,8 +53,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define	CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT	/* undef this for direct boot from */
-									/* NOR flash without preloader */
 
 #define	CONFIG_SYS_LONGHELP
 
@@ -65,7 +63,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(roundup(CONFIG_ENV_SIZE,4096) + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE 115200
 
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index 62d21f628666d522da8d103cda644f277cfbd6ed..ccc71c96c0a076a9795df5e3c5c5aba12b9ac1bc 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -29,6 +29,22 @@
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg 
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* 
+ * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_TEXT_BASE	0x00400000
+#endif /* CONFIG_SYS_TEXT_BASE */
+
 /*
  * Command line configuration.
  */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index e153b3120fbc0c3bc21a458b0117871a5fac64ae..031f8fb4ec991a37eae9f3476d873fadfc0fe474 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -92,9 +92,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
-#define CONFIG_SYS_INIT_RAM_END        (4 << 10)			/*  4 KiB */
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)			/*  4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * If the data cache is being used for the primordial stack and global
diff --git a/include/configs/km8xx.h b/include/configs/km8xx.h
index 2a42e99743165443af4198581992e48b2c462bef..7683fe542e562eab865ab179a270bf0d1b29d89f 100644
--- a/include/configs/km8xx.h
+++ b/include/configs/km8xx.h
@@ -107,9 +107,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index faa0f503266e6a5227bd86b4662d7a4f0d38b248..bf77cc0542600ee59172e2d57311e65a59c47d99 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -108,7 +108,6 @@
 #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
 
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Other required minimal configurations
@@ -182,6 +181,8 @@ int get_scl (void);
 
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_INIT_SP_ADDR		(0x00000000 + 0x1000 - /* Fix this */ \
-					CONFIG_SYS_GBL_DATA_SIZE)
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+/* Do early setups now in board_init_f() */
+#define CONFIG_BOARD_EARLY_INIT_F
 #endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 03d3aacb8f5ecc8599a7bbbbc22f6894d7a4695a..8fcadfee50603c68217d580578416591beed6814 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -179,9 +179,8 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 3a0531bc8f14c0a51b878626b23569fb2a290412..66cb53337d6d8b01401ccc53b5cc2f1ed50a7f63 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -88,9 +88,8 @@
 /* 440EPx has 16KB of internal SRAM, so no need for D-Cache		*/
 #undef CONFIG_SYS_INIT_RAM_DCACHE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
index fa876255bf1c5d21d17780e165d3d7b8f64c502d..95fc2437dd5b7bec976d1f1ee1113b05c21e1eb0 100644
--- a/include/configs/kvme080.h
+++ b/include/configs/kvme080.h
@@ -117,9 +117,8 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_FLASH_BASE		0x7C000000
diff --git a/include/configs/lart.h b/include/configs/lart.h
index 2d3b369aae68078c8c7fa53a03e53ee88a4b5a7d..795cf3487b3a5bbd0323eea8cbf5d55de64d63d3 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -42,7 +42,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index aaf663a749b6316ec7e1ef8f2dd59c24d77c8a67..b00647b3e01eef168660e215b4e77d703d3aa6e8 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -275,9 +275,8 @@
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
 #endif
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*----------------------------------------------------------------------
  * Serial configuration
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
index 65276a27c0b7f63d5a620bf3431d160212678074..17972d7e6ffa27b22461725476afa537b065dcec 100644
--- a/include/configs/lpc2292sodimm.h
+++ b/include/configs/lpc2292sodimm.h
@@ -31,7 +31,6 @@
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
 #undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * High Level Configuration Options
@@ -48,7 +47,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h
index bf4a57d249bd06ce4d2a65860de04445977d3bd4..06f3d7e58ff3b7f355aa127f7cced22314966f9f 100644
--- a/include/configs/lpd7a400.h
+++ b/include/configs/lpd7a400.h
@@ -38,7 +38,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * select serial console configuration
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
index 557f389ccbf2690e4c3265facd9211159d8631dc..7535f62d3df7026cfe1acf8210dbceb53cefb00f 100644
--- a/include/configs/lpd7a404.h
+++ b/include/configs/lpd7a404.h
@@ -38,7 +38,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * select serial console configuration
diff --git a/include/configs/luan.h b/include/configs/luan.h
index d8014047b7b6d0fe0986063518cb3c4658ddf209..3b4761bd08719919657851195e4067026446446a 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -80,9 +80,8 @@
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_END	(8 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(8 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index 3a99ec25c4be25221ce022a6091f07a0e37acc50..b7d53b65b787e62c10ca151165de0f993400f3c0 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -43,7 +43,7 @@
 #define CONFIG_MMC
 #define BOARD_LATE_INIT		1
 #define CONFIG_DOS_PARTITION
-
+#define	CONFIG_SYS_TEXT_BASE	0x0
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
 /* we will never enable dcache, because we have to setup MMU first */
@@ -53,7 +53,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -177,7 +176,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
 
@@ -202,6 +201,9 @@
 
 #define CONFIG_SYS_PSSR_VAL		0x20
 
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+#define	CONFIG_SYS_CKEN			0x0
+
 /*
  * Memory settings
  */
@@ -212,6 +214,9 @@
 #define CONFIG_SYS_MDREFR_VAL		0x00018018
 #define CONFIG_SYS_MDMRS_VAL		0x00000000
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
  * PCMCIA and CF Interfaces
  */
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index 1062765f03662813afc02a367545b64c4eaa3679..e23b0a1b2f25d0a75b1135c8f8ef34e6c60915db 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -275,9 +275,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	68  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -349,32 +348,32 @@
 
 /* List of I2C addresses to be verified by POST */
 #ifdef CONFIG_USE_FRAM
-#define I2C_ADDR_LIST	{  /*	CONFIG_SYS_I2C_AUDIO_ADDR, */	\
-				CONFIG_SYS_I2C_SYSMON_ADDR,	\
-				CONFIG_SYS_I2C_RTC_ADDR,	\
-				CONFIG_SYS_I2C_POWER_A_ADDR,	\
-				CONFIG_SYS_I2C_POWER_B_ADDR,	\
-				CONFIG_SYS_I2C_KEYBD_ADDR,	\
-				CONFIG_SYS_I2C_PICIO_ADDR,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR,	\
-			}
+#define CONFIG_SYS_POST_I2C_ADDRS	{/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+					 CONFIG_SYS_I2C_SYSMON_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_A_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_B_ADDR,	\
+					 CONFIG_SYS_I2C_KEYBD_ADDR,	\
+					 CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					}
 #else	/* Use EEPROM - which show up on 8 consequtive addresses */
-#define I2C_ADDR_LIST	{  /*	CONFIG_SYS_I2C_AUDIO_ADDR, */	\
-				CONFIG_SYS_I2C_SYSMON_ADDR,	\
-				CONFIG_SYS_I2C_RTC_ADDR,	\
-				CONFIG_SYS_I2C_POWER_A_ADDR,	\
-				CONFIG_SYS_I2C_POWER_B_ADDR,	\
-				CONFIG_SYS_I2C_KEYBD_ADDR,	\
-				CONFIG_SYS_I2C_PICIO_ADDR,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+0,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+1,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+2,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+3,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+4,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+5,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+6,	\
-				CONFIG_SYS_I2C_EEPROM_ADDR+7,	\
-			}
+#define CONFIG_SYS_POST_I2C_ADDRS	{/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+					 CONFIG_SYS_I2C_SYSMON_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_A_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_B_ADDR,	\
+					 CONFIG_SYS_I2C_KEYBD_ADDR,	\
+					 CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+0,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+1,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+2,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+3,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+4,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+5,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+6,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+7,	\
+					}
 #endif	/* CONFIG_USE_FRAM */
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index a4e92cce3b7b5bbb203ef9e2c24816411f861f22..4c9744ca4fa16fdacbbe32a6a0eb6ad3c0c6a538 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -87,10 +87,9 @@
  */
 #define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CONFIG_SYS_INIT_RAM_END		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /* unused GPT0 COMP reg	*/
 #define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
@@ -306,14 +305,13 @@
 #define CONFIG_SYS_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard		*/
 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* PIC I/O addr               */
 
-#define I2C_ADDR_LIST	{						\
-			CONFIG_SYS_I2C_RTC_ADDR,			\
-			CONFIG_SYS_I2C_EEPROM_CPU_ADDR,			\
-			CONFIG_SYS_I2C_EEPROM_MB_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_2_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_IO_ADDR }
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
+					 CONFIG_SYS_I2C_EEPROM_MB_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_2_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
+					 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
 
 /*
  * Pass open firmware flat tree
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index 26c2bcb6893ff1c841f5f6b9443dfe613a93d88d..68f0415a37b839a79e2d14dbeb39b3126e57c3cd 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -77,7 +77,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* Bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE			115200
 
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index c4853ab9c20db74f39bbc9f3ebcb5abac3d77e52..fcc789d714158349b5cd6c11b6eec943f6ad1215 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -88,9 +88,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
-#define CONFIG_SYS_INIT_RAM_END        (4 << 10)			/*  4 KiB */
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)			/*  4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * If the data cache is being used for the primordial stack and global
diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
index 7be135478ff5034ac268faf41605ae016dacbbba..3e4131eae171dad0fff741330983c9e3fd0309b8 100644
--- a/include/configs/manroland/mpc5200-common.h
+++ b/include/configs/manroland/mpc5200-common.h
@@ -113,9 +113,8 @@
 #define CONFIG_SYS_MBAR		0xF0000000
 #define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END -\
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
@@ -135,9 +134,9 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 4d946abb23c2a59aa5fcff9be5c7cc1799796d33..f1cdc4019eb7bfeffbaf4485ff46c5687891c6cf 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -259,11 +259,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h
index 4aef6fc9622b722cd75a6bea4cdf5b6a42e09a82..a1622916a03ba2904fe1ac2946fd8ee919498df9 100644
--- a/include/configs/mcu25.h
+++ b/include/configs/mcu25.h
@@ -71,9 +71,8 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* OCM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 1e82bc5ca7db8b7b2e30caf9d217cbf97b2204ac..b9cf1dc7975a2b260f1d2e84a0db2be4d5678048 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -206,10 +206,9 @@
 
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM addr */
-#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of monitor */
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 036b7904f353fcb5b944428f0e66991bd6d73aff..9961f122b1128323b912783850044c85c6da36bb 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -215,11 +215,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index dbb253143998c2774d58beae0fca239ff83ee261..a27b36b3786a3549d39e0aed0db6b55639bf0c92 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -48,7 +48,6 @@
 #undef CONFIG_USE_IRQ				/* don't need IRQ/FIQ stuff */
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #define CONFIG_MISC_INIT_R			/* Call misc_init_r */
 
 #define CONFIG_ARCH_CPU_INIT
@@ -182,7 +181,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
 					128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
 
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index 4dcd67919ba2978e6fc7682aa2b9dbbcc0b3402c..6dec0ee7403565d767548cd50a1e352915fea79b 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -178,9 +178,8 @@
 #define CONFIG_SYS_IMMR		0xF0000000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index bcdd86e9f3bd970da0e597c9459dc039d6c72e2b..75e4e076178a9d4214f94ff3bedfe3230dd912dc 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -135,15 +135,14 @@
 #define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
 
 /* global pointer */
-#define	CONFIG_SYS_GBL_DATA_SIZE	128 /* size of global data */
 /* start of global data */
 #define	CONFIG_SYS_GBL_DATA_OFFSET \
 	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE \
-				- CONFIG_SYS_GBL_DATA_SIZE)
+				- GENERATED_GBL_DATA_SIZE)
 
 /* monitor code */
 #define	SIZE				0x40000
-#define	CONFIG_SYS_MONITOR_LEN		(SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_MONITOR_LEN		(SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_MONITOR_BASE	\
 			(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
 #define	CONFIG_SYS_MONITOR_END \
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
index 74bab5fc4c1fe0bf41d60f227f0afd24fae3a496..57707f38e674d6c1a686822df5b1e6c022e07687 100644
--- a/include/configs/modnet50.h
+++ b/include/configs/modnet50.h
@@ -46,7 +46,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 935b5b9a052930320e285d72cf9e1e129e3fda3a..bdcae59e0df4207e8ed7685a4fcad2144a6979e3 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -47,29 +47,27 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DTT
-
+#define CONFIG_CMD_REGINFO
 
 /*
  * Serial console configuration
@@ -79,7 +77,6 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-
 /*
  * Ethernet configuration
  */
@@ -101,11 +98,14 @@
 #define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, "		\
 				"press \"<Esc><Esc>\" to stop\n", bootdelay
 
+#define CONFIG_CMDLINE_EDITING		1	/* add command line history	*/
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
 #define CONFIG_ETHADDR		00:50:C2:40:10:00
 #define CONFIG_OVERWRITE_ETHADDR_ONCE	1
 #define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
 
-
 /*
  * Default environment settings
  */
@@ -117,21 +117,22 @@
 	"serverip=192.168.1.1\0"					\
 	"gatewayip=192.168.1.1\0"					\
 	"console=ttyPSC0,115200\0"					\
-	"u-boot_addr=100000\0"						\
-	"kernel_addr=200000\0"						\
-	"fdt_addr=400000\0"						\
-	"ramdisk_addr=500000\0"						\
+	"u-boot_addr=400000\0"						\
+	"kernel_addr=400000\0"						\
+	"fdt_addr=700000\0"						\
+	"ramdisk_addr=800000\0"						\
 	"multi_image_addr=800000\0"					\
-	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
-	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
-	"bootfile=/tftpboot/motionpro/uImage\0"				\
-	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
-	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"u-boot=motionpro/u-boot.bin\0"					\
+	"bootfile=motionpro/uImage\0"					\
+	"fdt_file=motionpro/motionpro.dtb\0"				\
+	"ramdisk_file=motionpro/uRamdisk\0"				\
 	"multi_image_file=kernel+initrd+dtb.img\0"			\
 	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
-	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
+	"update=prot off fff00000 +${filesize};"			\
+		"era fff00000 +${filesize}; "				\
 		"cp.b ${u-boot_addr} fff00000 ${filesize};"		\
-		"prot on fff00000 fff3ffff\0"				\
+		"prot on fff00000 +${filesize}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
@@ -160,24 +161,20 @@
  */
 #define CONFIG_BOARD_EARLY_INIT_R	1
 
-
 /*
  * Low level configuration
  */
 
-
 /*
  * Clock configuration: SYS_XTALIN = 33MHz
  */
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000
 
-
 /*
  * Set IPB speed to 100MHz
  */
 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
 
-
 /*
  * Memory map
  */
@@ -186,7 +183,7 @@
  * Setting MBAR to otherwise will cause system hang when using SmartDMA such
  * as network commands.
  */
-#define CONFIG_SYS_MBAR		0xf0000000
+#define CONFIG_SYS_MBAR			0xf0000000
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 
 /*
@@ -203,10 +200,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
@@ -218,7 +214,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* 1 MiB for malloc() */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
 
-
 /*
  * Chip selects configuration
  */
@@ -251,7 +246,6 @@
 #define CONFIG_SYS_CS_BURST		0x00000000
 #define CONFIG_SYS_CS_DEADCYCLE	0x22222222
 
-
 /*
  * SDRAM configuration
  */
@@ -261,7 +255,6 @@
 #define SDRAM_CONTROL		0x504f0000
 #define SDRAM_MODE		0x00cd0000
 
-
 /*
  * Flash configuration
  */
@@ -299,7 +292,6 @@
 #define CONFIG_SYS_ATA_STRIDE		4
 #define CONFIG_DOS_PARTITION
 
-
 /*
  * I2C configuration
  */
@@ -308,7 +300,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
-
 /*
  * EEPROM configuration
  */
@@ -317,14 +308,12 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* 2ms/cycle + 3ms extra */
 #define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
 
-
 /*
  * RTC configuration
  */
 #define CONFIG_RTC_DS1337	1
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
-
 /*
  * Status LED configuration
  */
@@ -346,14 +335,12 @@ extern void __led_toggle(led_id_t id);
 extern void __led_set(led_id_t id, int state);
 #endif /* __ASSEMBLY__ */
 
-
 /*
  * Temperature sensor
  */
 #define CONFIG_DTT_LM75		1
 #define CONFIG_DTT_SENSORS	{ 0x49 }
 
-
 /*
  * Environment settings
  */
@@ -381,13 +368,11 @@ extern void __led_set(led_id_t id, int state);
  */
 #define CONFIG_SYS_GPS_PORT_CONFIG	0x1105a004
 
-
 /*
  * Motion-PRO's CPLD revision control register
  */
 #define CPLD_REV_REGISTER	(CONFIG_SYS_CS2_START + 0x06)
 
-
 /*
  * Miscellaneous configurable options
  */
@@ -406,7 +391,6 @@ extern void __led_set(led_id_t id, int state);
 
 #define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-
 /*
  * Various low-level settings
  */
@@ -415,7 +399,6 @@ extern void __led_set(led_id_t id, int state);
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 
-
 /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
 #define CONFIG_SYS_RESET_ADDRESS	0xfff00100
 
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 3138b493cd8d28e0099f9929228e748d81c30845..8e398d7205d6dce67abbdf2c8e9fc97791461d56 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -73,15 +73,12 @@
 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 #define CONFIG_BAUDRATE		115200
 
diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h
index afae1ab6dae1e18a64d090a8f017ecd1b7dee51b..a5e77c5a791302ffd1fc0df31ae5c7602a5b2d21 100644
--- a/include/configs/mpc5121-common.h
+++ b/include/configs/mpc5121-common.h
@@ -25,11 +25,10 @@
 
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM base */
-#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE /* End of area */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE /* Size of area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100	/* num bytes of initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index fbcc8392e7db5b232924f8675f8e72340b700a65..f966325a8e2859a4e59cabb3300cb8104ebeddff 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -270,10 +270,9 @@
 
 /* Use SRAM for initial stack */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_SRAM_SIZE		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE		/* Start of monitor */
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index 94a8c93b42b8f286d69179a02c85f094f4acfdbc..927446438ceb45742c5bc3e4f89cb804577a9937 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -221,10 +221,9 @@
  */
 #undef  CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0x07d00000	/* unused memory region */
-#define CONFIG_SYS_INIT_RAM_END	0x4000/* larger space - we have SDRAM initialized */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000/* larger space - we have SDRAM initialized */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128/* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 14f663f3b6ef24c82a7371ea0d4991eb6a94b0dd..d7a3a9690fe7581ce305e23d3d9402894cbff897 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -220,10 +220,9 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END		0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000 /* Size of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 0a472a65817f1355ebcc1b154a58e4af6ee730a8..311f524024da7788ade2cb762a07402ef0a3b4dc 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -57,7 +57,6 @@
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	256
 
 /* Memory */
 #define CONFIG_SYS_SDRAM_BASE		0x8C000000
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 0ea3527e30b0821ca886bf9bd9d18d08ff2f06cb..5304237a741528ae6adbbfddb22d7fff41c77a53 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -76,7 +76,6 @@
 #define CONFIG_SYS_MONITOR_BASE	MS7720SE_FLASH_BASE_1
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	256
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 02514285cc2008b188c42dc59d2cca1fddd0445d..1ddadf696d9ee4ea54bf46ed97c36b57bc5efb71 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -89,7 +89,6 @@
 							in Flash (NOT run time address in SDRAM) ?!? */
 #define CONFIG_SYS_MONITOR_LEN	(128 * 1024)		/* */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)		/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)		/* size in bytes reserved for initial data */
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 
 /* FLASH */
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 02090f23157de19141cc3d2c531b0fa5b50709b2..9b43acb2076589cfb318740a0bd4995ee27ca735 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -81,7 +81,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)			/* size in bytes reserved for initial data */
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 #define CONFIG_SYS_RX_ETH_BUFFER	(8)
 
diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
index 345bdd119a9c3cdca6d24e7f6ffb522ad5056744..8b3022b2c0974e0965ada9331e0942fb927d3a16 100644
--- a/include/configs/muas3001.h
+++ b/include/configs/muas3001.h
@@ -260,9 +260,8 @@
 #define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Hard reset configuration word */
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 97330d564010f5248a2331156c127d2155e3419a..425a1d83d7e0f78f32aa54fbb473630bbec299df 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -117,9 +117,8 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index bdcebd3b5dec128461e114e1a6dc9e3df3993561..de0121e3e6557b0d2e3a1f7a92abdc7715d72919 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -45,6 +45,22 @@
 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
 #define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
 
+/* 
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg 
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* 
+ * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_TEXT_BASE	0x00600000
+#endif /* CONFIG_SYS_TEXT_BASE */
+
 #define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
 #define MV_UART0_BASE		KW_UART0_BASE
 #define MV_SATA_BASE		KW_SATA_BASE
@@ -131,7 +147,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024) /* 1MiB for malloc() */
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Other required minimal configurations
@@ -142,6 +157,7 @@
 #define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
 #define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
 #define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */ 
 #define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
 #define CONFIG_NR_DRAM_BANKS	4
 #define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
index b2ffd3e935487849938ab4b2c6de1cb096ec2ca2..166da6ca7fd6f2e17122d9c26faddd3cce298a41 100644
--- a/include/configs/mx1ads.h
+++ b/include/configs/mx1ads.h
@@ -60,9 +60,6 @@
 
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 
-
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
 /*
  *  CS8900 Ethernet drivers
  */
@@ -80,7 +77,6 @@
 
 #define CONFIG_BAUDRATE		115200
 
-
 /*
  * BOOTP options
  */
@@ -89,7 +85,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -99,7 +94,6 @@
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_ELF
 
-
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"root=/dev/msdk mem=48M"
 #define CONFIG_BOOTFILE		"mx1ads"
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
index 90a8d8405b503fec999f866b1086f4aface3516a..1632ce82ba33fb2aeb873654996453f43e6c308f 100644
--- a/include/configs/mx1fs2.h
+++ b/include/configs/mx1fs2.h
@@ -34,7 +34,6 @@
 #undef	_CONFIG_UART4 /* internal uart 4 */
 #undef	CONFIG_SILENT_CONSOLE  /* use this to disable output */
 
-
 /*
  * BOOTP options
  */
@@ -43,7 +42,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -58,7 +56,6 @@
 #undef CONFIG_CMD_PING
 #undef CONFIG_CMD_SOURCE
 
-
 /*
  * Boot options. Setting delay to -1 stops autostart count down.
  */
@@ -98,9 +95,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN	  (CONFIG_ENV_SIZE + (128<<10) )
 
-
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
 #define CONFIG_STACKSIZE	(120<<10)      /* stack size */
 
 #ifdef CONFIG_USE_IRQ
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 57955dfc3b09ffb6fbd5ea29da66bd27a513f5b7..d2798e974bf07b83ab316d7380668e10f44b76f7 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -51,7 +51,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 4b4fb1a06a3f7cfc168b695dad7610bf9168125e..3b90a01623933b9995d229ebdb6667f60e310e36 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -47,7 +47,6 @@
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 
 /*
@@ -55,7 +54,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		(2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
 /* Bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 61654732706cbf616053f0dccdbc0139aa72cf8f..f98438d6373215f944cb829a81f009f117119946 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -24,11 +24,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */
 
 #define CONFIG_MX51	/* in a mx51 */
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 #define CONFIG_SYS_MX5_HCLK	24000000
 #define CONFIG_SYS_MX5_CLK32		32768
@@ -51,8 +51,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define BOARD_LATE_INIT
 
@@ -126,18 +124,42 @@
 
 #define CONFIG_LOADADDR		0x90800000	/* loadaddr env var */
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-		"netdev=eth0\0"						\
-		"uboot_addr=0xa0000000\0"				\
-		"uboot=u-boot.bin\0"			\
-		"loadaddr=0x90800000\0"			\
-		"bootargs_base=setenv bootargs console=tty "\
-			"console=ttymxc0,${baudrate}\0"\
-		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
-			"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
-		"bootcmd=run bootcmd_net\0"				\
-		"bootcmd_net=run bootargs_base bootargs_nfs; "		\
-			"tftpboot ${loadaddr} ${kernel}; bootm\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
 
 #define CONFIG_ARP_TIMEOUT	200UL
 
@@ -145,6 +167,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"MX51EVK U-Boot > "
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
@@ -175,6 +199,15 @@
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
 
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
 
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 1063d123d279a4117121d2a747608fa6e76b2e6f..8de5aaf1ed60067fbea0da7beb45fd6b569f8308 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -208,10 +208,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index c63c84650f044f500d492f7ddce07cdc2322ae73..f15901393441664f5aefe4cfc9111985f9acb4ca 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -72,7 +72,6 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
 /*
@@ -120,9 +119,6 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
-/*#define CONFIG_SKIP_LOWLEVEL_INIT */
-
 /*
  * Partitions (mtdparts command line support)
  */
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 2b640dca980b14782215096bbcd88b6ffa87c98e..49a16ab2066082c05a2fa2fe4d0903913685ef4d 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -90,7 +90,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x00000000
 #define CONFIG_SYS_MEMTEST_END		0x0FFFFFFF
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* for initial data */
 
 #define BOARD_LATE_INIT		/* call board_late_init during start up */
 
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
index e4bf57b7555630238a964cef067b12e419539776..53f2084d9f770dbc9279e6838e0e92590fb38cee 100644
--- a/include/configs/nios2-generic.h
+++ b/include/configs/nios2-generic.h
@@ -123,12 +123,11 @@
 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
 					 CONFIG_SYS_SDRAM_SIZE - \
 					 CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
 #define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
 					 CONFIG_SYS_MALLOC_LEN)
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
index 79dcd647c2d14fd56ad998e31416523ef61351bb..e6b774f2c318ef1ad20a76f4d4f72deba8d379ad 100644
--- a/include/configs/ns9750dev.h
+++ b/include/configs/ns9750dev.h
@@ -50,7 +50,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial
 					 * data */
 
 /*
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index c9c69bbab6c66bed5e7af352fefceadfeaa6ee47..9f5a0b89b7c200714005bf5029767a6a44f2c06a 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -214,11 +214,10 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index f33f0ff2c8c86b2adb2f3519aca5cc74b6ea3710..d0fe9dadfbe47c06ab50a92033f3b34238145d89 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -72,10 +72,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM  1
 #define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
index b0ebafd7bd0e2a37c410bc0069f977489adaf8b0..9ff4f843ccd6c1f2a8d5420b2adfa4ea41488a6b 100644
--- a/include/configs/omap1510inn.h
+++ b/include/configs/omap1510inn.h
@@ -50,7 +50,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h
index 0bbb5b35c155c162851572860a0b49a5f99017e4..2936dcc56f6916951f7ea6b294b8cfdffc701dab 100644
--- a/include/configs/omap1610h2.h
+++ b/include/configs/omap1610h2.h
@@ -52,7 +52,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
index 832dd426b6ebc518894f7375fca7d884ffbe4796..0b41c46648d87a4468fb471469f96b8a40951bd6 100644
--- a/include/configs/omap1610inn.h
+++ b/include/configs/omap1610inn.h
@@ -51,7 +51,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 47437b09c645f0e8f25d99dc6fb219a362f91ae2..7161ab18ca38167794172040799f7afbc9ef7893 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -72,7 +72,6 @@
  */
 #define CONFIG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
-#define CONFIG_SYS_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 900dbd3f7a06699828312ad8cc8b758b162d3366..1c9a0075b829b049ee5319998e677bfb0d44b846 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -75,7 +75,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
 /*
@@ -348,6 +347,6 @@ extern unsigned int boot_flash_type;
 
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index c4aa220f78900024875a89abee1fc8908ded30b3..e925f3bd2d63bafb4027f76c99c361a398b73e0d 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -71,7 +71,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 /*
  * Hardware drivers
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 69f912679eae05b29e8b5e5883f8ee85b39f690c..02920787458f6d59d61db3db16dbb19c34118cad 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -58,7 +58,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
 /*
@@ -325,6 +324,6 @@ extern unsigned int boot_flash_type;
 #endif /* (CONFIG_CMD_NET) */
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE)
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 3308aceb49264f9169b9382cbacf7b1adf6e08e2..b78aacfa088dcc79a4733765491efec05c91771f 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -61,7 +61,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
 /*
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 5439aa3dd9c74fb05e7fea2e20e79868f5bf0662..fab263d6cbd992b0728cb0215e5a2f4fabcc2c1a 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -78,7 +78,6 @@
  */
 #define CONFIG_ENV_SIZE			(256 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
 /*--------------------------------------------------------------------------*/
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index f612e0fd19f7758c28528b81aee75f355f203d57..10b248ad865ef17f914f0fb7064a73ad532991f8 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -67,7 +67,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 
 /*
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index aaf929e08e284da5b2722d30fc4819572fa52cfc..b7c301f8ed7eb9b21ffb3a9cd64c1e785b9b8de1 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -68,7 +68,6 @@
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 /*
  * Hardware drivers
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index b52ca19ae9ad6ee866900c093194d87406416181..74defabbf896ef27c204d54eb5103ca3529f4768 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -67,7 +67,6 @@
  */
 #define CONFIG_ENV_SIZE			(256 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 /* Vector Base */
 #define CONFIG_SYS_CA9_VECTOR_BASE	SRAM_ROM_VECT_BASE
@@ -228,6 +227,6 @@
 #define CONFIG_NR_DRAM_BANKS	1
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 174d73f0668b353d1019460d48b38bbdf8a60923..26c380d3e7eed95ff74ea6a8a475958fb64fe167 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -68,7 +68,6 @@
  */
 #define CONFIG_ENV_SIZE			(128 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
 /* Vector Base */
 #define CONFIG_SYS_CA9_VECTOR_BASE	SRAM_ROM_VECT_BASE
@@ -233,6 +232,6 @@
 #define CONFIG_NR_DRAM_BANKS	1
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
index bc660e39e829a86c5fdde4ab331168e60a01692c..b875464b0bd25161b3276182144818895cb27a32 100644
--- a/include/configs/omap5912osk.h
+++ b/include/configs/omap5912osk.h
@@ -54,7 +54,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
index a6a8a023f1b0ee40a5703a4f2442287276cf2cf1..fa3681e6dc6636fe0404ce3539ec2ae133a159ae 100644
--- a/include/configs/omap730p2.h
+++ b/include/configs/omap730p2.h
@@ -59,7 +59,6 @@
  */
 
 #define CONFIG_SYS_MALLOC_LEN		   (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	   128	     /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index 4a1cedec0fe8dfdb9f46a74a1faafd3af42ca240..ca3bf26215e92ed040b5ef28b9b737fe0ea361c9 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -48,7 +48,6 @@
 #undef CONFIG_USE_IRQ				/* don't need IRQ/FIQ stuff */
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
 
 #define CONFIG_ARCH_CPU_INIT
@@ -235,7 +234,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
 					128*1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
 
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 8b5ef8fa852fdcf7699715ab98f0f2c3ccae8764..71eb78495f2613d074601a3cfc03d7e0a81f1f1d 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -98,9 +98,8 @@
 */
 #undef	CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0x42000000
-#define CONFIG_SYS_INIT_RAM_END	0x1000
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 71529a23d3a96e7b27147aebf724b6d23ad64e58..719a12aaa0cbe4376a334a71a8ecd8a1e8d1e6e3 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -61,10 +61,9 @@
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x2000	    /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	    /* num bytes initial data	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	    /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
index 926728b15f4ac6771be1eb9d4b539d74ac55b9f6..65f1306f5cf4444010be8655e94ba7d420839bc3 100644
--- a/include/configs/palmld.h
+++ b/include/configs/palmld.h
@@ -33,7 +33,7 @@
  */
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define	CONFIG_SYS_GBL_DATA_SIZE	128
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #define	CONFIG_BOOTCOMMAND						\
 	"if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then "	\
@@ -155,7 +155,7 @@
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * NOR FLASH
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index fe87648ac60b4fb8e610d3aed3d02501d5c9032c..3f6c2f1108644bbd2421a82216ebf64606e37f59 100644
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -35,7 +35,7 @@
  */
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define	CONFIG_SYS_GBL_DATA_SIZE	128
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #define	CONFIG_BOOTCOMMAND						\
 	"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then "	\
@@ -156,7 +156,7 @@
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * NOR FLASH
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 5898b4e8221eb18e8b89f3a41c8876d431864743..676f40c51a1523fd34fe3d97414159ab9a696e90 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -223,12 +223,11 @@ RTC configuration
 #define CONFIG_SYS_DEFAULT_MBAR		0x80000000
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE	/* End of used */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used */
 								/* area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes */
 						/* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-						CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index afdd69cd78858c29f2e2c9bf7044e4c6e73fe8fd..deb5b332f1fea53f99d5dfea5dee20ea8ff48452 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -74,9 +74,8 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256			/* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 220f68658bc02064bb8e0ad38c73e0d3df78c8a7..33fa6ee8bd2fd2c6caf273238706e361ee56a32d 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -64,7 +64,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index 28dfe3b2ee7aee632d7921c46339e00dd108c98b..5830345921e7d0e5e9c62c55eb9300092a6613e8 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -221,10 +221,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 3b6e60afe9f5c754f49787ebf540a435efa1f7ee..64654f825e309f548a9f424e79e38a7ed857c92f 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -39,6 +39,7 @@
 #undef CONFIG_LCD
 #undef CONFIG_MMC
 #define BOARD_LATE_INIT		1
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
@@ -49,7 +50,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -155,15 +155,9 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
 
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
@@ -180,7 +174,7 @@
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * GPIO settings
@@ -213,9 +207,9 @@
 #define CONFIG_SYS_GAFR2_U_VAL		0x00000000
 
 #define CONFIG_SYS_PSSR_VAL		0x20
-#define CONFIG_SYS_CCCR_VAL	    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
-#define CONFIG_SYS_CKEN_VAL	    0x00000060	/* FFUART and STUART enabled	*/
-#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+#define CONFIG_SYS_CCCR		    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
+#define CONFIG_SYS_CKEN		    0x00000060	/* FFUART and STUART enabled	*/
+#define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/
 
 /*
  * Memory settings
@@ -231,6 +225,9 @@
 					   /* bits set in lowlevel_init.S	*/
 #define CONFIG_SYS_MDMRS_VAL		0x00000000
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
  * PCMCIA and CF Interfaces
  */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index a0b00e9706a5beda3586ae17a29b6554887767e1..7fcc9babdc89549c951d06fe05fcf546335d3282 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -152,7 +152,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -370,7 +369,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		\
 		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 #define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
 
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 9735e6a0797f35b12b595ae2c12c964fd2d5ca36..619af2d9bfca0b79dc9bf33c15357f57741a1126 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -161,7 +161,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #undef CONFIG_SKIP_LOWLEVEL_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 #define CONFIG_USER_LOWLEVEL_INIT	1
 
 /*
@@ -401,7 +400,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
 
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 690f119f4cd94a1971c3736ce097ed60fd940a10..3ed6b56bfe2d30f5b4ee690fdb5f93fdc5c4266d 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -47,7 +47,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -175,7 +174,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
 					0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE		(32*1024)	/* regular stack */
 
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index e7584c3a2957fddc5190b2f5755ee66e260f1183..652b85efd594c332f9034069346acb2e0f26fa59 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -297,15 +297,14 @@
  * copied to top of RAM by the init code.
  *
  * CONFIG_SYS_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
- * CONFIG_SYS_INIT_RAM_END		- Size of Init RAM
- * CONFIG_SYS_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
+ * CONFIG_SYS_INIT_RAM_SIZE		- Size of Init RAM
+ * GENERATED_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
  * CONFIG_SYS_GBL_DATA_OFFSET		- Start of global data, top of stack
  */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x4000)
-#define CONFIG_SYS_INIT_RAM_END	0x4000
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 
 /*
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index 7018a8c3c78d2f4acf9b96b77cb1894cf0260696..68c62770f23757dcdb813a113ed9ed176acefaea 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -422,9 +422,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 4581674ed3a55381866fea4d897157e91683352b..c1c7f80d4b24deac235130b3b1561101c2ac4279 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -42,7 +42,7 @@
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
 #undef CONFIG_SKIP_LOWLEVEL_INIT			/* define for developing */
-#undef CONFIG_SKIP_RELOCATE_UBOOT			/* define for developing */
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 /*
  * define the following to enable debug blinks.  A debug blink function
@@ -75,7 +75,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * PXA250 IDP memory map information
@@ -271,7 +270,7 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 1 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
 #define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
@@ -293,7 +292,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * GPIO settings
@@ -317,6 +316,9 @@
 
 #define CONFIG_SYS_PSSR_VAL		0x20
 
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+#define	CONFIG_SYS_CKEN			0x0
+
 /*
  * Memory settings
  */
@@ -326,6 +328,8 @@
 #define CONFIG_SYS_MDCNFG_VAL		0x090009C9
 #define CONFIG_SYS_MDREFR_VAL		0x0085C017
 #define CONFIG_SYS_MDMRS_VAL		0x00220022
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces
diff --git a/include/configs/qong.h b/include/configs/qong.h
index 426d90d7dea780b18609dd4ca345e7b14a364a1a..e2f7a5e9f9fc13f5e61b3024bdb5dadc63ee97ff 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -43,7 +43,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
@@ -300,8 +299,8 @@ extern int qong_nand_rdy(void *chip);
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_END		IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
 
 #define CONFIG_BOARD_EARLY_INIT_F	1
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index f847f9cb33dda0873b21eb9b3807347d28231ee5..5fd7838d52a52862bf0a11c7c2d2d8247daa1b26 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -247,10 +247,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
index 2440eee7c07cb1c217cc03041bfee0f559de5552..0ebb0940826e2e7926ebfafb35dfa2c0a70271b7 100644
--- a/include/configs/quantum.h
+++ b/include/configs/quantum.h
@@ -158,9 +158,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index bc518db7e2fdf4363d28abb0cc6a10a2aeb9829e..ade6f7c7086efe894738a301d14e4e208033fc4d 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -58,7 +58,6 @@
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /*
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 41376da200359a7547021e5b97fb734beb0d7d2f..3416cb897e11c5c1ad46ca62b003f1c295f37d8d 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -101,7 +101,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(1204 * 1024)
 
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 #define CONFIG_SYS_RX_ETH_BUFFER	(8)
 
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
index a7d5dac9af8ba364ff2547ce0a7d86e3d9af5225..f75ab6781826455266bf1bf963ecafcd8d70e0fa 100644
--- a/include/configs/redwood.h
+++ b/include/configs/redwood.h
@@ -89,10 +89,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index 5e6bc27e097577d41f87e67fc6305657d306def6..064716f904f0d91bc96e86a14b8741a4440fc757 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -154,9 +154,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index b82ff372a60935f52327cb1d7a6170a24a892f77..5761f20a19e820f65f61576905fd4f6433ccb77d 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -253,9 +253,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index 9aa71b4496a6e84e539c0a85ffd0e1aab940593a..b3feaa8c33276b5314dce8eccbdb33eed6e803e1 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -78,7 +78,6 @@
 #define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	256
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /* FLASH */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index dc01ceb7b26a653075b92f4f00a9907953f36e2f..541aec05ff18d0b5ff71a19fbc16b771c0cb6c98 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -40,8 +40,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
 /* input clock of PLL: has 24MHz input clock at S5PC110 */
 #define CONFIG_SYS_CLK_FREQ_C110	24000000
 
@@ -58,7 +56,6 @@
  * 1MB = 0x100000, 0x100000 = 1024 * 1024
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for */
 						/* initial data */
 /*
  * select serial console configuration
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index d7417164cb3099290577157197bf4ae65b5ff56e..32e0444a2fb197c0d8873ee58385ed743a6d3af2 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -673,9 +673,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index 025ad0953c2807115f86aa80897fedb888326e68..f0f19b2712cb6acfc1806c4fc53c11ed998394b8 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -59,7 +59,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index b9f27cc95b7870a10e688f6aead97c9e9045e6e3..00f4dc9f7c08bd2606c2e07ed92d044394319010 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -54,7 +54,6 @@
 #define CONFIG_INITRD_TAG		1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -187,7 +186,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 #define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
 
 #ifdef CONFIG_USE_IRQ
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index 3de2a9efb88e195612d24f8fbd3ce2cbb6880fde..6f0d728f906e3d8df2527f05b57cf1bdcb775b31 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -264,9 +264,8 @@
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h
index 0934a002bfdf7ecd0f2dc62c49d824918404281f..5993be6006a06778dca694a13dc8551dcd1c77ff 100644
--- a/include/configs/sbc8240.h
+++ b/include/configs/sbc8240.h
@@ -201,11 +201,10 @@ typedef unsigned int led_id_t;
 
 	/* Size in bytes reserved for initial data
 	 */
-#define CONFIG_SYS_GBL_DATA_SIZE    128
 
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 54a1a36e292fd1b7bc711494170ffd38a5f0fdc5..0d83337254a5116bc29b8f44bf2a8e76b424ecd8 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -572,9 +572,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index ee2292ce8648088f23db86f90624029d66614a35..b418cf23baf60e8fc0daf3dfe434bad68e969dc6 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -169,10 +169,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x1000			/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000			/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 0ddd20d376b7f0adf4fc33e8dd3863c457434924..7bf9fc76c2168a5b301d76aa71c5807fa22528e4 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -321,12 +321,11 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index cd9652cfc3efa8c3ea7636fa674ed9178dd68d0b..101c5d943d306f306074dea67f8cce6a431d1e96 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -191,10 +191,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 9e2aef42eb96ef3dd973c06ae676d9f55489b625..90d84eba8aedc09a2454107a9ac1206066f60f7e 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -249,10 +249,9 @@
 #else
 #define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
 #endif
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 3e6abf34e4805b4135a26c33a68c110b8fce05dc..04511057efdbee8bafd7fb5ef5d2174e1d9f33dd 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -463,7 +463,7 @@
 /* Where the internal SRAM starts */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
 /* Where the internal SRAM ends (only offset) */
-#define CONFIG_SYS_INIT_RAM_END	0x0F00
+#define CONFIG_SYS_INIT_RAM_SIZE	0x0F00
 
 /*
 
@@ -476,13 +476,12 @@
 			   |	      |
 			   | 64 Bytes |
 			   |	      |
- CONFIG_SYS_INIT_RAM_END  ------> ------------ higher address
+ CONFIG_SYS_INIT_RAM_SIZE  ------> ------------ higher address
   (offset only)
 
 */
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE     64
-#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* Initial value of the stack pointern in internal SRAM */
 #define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index 555671464bb33e09b370a74d607f0889c3288f08..3da214e99dda14857464b1f00745dbf53df58f33 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -35,7 +35,6 @@
  * Select serial console configuration
  */
 
-
 /*
  * BOOTP options
  */
@@ -44,7 +43,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -58,7 +56,6 @@
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_SOURCE
 
-
 /*
  * Boot options. Setting delay to -1 stops autostart count down.
  * NOTE: Sending parameters to kernel depends on kernel version and
@@ -100,15 +97,11 @@
 #define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */
 #undef	CONFIG_VFD			 /* do not send framebuffer setup    */
 
-
 /*
  * Malloc pool need to host env + 128 Kb reserve for other allocations.
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10) )
 
-
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
 #define CONFIG_STACKSIZE	(120<<10)      /* stack size		     */
 
 #ifdef CONFIG_USE_IRQ
@@ -134,15 +127,6 @@
 #define SCB9328_SDRAM_1		0x08000000	/* SDRAM bank #1	   */
 #define SCB9328_SDRAM_1_SIZE	0x01000000	/* 16 MB		   */
 
-/*
- * Flash Controller settings
- */
-
-/*
- * Hardware drivers
- */
-
-
 /*
  * Configuration for FLASH memory for the Synertronixx board
  */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 412deeadb6fe682f8aa723064a81c8fb6d147bcf..a406ca032ce9153d023a3199083ce255a8cf3b0d 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -98,9 +98,8 @@
  */
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index c8c62ad76e391177482680110fe835a4cc681403..209cb88f3f33fe442b4754beac4576c8e53737ee 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -85,7 +85,6 @@
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 #define CONFIG_SYS_FLASH_CFI
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index 2c18e2f7fdf1e039a0c664740bcd0b00a60cd1ac..591fb5cd158d0c3c40ea401235360bb4d9ec38bf 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -62,8 +62,10 @@
 
 /* MEMORY */
 #if defined(CONFIG_SH_32BIT)
-#define SH7785LCR_SDRAM_PHYS_BASE	(0x48000000)
-#define SH7785LCR_SDRAM_BASE		(0x88000000)
+/* 0x40000000 - 0x47FFFFFF does not use */
+#define CONFIG_SH_SDRAM_OFFSET		(0x8000000)
+#define SH7785LCR_SDRAM_PHYS_BASE	(0x40000000 + CONFIG_SH_SDRAM_OFFSET)
+#define SH7785LCR_SDRAM_BASE		(0x80000000 + CONFIG_SH_SDRAM_OFFSET)
 #define SH7785LCR_SDRAM_SIZE		(384 * 1024 * 1024)
 #define SH7785LCR_FLASH_BASE_1		(0xa0000000)
 #define SH7785LCR_FLASH_BANK_SIZE	(64 * 1024 * 1024)
@@ -108,7 +110,6 @@
 #define CONFIG_SYS_MONITOR_BASE	(SH7785LCR_FLASH_BASE_1)
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 
 /* FLASH */
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
index d848915d0e99761779a6ba2a78bd4467f1f0ff52..c0e6643fb401c0a89cf389398ce36d97b65065ce 100644
--- a/include/configs/shannon.h
+++ b/include/configs/shannon.h
@@ -34,7 +34,6 @@
  */
 #define CONFIG_INFERNO			/* we are using the inferno bootldr */
 #define CONFIG_SKIP_LOWLEVEL_INIT	1
-#undef  CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * High Level Configuration Options
@@ -51,7 +50,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index fd51219af4cddd1d2e656030aaa92a9d09f3b057..064749e2d6d67b057a1df42cc723db1654ae7341 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -52,7 +52,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index f9d1e55186fc783c3280de7eceb26a43a8c84c94..62fe97e76ac02c19a457ac55d770516c1e46c0aa 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -49,7 +49,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 451b53430c250980a1a2c5656432776f18de942b..671f2c7c8b1df6347b490cf1cdcc8b8ef7fc1f45 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -40,8 +40,6 @@
 #define CONFIG_S3C64XX		1	/* in a SAMSUNG S3C64XX Family  */
 #define CONFIG_SMDK6400		1	/* on a SAMSUNG SMDK6400 Board  */
 
-#define CONFIG_SKIP_RELOCATE_UBOOT
-
 #define CONFIG_PERIPORT_REMAP
 #define CONFIG_PERIPORT_BASE	0x70000000
 #define CONFIG_PERIPORT_SIZE	0x13
@@ -71,7 +69,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index bfd09a0916eed7ea9668eb10beba485dd2bb38ae..e36b262a8ec56b8471f3e13e0ba5691b9773d5cd 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -45,8 +45,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
 /* input clock of PLL: SMDKC100 has 12MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		12000000
 
@@ -63,7 +61,6 @@
  * 1MB = 0x100000, 0x100000 = 1024 * 1024
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for */
 						/* initial data */
 /*
  * select serial console configuration
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 0bbad161f6f8b0bad80435fbf49f1f4bde6fa083..5f2fb1e9279cf89c6656c02a450f6035b40990d5 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -170,10 +170,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384KiB for Mon */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
index 75b8e600e573b1c3d0424d5295d25b424c587f7c..f1cbe95715e3b239191fbd974c4f303367b9be55 100644
--- a/include/configs/sorcery.h
+++ b/include/configs/sorcery.h
@@ -227,10 +227,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in DPRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 4d1874714275e640416af96f04a165fcf2611d8e..e39d3bd944b4f12bf6dca847b258aec6398f00d1 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -143,9 +143,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index cc52e39ffb6cc082763ffe8d61410eb27e654f92..4e5bdea369a34ebb30ff23b498b29ac4d41ad522 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -181,7 +181,6 @@
 #define CONFIG_SYS_MEMTEST_START		0x00800000
 #define CONFIG_SYS_MEMTEST_END			0x04000000
 #define CONFIG_SYS_MALLOC_LEN			(1024*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE		128
 #define CONFIG_IDENT_STRING			"-SPEAr"
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_PROMPT			"u-boot> "
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index b5ac1689b886831e2d191a7ce4582255bd84e598..d6195b186a384c01211f5d668ba5c0e8e23af00f 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -271,10 +271,10 @@
 
 /* List of I2C addresses to be verified by POST */
 #if defined (CONFIG_MINIFAP)
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST	{	CONFIG_SYS_I2C_EEPROM_ADDR,	\
-				CONFIG_SYS_I2C_HWMON_ADDR,	\
-				CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_HWMON_ADDR,	\
+					 CONFIG_SYS_I2C_SLAVE}
 #endif
 
 /*
@@ -322,14 +322,13 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 479fbab4cb001d9870a90a4c9bb85c6552caf4cf..c2497ad09c1266d374cf579e8ab60d697d1f6366 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -155,10 +155,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 6ea58074bb5b260b1ccf55a6d30e0b36466832ff..996120a02b1b022df4d8e1cf3f0d2abd8b29801b 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -167,10 +167,9 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index b9739ff19c63fe9003e0b73c78234da5d26a9ecb..890186e914832058f029f195b8d92c07c0a78269 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -168,9 +168,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 219b85b59000dc8f422fbb4f1937803ba41da5ea..22486807f44c127a8ce7baba24f2326c45438f4a 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -193,9 +193,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index d00e64eff291cc8f71b84a6333179448fe5d7023..6115a5f41326b64f60be40ccbbb9862a4fa9b2b4 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -97,10 +97,9 @@
  * Initial RAM & stack pointer (placed in OCM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256	/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index 6e9dbc5759395d9ce8ded01d3febc70c2718b463..a3738b7b1d2dcafb9db2c96b566eb51ad9abed15 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -288,10 +288,9 @@ unsigned char spi_read(void);
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 12f35ae1f4a71e8313207415111284d36f267e9a..3046081c52efc5fd5e637f00b4cc1e946028c405 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -68,10 +68,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
index f423a0eb2699baf14b62efaa1960209483640a33..68290efca5624bd41cd8d7870b6c759590c86ae9 100644
--- a/include/configs/tnetv107x_evm.h
+++ b/include/configs/tnetv107x_evm.h
@@ -50,7 +50,6 @@
 
 /* Memory Info */
 #define CONFIG_SYS_MALLOC_LEN		(0x10000 + 1*1024*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define PHYS_SDRAM_1			TNETV107X_DDR_EMIF_DATA_BASE
 #define PHYS_SDRAM_1_SIZE		0x04000000
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h
index 5af2af3d1cb5efb52b02d259fdeeaca4e5eb3181..7b18022c6e36c7f10a31d453aeba86f37bad8182 100644
--- a/include/configs/tny_a9260.h
+++ b/include/configs/tny_a9260.h
@@ -63,7 +63,6 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 
 /*
  * Hardware drivers
@@ -164,7 +163,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
 
 #define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
 
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 9827195e8d59102ece270f38839844046f6c28f8..d5736a23d22545c0a50b8b0434ab4393a98f72cb 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -95,7 +95,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 474349537bdd63c3f445426c1cb1f8593173fbef..2512f93f9c682940462f37b61f94903a2eff27be 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -44,6 +44,7 @@
 
 #define CONFIG_MMC		1
 #define BOARD_LATE_INIT		1
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
@@ -56,7 +57,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -213,7 +213,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * GPIO settings
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 996afa3b0706b3f066fed214f25bcd70a397df5e..8f8a1a377ebc6e0f4bb3a7c1bbf02dd77492051b 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -66,7 +66,6 @@
 /* malloc() len */
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
 /* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 /*
  * Board has 2 32MB banks of DRAM but there is a bug when using
  * both so only the first is configured
@@ -179,6 +178,6 @@
 /* additions for new relocation code, must be added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
-					CONFIG_SYS_GBL_DATA_SIZE)
+					GENERATED_GBL_DATA_SIZE)
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
index 5392fb590794e21b1182c0fdb5a19f2055ff120b..9da318d4278ba0fb6b9e70cd3f777321fbdf7810 100644
--- a/include/configs/uc100.h
+++ b/include/configs/uc100.h
@@ -200,9 +200,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
index c027f46e5d288d95f73a82a34d5d24d70d59b5f8..bb9f606a05f6f038f8cacd5a268d45b2c1a12e06 100644
--- a/include/configs/utx8245.h
+++ b/include/configs/utx8245.h
@@ -196,10 +196,9 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}"
 #define CONFIG_SYS_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
 									/* initial data */
 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
-#define CONFIG_SYS_INIT_RAM_END      0x1000
-#define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*--------------------------------------------------------------------
  * NS16550 Configuration
diff --git a/include/configs/v37.h b/include/configs/v37.h
index c34b6e86786e92b93164994a25bfc8e1797dea0a..a3fdc38ae1fb455c99f40f7adbeb2a8bf971fa26 100644
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@@ -158,9 +158,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 96ffc6a0d52b5df39f86214893abb99b123ed288..47bb84610df92c87ad86e04dfb8feb5450c5fc8f 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -227,10 +227,9 @@
 
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 283b92c433872af40ca372f430f3c6c8beb5ddfc..abb57fe94c560ef0e044e8d3e647ddaa5cad668a 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -171,11 +171,10 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END		0x1000	/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000	/* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 4273b84a44a931ae24cfaf8984b88e8473cb712c..45d8434437de7b74d4dd360f09a29ad3f39dd228 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -76,7 +76,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index 56fb5f7110e1956d9b7feedb311f970ad903c24d..466d930b98305bcd59267fb11f04044d33b99a18 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -176,9 +176,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index a2ecbe50d63f5b524f3d5c4114d5799cfff6eac8..a5c116b347f804d6fa97850aeaec7cf8468ad31b 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -46,7 +46,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(2048 * 1024)
 
 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 
 /*
  * Hardware drivers
@@ -191,18 +190,11 @@
 #define CONFIG_SYS_SDRAM_BASE		0x90000000
 #define CONFIG_SYS_INIT_RAM_ADDR	0x1FFE8000
 
-#ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
-#define CONFIG_SYS_INIT_RAM_END		(64 * 1024)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		(64 * 1024)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
 					CONFIG_SYS_GBL_DATA_OFFSET)
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + 0x2000)
-#endif
-
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* 166 MHz DDR RAM */
@@ -211,4 +203,18 @@
 
 #define CONFIG_SYS_NO_FLASH
 
+/*
+ * Framebuffer and LCD
+ */
+#define CONFIG_PREBOOT
+#define CONFIG_LCD
+#define CONFIG_VIDEO_MX5
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP		LCD_COLOR16
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+
 #endif				/* __CONFIG_H */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 2c95c121f372bc251438fb5b8e65d78c92d71017..d153762885f2aa0677022c6e1b9888df783c04e5 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -161,11 +161,10 @@
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_END		0x1000		/* size */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* size */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* size init data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index d46717cd25301a468cc1dab87657e432f7aabaa8..c258030e297d84a92175ccf5b8329209a20d1497 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -71,7 +71,6 @@
 /*
  * Size of malloc() pool and stack
  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 #define CONFIG_STACKSIZE		(1 * 1024 * 1024)
 
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index c9d9c69cda87e6811ffbd04106573d8e37720fe7..35afcd356c58d37161339e133e1515bec74ec526 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -27,13 +27,13 @@
  */
 #define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_VPAC270		1	/* Voipac PXA270 board */
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 /*
  * Environment settings
  */
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define	CONFIG_SYS_GBL_DATA_SIZE	128
 #define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_BOOTCOMMAND						\
 	"if mmc init && fatload mmc 0 0xa4000000 uImage; then "		\
@@ -184,7 +184,7 @@
 #define	CONFIG_SYS_IPL_LOAD_ADDR	(0x5c000000)
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define	CONFIG_SYS_INIT_SP_ADDR		\
-	(PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048)
+	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
 
 /*
  * NOR FLASH
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index 72ac4e33c2cde994b0f64374d1d7d44b9828620e..d10f74843d26c01665a7f19a84a8e4628d94e1e0 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -217,9 +217,8 @@
 #define CONFIG_SYS_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
 
 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
deleted file mode 100644
index a961a27922ceb7783b220259d3e18d7d6f0c9a21..0000000000000000000000000000000000000000
--- a/include/configs/wepep250.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PXA250          1        /* this is an PXA250 CPU     */
-#define CONFIG_WEPEP250        1        /* config for wepep250 board */
-#undef  CONFIG_USE_IRQ                  /* don't need use IRQ/FIQ    */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_BTUART          1       /* BTUART is default on WEP dev board */
-#define CONFIG_BAUDRATE   115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_SOURCE
-
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY   -1
-#define CONFIG_BOOTARGS    "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8"
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CONFIG_SYS_LONGHELP                                  /* undef saves memory  */
-#define CONFIG_SYS_PROMPT              "WEP> "               /* prompt string       */
-#define CONFIG_SYS_CBSIZE              256                   /* console I/O buffer  */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
-#define CONFIG_SYS_MAXARGS             16                    /* max command args    */
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE            /* boot args buf size  */
-
-#define CONFIG_SYS_MEMTEST_START       0xa0400000            /* memtest test area   */
-#define CONFIG_SYS_MEMTEST_END         0xa0800000
-
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_SYS_CPUSPEED            0x141        /* core clock - register value  */
-
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG           1   /* send commandline to Kernel       */
-#define CONFIG_SETUP_MEMORY_TAGS     1   /* send memory definition to kernel */
-#undef  CONFIG_INITRD_TAG                /* do not send initrd params        */
-#undef  CONFIG_VFD                       /* do not send framebuffer setup    */
-
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN	  (CONFIG_ENV_SIZE + (128<<10) )
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-
-#define CONFIG_STACKSIZE        (120<<10)      /* stack size */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4<<10)        /* IRQ stack  */
-#define CONFIG_STACKSIZE_FIQ    (4<<10)        /* FIQ stack  */
-#endif
-
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS    1                /* we have 1 bank of SDRAM */
-#define WEP_SDRAM_1            0xa0000000        /* SDRAM bank #1           */
-#define WEP_SDRAM_1_SIZE       0x02000000        /* 32 MB ( 2 chip )        */
-#define WEP_SDRAM_2            0xa2000000        /* SDRAM bank #2           */
-#define WEP_SDRAM_2_SIZE       0x00000000        /* 0 MB                    */
-#define WEP_SDRAM_3            0xa8000000        /* SDRAM bank #3           */
-#define WEP_SDRAM_3_SIZE       0x00000000        /* 0 MB                    */
-#define WEP_SDRAM_4            0xac000000        /* SDRAM bank #4           */
-#define WEP_SDRAM_4_SIZE       0x00000000        /* 0 MB                    */
-
-#define CONFIG_SYS_DRAM_BASE           0xa0000000
-#define CONFIG_SYS_DRAM_SIZE           0x02000000
-
-/* Uncomment used SDRAM chip */
-#define WEP_SDRAM_K4S281633
-/*#define WEP_SDRAM_K4S561633*/
-
-
-/*
- * Configuration for FLASH memory
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* number of sector in FLASH bank    */
-#define WEP_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
-#define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */
-#define WEP_FLASH_BANK_SIZE  0x2000000  /* size of one flash bank*/
-#define WEP_FLASH_SECT_SIZE  0x0040000  /* size of erase sector */
-#define WEP_FLASH_BASE       0x0000000  /* location of flash memory */
-#define WEP_FLASH_UNLOCK        1       /* perform hw unlock first */
-
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
-   is not so clear to me. In other words we can provide more informations
-   to user, but this expects more complex flash handling we do not provide
-   now.*/
-#undef  CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Write operation */
-
-#define CONFIG_SYS_FLASH_BASE          WEP_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK		0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR		5
-#define CONFIG_SYS_JFFS2_NUM_BANKS		1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128kb ( 1 flash sector )  */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		0x20000	        /* absolute address for now  */
-#define CONFIG_ENV_SIZE		0x2000
-
-#define	PHYS_SDRAM_1			WEP_SDRAM_1
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-#undef  CONFIG_ENV_OVERWRITE                    /* env is not writable now   */
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CONFIG_SYS_LOAD_ADDR        0x40000
-
-#endif  /* __CONFIG_H */
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 67d4106d6f1b8a5d0b96e95f1c40dcf5b591f3c1..a75c426dfa21e32324bccafebb253a2bf5fae723 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -42,6 +42,7 @@
  */
 #define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
 #define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 
 #define BOARD_LATE_INIT		1
@@ -114,7 +115,6 @@
  * used for the RAM copy of the uboot code
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Miscellaneous configurable options
@@ -168,7 +168,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * FLASH and environment organization
@@ -437,8 +437,9 @@
  */
 #define CONFIG_SYS_PSSR_VAL		0x00000030
 
-#define CONFIG_SYS_CKEN_VAL            0x00000080  /*  */
-#define CONFIG_SYS_ICMR_VAL            0x00000000  /* No interrupts enabled        */
+#define CONFIG_SYS_CKEN			0x00000080  /*  */
+#define CONFIG_SYS_ICMR			0x00000000  /* No interrupts enabled        */
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
 
 
 /*
@@ -562,6 +563,9 @@
  */
 #define CONFIG_SYS_MDMRS_VAL		0x00320032
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
  * PCMCIA and CF Interfaces
  */
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index b4a96759355a2834562bcc6ae9cda39aebbe376c..2422c0b0c34b45ebf780d5b4eec2b73b1cafe9d7 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -91,10 +91,9 @@
 
 /*Stack*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x800000/* Initial RAM address    */
-#define CONFIG_SYS_INIT_RAM_END		0x2000	/* End of used area in RAM  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data   */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
-				- CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000	/* Size of used area in RAM  */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+				- GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /*Speed*/
 #define CONFIG_SYS_CLK_FREQ	XPAR_CORE_CLOCK_FREQ_HZ
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 2ff9a2813adc9f4e25ecb656ce97531b30416c60..497cb9198f8e7c33afdd1456572103ad9e39eed3 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -35,6 +35,7 @@
 #define CONFIG_PXA250	       1	/* This is an PXA250 CPU	*/
 #define CONFIG_XM250	       1	/* on a MicroSys XM250 Board	*/
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 /* we will never enable dcache, because we have to setup MMU first */
 #define CONFIG_SYS_NO_DCACHE
@@ -45,7 +46,6 @@
  *
  */
 #define CONFIG_SYS_MALLOC_LEN		(256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -175,7 +175,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * FLASH and environment organization
@@ -322,9 +322,9 @@
  * Clocks, power control and interrupts
  */
 #define CONFIG_SYS_PSSR_VAL	    0x00000030
-#define CONFIG_SYS_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
-#define CONFIG_SYS_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
-#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+#define CONFIG_SYS_CCCR		    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
+#define CONFIG_SYS_CKEN		    0x000141ec	/* FFUART and STUART enabled	*/
+#define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/
 
 /* FIXME
  *
@@ -343,6 +343,8 @@
 #define CONFIG_SYS_MDCNFG_VAL	    0x000009c9
 #define CONFIG_SYS_MDMRS_VAL	    0x00220022
 #define CONFIG_SYS_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
diff --git a/include/configs/XPEDITE1000.h b/include/configs/xpedite1000.h
similarity index 97%
rename from include/configs/XPEDITE1000.h
rename to include/configs/xpedite1000.h
index 560584977423371681d67128b98dc8b180acc310..cd7148df1537b1872ed7f0011799cef3ee92ab2b 100644
--- a/include/configs/XPEDITE1000.h
+++ b/include/configs/xpedite1000.h
@@ -33,6 +33,7 @@
 /* High Level Configuration Options */
 #define CONFIG_XPEDITE1000	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite1000"
+#define CONFIG_SYS_FORM_PMC	1
 #define CONFIG_4xx		1		/* ... PPC4xx family */
 #define CONFIG_440		1
 #define CONFIG_440GX		1		/* 440 GX */
@@ -101,9 +102,8 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END		0x2000	/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000	/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 KB for Mon */
@@ -341,8 +341,8 @@ extern void out32(unsigned int, unsigned long);
 	"misc_args=ip=on\0"						\
 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 	"bootfile=/home/user/file\0"					\
-	"osfile=/home/user/uImage-XPedite1000\0"			\
-	"fdtfile=/home/user/xpedite1000.dtb\0"				\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
 	"fdtaddr=c00000\0"						\
 	"osaddr=0x1000000\0"						\
diff --git a/include/configs/XPEDITE5170.h b/include/configs/xpedite517x.h
similarity index 94%
rename from include/configs/XPEDITE5170.h
rename to include/configs/xpedite517x.h
index 1851997916c07970220e02fc6bdef759ade87b00..cb83a646711d6fd4ca7cb0bf6fb9c284c23993bf 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/xpedite517x.h
@@ -22,7 +22,7 @@
  */
 
 /*
- * xpedite5170 board configuration file
+ * xpedite517x board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -34,6 +34,7 @@
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_XPEDITE5140	1	/* MPC8641HPCN board specific */
 #define CONFIG_SYS_BOARD_NAME	"XPedite5170"
+#define CONFIG_SYS_FORM_3U_VPX	1
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
@@ -107,6 +108,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY |\
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_DS1621_ADDR,	\
+					 CONFIG_SYS_I2C_DS4510_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_LM90_ADDR,	\
+					 CONFIG_SYS_I2C_PCA9553_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
+					 CONFIG_SYS_I2C_PEX8518_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST		{0x50}
 
 /*
  * Memory map
@@ -202,10 +218,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
-#define CONFIG_SYS_INIT_RAM_END		0x00004000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
@@ -258,6 +273,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_DS1621_ADDR	0x48
 #define CONFIG_DTT_DS1621
 #define CONFIG_DTT_SENSORS		{ 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4c
 
 /* I2C EEPROM - AT24C128B */
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
@@ -281,6 +297,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
 #define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+#define CONFIG_SYS_I2C_PCA9553_ADDR	0x62
 
 /*
  * PU = pulled high, PD = pulled low
@@ -324,18 +341,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* PCIE1 - PEX8518 */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
 /* PCIE2 - VPX P1 */
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
 
@@ -545,6 +562,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SNTP
@@ -725,8 +743,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 	"misc_args=ip=on\0"						\
 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 	"bootfile=/home/user/file\0"					\
-	"osfile=/home/user/uImage-XPedite5170\0"			\
-	"fdtfile=/home/user/xpedite5170.dtb\0"				\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
 	"fdtaddr=c00000\0"						\
 	"osaddr=0x1000000\0"						\
diff --git a/include/configs/XPEDITE5200.h b/include/configs/xpedite520x.h
similarity index 95%
rename from include/configs/XPEDITE5200.h
rename to include/configs/xpedite520x.h
index d0e9492b4ed73a1b7884ac5e834737a7842e4ecf..b6b391f89f45cfcc1fde5feea2aab1db7756666d 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/xpedite520x.h
@@ -22,7 +22,7 @@
  */
 
 /*
- * xpedite5200 board configuration file
+ * xpedite520x board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -36,6 +36,7 @@
 #define CONFIG_MPC8548		1
 #define CONFIG_XPEDITE5200	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5200"
+#define CONFIG_SYS_FORM_PMC_XMC	1
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -92,6 +93,13 @@
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
 
 /*
  * Memory map
@@ -178,10 +186,9 @@
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
-#define CONFIG_SYS_INIT_RAM_END		0x4000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x4000
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
@@ -250,7 +257,7 @@
 #define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
 #define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
-#define CONFIG_SYS_PCA953X_FLASH_WP		0x20
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20
 #define CONFIG_SYS_PCA953X_MONARCH		0x40
 #define CONFIG_SYS_PCA953X_EREADY		0x80
 
@@ -264,14 +271,17 @@
 #define CONFIG_SYS_PCA953X_P14_IO6		0x40
 #define CONFIG_SYS_PCA953X_P14_IO7		0x80
 
+/* 12-bit ADC used to measure CPU diode */
+#define CONFIG_SYS_I2C_MAX1237_ADDR		0x34
+
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
-#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
 #define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
 
@@ -339,6 +349,7 @@
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_REGINFO
@@ -521,8 +532,8 @@
 	"misc_args=ip=on\0"						\
 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 	"bootfile=/home/user/file\0"					\
-	"osfile=/home/user/uImage-XPedite5200\0"			\
-	"fdtfile=/home/user/xpedite5200.dtb\0"				\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
 	"fdtaddr=c00000\0"						\
 	"osaddr=0x1000000\0"						\
diff --git a/include/configs/XPEDITE5370.h b/include/configs/xpedite537x.h
similarity index 94%
rename from include/configs/XPEDITE5370.h
rename to include/configs/xpedite537x.h
index 629dc0d89c6e2c77c94e891f7890b7316d4c9b35..e0a1fa406cd2b7804c1de78784756654ae25522d 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/xpedite537x.h
@@ -22,7 +22,7 @@
  */
 
 /*
- * xpedite5370 board configuration file
+ * xpedite537x board configuration file
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -36,6 +36,7 @@
 #define CONFIG_MPC8572		1
 #define CONFIG_XPEDITE5370	1
 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
+#define CONFIG_SYS_FORM_3U_VPX	1
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -110,6 +111,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_DS1621_ADDR,	\
+					 CONFIG_SYS_I2C_DS4510_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_LM90_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
+					 CONFIG_SYS_I2C_PEX8518_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST		{0x50}
 
 /*
  * Memory map
@@ -209,10 +224,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
-#define CONFIG_SYS_INIT_RAM_END		0x00004000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
@@ -265,6 +279,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_DS1621_ADDR	0x48
 #define CONFIG_DTT_DS1621
 #define CONFIG_DTT_SENSORS		{ 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4c
 
 /* I2C EEPROM - AT24C128B */
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
@@ -334,18 +349,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* PCIE1 - VPX P1 */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
 /* PCIE2 - PEX8518 */
-#define CONFIG_SYS_PCIE2_MEM_BASE	0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
 
@@ -396,6 +411,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SNTP
@@ -578,8 +594,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 	"misc_args=ip=on\0"						\
 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 	"bootfile=/home/user/file\0"					\
-	"osfile=/home/user/uImage-XPedite5370\0"			\
-	"fdtfile=/home/user/xpedite5370.dtb\0"				\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
 	"ubootfile=/home/user/u-boot.bin\0"				\
 	"fdtaddr=c00000\0"						\
 	"osaddr=0x1000000\0"						\
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
new file mode 100644
index 0000000000000000000000000000000000000000..42d1f6980eb850636f829eb90a41929831948638
--- /dev/null
+++ b/include/configs/xpedite550x.h
@@ -0,0 +1,606 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite550x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_P2020		1
+#define CONFIG_XPEDITE550X	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5500"
+#define CONFIG_SYS_FORM_PMC_XMC	1
+#define CONFIG_PRPMC_PCI_ALIAS	"pci0"	/* Processor PMC interface on pci0 */
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+#endif
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (PEX8112 or XMC) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1			0x54
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_LM75_ADDR,	\
+					 CONFIG_SYS_I2C_LM90_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000 0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xee00_0000 0xee00_ffff	Boot page translation	4K non-cacheable
+ * 0xef00_0000 0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000 0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000 0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
+					 CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST	/* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_XACS		| \
+				 OR_GPCM_ACS_DIV2	| \
+				 OR_GPCM_SCY_8		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR		| \
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
+				 OR_FCM_PGS	| \
+				 OR_FCM_CSCT	| \
+				 OR_FCM_CST	| \
+				 OR_FCM_CHT	| \
+				 OR_FCM_SCY_1	| \
+				 OR_FCM_TRLX	| \
+				 OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+#define CONFIG_FDT_FIXUP_PCI_IRQ	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C				/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C DS7505 temperature sensor */
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS		{ 0 }
+#define CONFIG_SYS_I2C_LM75_ADDR	0x48
+
+/* I2C ADT7461 temperature sensor */
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4C
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * GPIO pin definitions, PU = pulled high, PD = pulled low
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Write protection (0: disabled, 1: enabled) */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_XMC_GA0		0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA1		0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA2		0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_WAKE		0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_BIST		0x20 /* Enable XMC BIST */
+#define CONFIG_SYS_PCA953X_PMC_EREADY		0x40 /* PU; PMC PCI eready */
+#define CONFIG_SYS_PCA953X_PMC_MONARCH		0x80 /* PMC monarch mode enable */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_MC_GPIO0		0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO1		0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO2		0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO3		0x08 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO4		0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO5		0x20 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO6		0x40 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO7		0x80 /* PU; */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1 - PEX8112 or XMC, depending on build option */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_ETHPRIME		"eTSEC2"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+/*
+ * USB
+ */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff     Sec FDT (256KB)
+ * f6f00000 - f7efffff     Sec OS image (16MB)
+ * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	MK_STR(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR	MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	MK_STR(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR	MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	MK_STR(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
deleted file mode 100644
index 9606b5316bff1b4dbbd8a47c8e735f521c12ccdb..0000000000000000000000000000000000000000
--- a/include/configs/xsengine.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_PXA250			1		/* This is an PXA250 CPU    */
-#define CONFIG_XSENGINE			1
-#define CONFIG_MMC			1
-#define CONFIG_DOS_PARTITION		1
-#define BOARD_LATE_INIT			1
-#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_SYS_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */
-
-#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
-#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
-#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
-#define CONFIG_SYS_DRAM_BASE			0xa0000000
-#define CONFIG_SYS_DRAM_SIZE			0x04000000
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
-#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
-#define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
-#define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=xsengine-0"
-#define MTDPARTS_DEFAULT	"mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
-*/
-
-/* Environment settings */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH             1
-#define CONFIG_ENV_ADDR                    (PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector (after monitor)*/
-#define CONFIG_ENV_SECT_SIZE               PHYS_FLASH_SECT_SIZE		/* Size of the Environment Sector */
-#define CONFIG_ENV_SIZE                    0x4000				/* 16kB Total Size of Environment Sector */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT		(75*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT		(50*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
-
-/* Hardware drivers */
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE		0x04000300
-#define CONFIG_SMC_USE_32_BIT		1
-
-/* select serial console configuration */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART			1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_BAUDRATE			115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_JFFS2
-
-
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ETHADDR			FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK			255.255.255.0
-#define CONFIG_IPADDR			192.168.1.50
-#define CONFIG_SERVERIP			192.168.1.2
-#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
-#define CONFIG_CMDLINE_TAG
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_HUSH_PARSER			1
-#define CONFIG_SYS_PROMPT_HUSH_PS2		"> "
-#define CONFIG_SYS_LONGHELP								/* undef to save memory	*/
-#define CONFIG_SYS_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE			256					/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS			16					/* max number of command args */
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE				/* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START		0xA0400000				/* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
-#define CONFIG_SYS_LOAD_ADDR			0xA0000000				/* load kernel to this address   */
-
-#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE			0xF0000000
-#endif
-
-/* Stack sizes - The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef  CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
-
-/* GP set register */
-#define CONFIG_SYS_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
-#define CONFIG_SYS_GPSR1_VAL			0x00020000	/* nPWE */
-#define CONFIG_SYS_GPSR2_VAL			0x0000C000	/* CS2, CS3 */
-
-/* GP clear register */
-#define CONFIG_SYS_GPCR0_VAL			0x00000000
-#define CONFIG_SYS_GPCR1_VAL			0x00000000
-#define CONFIG_SYS_GPCR2_VAL			0x00000000
-
-/* GP direction register */
-#define CONFIG_SYS_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
-#define CONFIG_SYS_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
-#define CONFIG_SYS_GPDR2_VAL			0x0000C000	/* CS2, CS3 */
-
-/* GP rising edge detect register */
-#define CONFIG_SYS_GRER0_VAL			0x00000000
-#define CONFIG_SYS_GRER1_VAL			0x00000000
-#define CONFIG_SYS_GRER2_VAL			0x00000000
-
-/* GP falling edge detect register */
-#define CONFIG_SYS_GFER0_VAL			0x00000000
-#define CONFIG_SYS_GFER1_VAL			0x00000000
-#define CONFIG_SYS_GFER2_VAL			0x00000000
-
-/* GP alternate function register */
-#define CONFIG_SYS_GAFR0_L_VAL			0x80000000	/* CS1 */
-#define CONFIG_SYS_GAFR0_U_VAL			0x00000010	/* RDY */
-#define CONFIG_SYS_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
-#define CONFIG_SYS_GAFR1_U_VAL			0x00000008	/* nPWE */
-#define CONFIG_SYS_GAFR2_L_VAL			0xA0000000	/* CS2, CS3 */
-#define CONFIG_SYS_GAFR2_U_VAL			0x00000000
-
-#define CONFIG_SYS_PSSR_VAL			0x00000020	/* Power manager sleep status */
-#define CONFIG_SYS_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
-#define CONFIG_SYS_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
-#define CONFIG_SYS_ICMR_VAL			0x00000000	/* No interrupts enabled        */
-
-/* Memory settings */
-#define CONFIG_SYS_MSC0_VAL			0x25F425F0
-
-/* MDCNFG: SDRAM Configuration Register */
-#define CONFIG_SYS_MDCNFG_VAL			0x000009C9
-
-/* MDREFR: SDRAM Refresh Control Register */
-#define CONFIG_SYS_MDREFR_VAL			0x00018018
-
-/* MDMRS: Mode Register Set Configuration Register */
-#define CONFIG_SYS_MDMRS_VAL			0x00220022
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 0d450f50d4a1cc1244f97f9deda5aa0868a20fa3..0cbef6f85f77eb47e8827213076e30ca2ebbb5e5 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -77,9 +77,8 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CONFIG_SYS_INIT_RAM_END	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256			/* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 8d5d45fbc85e445e886925115aadff0ecab2b8dc..fb684b5e106f039865475937ce1dfd444509af20 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -97,10 +97,9 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index 5ddec84c74cd8e7f958199abe09ea58aba2b4592..f9a6b9313f66eb72247de6b1bd282695b8c8d36f 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -253,10 +253,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for POST and BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
 
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index ce65d1f1c6e2b30d3acd69c5b477bd1f9eca81d0..615d5c1f75cf9076c87fb1e2ee9c83e0785d383e 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -27,9 +27,9 @@
  */
 #define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_ZIPITZ2		1	/* Zipit Z2 board */
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef	BOARD_LATE_INIT
-#undef	CONFIG_SKIP_RELOCATE_UBOOT
 #undef	CONFIG_USE_IRQ
 #undef	CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -42,7 +42,6 @@
 #define CONFIG_ENV_SIZE			0x20000
 
 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define	CONFIG_SYS_GBL_DATA_SIZE	512
 #define	CONFIG_ARCH_CPU_INIT
 
 #define	CONFIG_BOOTCOMMAND						\
@@ -177,7 +176,7 @@ unsigned char zipitz2_spi_read(void);
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048)
 
 /*
  * NOR FLASH
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index c33ca2de918e8d20670bd0711aeec9c76c572d4c..1e03b0180d96c4417d5e0693ff525ae0830277f6 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -45,7 +45,6 @@
 #undef CONFIG_MMC
 #define BOARD_LATE_INIT		1
 
-#undef CONFIG_SKIP_RELOCATE_UBOOT
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
 /* we will never enable dcache, because we have to setup MMU first */
@@ -55,7 +54,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -191,7 +189,7 @@
 #undef CONFIG_SYS_SKIP_DRAM_SCRUB
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * NAND Flash
diff --git a/include/lattice.h b/include/lattice.h
index 75729b605ab6a90dc49fc61930fe33ada2ea4db9..e965663579e6919435327915bd0af23e27d9ffe3 100755
--- a/include/lattice.h
+++ b/include/lattice.h
@@ -317,4 +317,3 @@ void writePort(unsigned char pins, unsigned char value);
 unsigned char readPort(void);
 void sclock(void);
 #endif
-
diff --git a/include/led-display.h b/include/led-display.h
index 41c37443452bc2ffdad092c06870b51a875e3850..eaa0f406406d5cbe0e8d6d004320432c866b0424 100644
--- a/include/led-display.h
+++ b/include/led-display.h
@@ -29,7 +29,6 @@
 /* Display Commands */
 #define DISPLAY_CLEAR	0x1 /* Clear the display */
 #define DISPLAY_HOME	0x2 /* Set cursor at home position */
-#define DISPLAY_MARK	0x4 /* Enable the decimal point led, if implemented */
 
 void display_set(int cmd);
 int display_putc(char c);
diff --git a/include/linux/fb.h b/include/linux/fb.h
new file mode 100644
index 0000000000000000000000000000000000000000..3858f8f80f6b6cc17ea62976a78d11578025bcf8
--- /dev/null
+++ b/include/linux/fb.h
@@ -0,0 +1,616 @@
+#ifndef _LINUX_FB_H
+#define _LINUX_FB_H
+
+#include <linux/types.h>
+
+/* Definitions of frame buffers						*/
+
+#define FB_MAX			32	/* sufficient for now */
+
+#define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
+
+#define FB_VISUAL_MONO01		0	/* Monochr. 1=Black 0=White */
+#define FB_VISUAL_MONO10		1	/* Monochr. 1=White 0=Black */
+#define FB_VISUAL_TRUECOLOR		2	/* True color	*/
+#define FB_VISUAL_PSEUDOCOLOR		3	/* Pseudo color (like atari) */
+#define FB_VISUAL_DIRECTCOLOR		4	/* Direct color */
+#define FB_VISUAL_STATIC_PSEUDOCOLOR	5	/* Pseudo color readonly */
+
+#define FB_ACCEL_NONE		0	/* no hardware accelerator	*/
+
+struct fb_fix_screeninfo {
+	char id[16];			/* identification string eg "TT Builtin" */
+	unsigned long smem_start;	/* Start of frame buffer mem */
+					/* (physical address) */
+	__u32 smem_len;			/* Length of frame buffer mem */
+	__u32 type;			/* see FB_TYPE_*		*/
+	__u32 type_aux;			/* Interleave for interleaved Planes */
+	__u32 visual;			/* see FB_VISUAL_*		*/
+	__u16 xpanstep;			/* zero if no hardware panning	*/
+	__u16 ypanstep;			/* zero if no hardware panning	*/
+	__u16 ywrapstep;		/* zero if no hardware ywrap	*/
+	__u32 line_length;		/* length of a line in bytes	*/
+	unsigned long mmio_start;	/* Start of Memory Mapped I/O	*/
+					/* (physical address) */
+	__u32 mmio_len;			/* Length of Memory Mapped I/O	*/
+	__u32 accel;			/* Indicate to driver which	*/
+					/*  specific chip/card we have	*/
+	__u16 reserved[3];		/* Reserved for future compatibility */
+};
+
+/*
+ * Interpretation of offset for color fields: All offsets are from the right,
+ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
+ * can use the offset as right argument to <<). A pixel afterwards is a bit
+ * stream and is written to video memory as that unmodified.
+ *
+ * For pseudocolor: offset and length should be the same for all color
+ * components. Offset specifies the position of the least significant bit
+ * of the pallette index in a pixel value. Length indicates the number
+ * of available palette entries (i.e. # of entries = 1 << length).
+ */
+struct fb_bitfield {
+	__u32 offset;			/* beginning of bitfield	*/
+	__u32 length;			/* length of bitfield		*/
+	__u32 msb_right;
+
+};
+
+#define FB_NONSTD_HAM		1	/* Hold-And-Modify (HAM)	*/
+#define FB_NONSTD_REV_PIX_IN_B	2	/* order of pixels in each byte is reversed */
+
+#define FB_ACTIVATE_NOW		0	/* set values immediately (or vbl)*/
+#define FB_ACTIVATE_NXTOPEN	1	/* activate on next open	*/
+#define FB_ACTIVATE_TEST	2	/* don't set, round up impossible */
+#define FB_ACTIVATE_MASK       15
+					/* values			*/
+#define FB_ACTIVATE_VBL	       16	/* activate values on next vbl	*/
+#define FB_CHANGE_CMAP_VBL     32	/* change colormap on vbl	*/
+#define FB_ACTIVATE_ALL	       64	/* change all VCs on this fb	*/
+#define FB_ACTIVATE_FORCE     128	/* force apply even when no change*/
+#define FB_ACTIVATE_INV_MODE  256	/* invalidate videomode */
+
+#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
+#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
+#define FB_SYNC_EXT		4	/* external sync		*/
+#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active	*/
+#define FB_SYNC_BROADCAST	16	/* broadcast video timings	*/
+					/* vtotal = 144d/288n/576i => PAL  */
+					/* vtotal = 121d/242n/484i => NTSC */
+#define FB_SYNC_ON_GREEN	32	/* sync on green */
+
+#define FB_VMODE_NONINTERLACED	0	/* non interlaced */
+#define FB_VMODE_INTERLACED	1	/* interlaced	*/
+#define FB_VMODE_DOUBLE		2	/* double scan */
+#define FB_VMODE_ODD_FLD_FIRST	4	/* interlaced: top line first */
+#define FB_VMODE_MASK		255
+
+#define FB_VMODE_YWRAP		256	/* ywrap instead of panning	*/
+#define FB_VMODE_SMOOTH_XPAN	512	/* smooth xpan possible (internally used) */
+#define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset	*/
+
+/*
+ * Display rotation support
+ */
+#define FB_ROTATE_UR	  0
+#define FB_ROTATE_CW	  1
+#define FB_ROTATE_UD	  2
+#define FB_ROTATE_CCW	  3
+
+#define PICOS2KHZ(a) (1000000000UL/(a))
+#define KHZ2PICOS(a) (1000000000UL/(a))
+
+struct fb_var_screeninfo {
+	__u32 xres;			/* visible resolution		*/
+	__u32 yres;
+	__u32 xres_virtual;		/* virtual resolution		*/
+	__u32 yres_virtual;
+	__u32 xoffset;			/* offset from virtual to visible */
+	__u32 yoffset;			/* resolution			*/
+
+	__u32 bits_per_pixel;		/* guess what			*/
+	__u32 grayscale;		/* != 0 Graylevels instead of colors */
+
+	struct fb_bitfield red;		/* bitfield in fb mem if true color, */
+	struct fb_bitfield green;	/* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;	/* transparency			*/
+
+	__u32 nonstd;			/* != 0 Non standard pixel format */
+
+	__u32 activate;			/* see FB_ACTIVATE_*		*/
+
+	__u32 height;			/* height of picture in mm    */
+	__u32 width;			/* width of picture in mm     */
+
+	__u32 accel_flags;		/* (OBSOLETE) see fb_info.flags */
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	__u32 pixclock;			/* pixel clock in ps (pico seconds) */
+	__u32 left_margin;		/* time from sync to picture	*/
+	__u32 right_margin;		/* time from picture to sync	*/
+	__u32 upper_margin;		/* time from sync to picture	*/
+	__u32 lower_margin;
+	__u32 hsync_len;		/* length of horizontal sync	*/
+	__u32 vsync_len;		/* length of vertical sync	*/
+	__u32 sync;			/* see FB_SYNC_*		*/
+	__u32 vmode;			/* see FB_VMODE_*		*/
+	__u32 rotate;			/* angle we rotate counter clockwise */
+	__u32 reserved[5];		/* Reserved for future compatibility */
+};
+
+struct fb_cmap {
+	__u32 start;			/* First entry	*/
+	__u32 len;			/* Number of entries */
+	__u16 *red;			/* Red values	*/
+	__u16 *green;
+	__u16 *blue;
+	__u16 *transp;			/* transparency, can be NULL */
+};
+
+struct fb_con2fbmap {
+	__u32 console;
+	__u32 framebuffer;
+};
+
+/* VESA Blanking Levels */
+#define VESA_NO_BLANKING	0
+#define VESA_VSYNC_SUSPEND	1
+#define VESA_HSYNC_SUSPEND	2
+#define VESA_POWERDOWN		3
+
+
+enum {
+	/* screen: unblanked, hsync: on,  vsync: on */
+	FB_BLANK_UNBLANK       = VESA_NO_BLANKING,
+
+	/* screen: blanked,   hsync: on,  vsync: on */
+	FB_BLANK_NORMAL        = VESA_NO_BLANKING + 1,
+
+	/* screen: blanked,   hsync: on,  vsync: off */
+	FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
+
+	/* screen: blanked,   hsync: off, vsync: on */
+	FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
+
+	/* screen: blanked,   hsync: off, vsync: off */
+	FB_BLANK_POWERDOWN     = VESA_POWERDOWN + 1
+};
+
+#define FB_VBLANK_VBLANKING	0x001	/* currently in a vertical blank */
+#define FB_VBLANK_HBLANKING	0x002	/* currently in a horizontal blank */
+#define FB_VBLANK_HAVE_VBLANK	0x004	/* vertical blanks can be detected */
+#define FB_VBLANK_HAVE_HBLANK	0x008	/* horizontal blanks can be detected */
+#define FB_VBLANK_HAVE_COUNT	0x010	/* global retrace counter is available */
+#define FB_VBLANK_HAVE_VCOUNT	0x020	/* the vcount field is valid */
+#define FB_VBLANK_HAVE_HCOUNT	0x040	/* the hcount field is valid */
+#define FB_VBLANK_VSYNCING	0x080	/* currently in a vsync */
+#define FB_VBLANK_HAVE_VSYNC	0x100	/* verical syncs can be detected */
+
+struct fb_vblank {
+	__u32 flags;			/* FB_VBLANK flags */
+	__u32 count;			/* counter of retraces since boot */
+	__u32 vcount;			/* current scanline position */
+	__u32 hcount;			/* current scandot position */
+	__u32 reserved[4];		/* reserved for future compatibility */
+};
+
+/* Internal HW accel */
+#define ROP_COPY 0
+#define ROP_XOR  1
+
+struct fb_copyarea {
+	__u32 dx;
+	__u32 dy;
+	__u32 width;
+	__u32 height;
+	__u32 sx;
+	__u32 sy;
+};
+
+struct fb_fillrect {
+	__u32 dx;	/* screen-relative */
+	__u32 dy;
+	__u32 width;
+	__u32 height;
+	__u32 color;
+	__u32 rop;
+};
+
+struct fb_image {
+	__u32 dx;		/* Where to place image */
+	__u32 dy;
+	__u32 width;		/* Size of image */
+	__u32 height;
+	__u32 fg_color;		/* Only used when a mono bitmap */
+	__u32 bg_color;
+	__u8  depth;		/* Depth of the image */
+	const char *data;	/* Pointer to image data */
+	struct fb_cmap cmap;	/* color map info */
+};
+
+/*
+ * hardware cursor control
+ */
+
+#define FB_CUR_SETIMAGE 0x01
+#define FB_CUR_SETPOS	0x02
+#define FB_CUR_SETHOT	0x04
+#define FB_CUR_SETCMAP	0x08
+#define FB_CUR_SETSHAPE 0x10
+#define FB_CUR_SETSIZE	0x20
+#define FB_CUR_SETALL	0xFF
+
+struct fbcurpos {
+	__u16 x, y;
+};
+
+struct fb_cursor {
+	__u16 set;		/* what to set */
+	__u16 enable;		/* cursor on/off */
+	__u16 rop;		/* bitop operation */
+	const char *mask;	/* cursor mask bits */
+	struct fbcurpos hot;	/* cursor hot spot */
+	struct fb_image	image;	/* Cursor image */
+};
+
+#ifdef CONFIG_FB_BACKLIGHT
+/* Settings for the generic backlight code */
+#define FB_BACKLIGHT_LEVELS	128
+#define FB_BACKLIGHT_MAX	0xFF
+#endif
+
+#ifdef __KERNEL__
+
+struct vm_area_struct;
+struct fb_info;
+struct device;
+struct file;
+
+/* Definitions below are used in the parsed monitor specs */
+#define FB_DPMS_ACTIVE_OFF	1
+#define FB_DPMS_SUSPEND		2
+#define FB_DPMS_STANDBY		4
+
+#define FB_DISP_DDI		1
+#define FB_DISP_ANA_700_300	2
+#define FB_DISP_ANA_714_286	4
+#define FB_DISP_ANA_1000_400	8
+#define FB_DISP_ANA_700_000	16
+
+#define FB_DISP_MONO		32
+#define FB_DISP_RGB		64
+#define FB_DISP_MULTI		128
+#define FB_DISP_UNKNOWN		256
+
+#define FB_SIGNAL_NONE		0
+#define FB_SIGNAL_BLANK_BLANK	1
+#define FB_SIGNAL_SEPARATE	2
+#define FB_SIGNAL_COMPOSITE	4
+#define FB_SIGNAL_SYNC_ON_GREEN	8
+#define FB_SIGNAL_SERRATION_ON	16
+
+#define FB_MISC_PRIM_COLOR	1
+#define FB_MISC_1ST_DETAIL	2	/* First Detailed Timing is preferred */
+struct fb_chroma {
+	__u32 redx;	/* in fraction of 1024 */
+	__u32 greenx;
+	__u32 bluex;
+	__u32 whitex;
+	__u32 redy;
+	__u32 greeny;
+	__u32 bluey;
+	__u32 whitey;
+};
+
+struct fb_monspecs {
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;	/* mode database */
+	__u8  manufacturer[4];		/* Manufacturer */
+	__u8  monitor[14];		/* Monitor String */
+	__u8  serial_no[14];		/* Serial Number */
+	__u8  ascii[14];		/* ? */
+	__u32 modedb_len;		/* mode database length */
+	__u32 model;			/* Monitor Model */
+	__u32 serial;			/* Serial Number - Integer */
+	__u32 year;			/* Year manufactured */
+	__u32 week;			/* Week Manufactured */
+	__u32 hfmin;			/* hfreq lower limit (Hz) */
+	__u32 hfmax;			/* hfreq upper limit (Hz) */
+	__u32 dclkmin;			/* pixelclock lower limit (Hz) */
+	__u32 dclkmax;			/* pixelclock upper limit (Hz) */
+	__u16 input;			/* display type - see FB_DISP_* */
+	__u16 dpms;			/* DPMS support - see FB_DPMS_ */
+	__u16 signal;			/* Signal Type - see FB_SIGNAL_* */
+	__u16 vfmin;			/* vfreq lower limit (Hz) */
+	__u16 vfmax;			/* vfreq upper limit (Hz) */
+	__u16 gamma;			/* Gamma - in fractions of 100 */
+	__u16 gtf	: 1;		/* supports GTF */
+	__u16 misc;			/* Misc flags - see FB_MISC_* */
+	__u8  version;			/* EDID version... */
+	__u8  revision;			/* ...and revision */
+	__u8  max_x;			/* Maximum horizontal size (cm) */
+	__u8  max_y;			/* Maximum vertical size (cm) */
+};
+
+struct fb_cmap_user {
+	__u32 start;			/* First entry	*/
+	__u32 len;			/* Number of entries */
+	__u16 *red;		/* Red values	*/
+	__u16 *green;
+	__u16 *blue;
+	__u16 *transp;		/* transparency, can be NULL */
+};
+
+struct fb_image_user {
+	__u32 dx;			/* Where to place image */
+	__u32 dy;
+	__u32 width;			/* Size of image */
+	__u32 height;
+	__u32 fg_color;			/* Only used when a mono bitmap */
+	__u32 bg_color;
+	__u8  depth;			/* Depth of the image */
+	const char *data;	/* Pointer to image data */
+	struct fb_cmap_user cmap;	/* color map info */
+};
+
+struct fb_cursor_user {
+	__u16 set;			/* what to set */
+	__u16 enable;			/* cursor on/off */
+	__u16 rop;			/* bitop operation */
+	const char *mask;	/* cursor mask bits */
+	struct fbcurpos hot;		/* cursor hot spot */
+	struct fb_image_user image;	/* Cursor image */
+};
+
+/*
+ * Register/unregister for framebuffer events
+ */
+
+/*	The resolution of the passed in fb_info about to change */
+#define FB_EVENT_MODE_CHANGE		0x01
+/*	The display on this fb_info is beeing suspended, no access to the
+ *	framebuffer is allowed any more after that call returns
+ */
+#define FB_EVENT_SUSPEND		0x02
+/*	The display on this fb_info was resumed, you can restore the display
+ *	if you own it
+ */
+#define FB_EVENT_RESUME			0x03
+/*	An entry from the modelist was removed */
+#define FB_EVENT_MODE_DELETE		0x04
+/*	A driver registered itself */
+#define FB_EVENT_FB_REGISTERED		0x05
+/*	A driver unregistered itself */
+#define FB_EVENT_FB_UNREGISTERED	0x06
+/*	CONSOLE-SPECIFIC: get console to framebuffer mapping */
+#define FB_EVENT_GET_CONSOLE_MAP	0x07
+/*	CONSOLE-SPECIFIC: set console to framebuffer mapping */
+#define FB_EVENT_SET_CONSOLE_MAP	0x08
+/*	A hardware display blank change occured */
+#define FB_EVENT_BLANK			0x09
+/*	Private modelist is to be replaced */
+#define FB_EVENT_NEW_MODELIST		0x0A
+/*	The resolution of the passed in fb_info about to change and
+	all vc's should be changed	   */
+#define FB_EVENT_MODE_CHANGE_ALL	0x0B
+/*	A software display blank change occured */
+#define FB_EVENT_CONBLANK		0x0C
+/*	Get drawing requirements	*/
+#define FB_EVENT_GET_REQ		0x0D
+/*	Unbind from the console if possible */
+#define FB_EVENT_FB_UNBIND		0x0E
+
+struct fb_event {
+	struct fb_info *info;
+	void *data;
+};
+
+struct fb_blit_caps {
+	u32 x;
+	u32 y;
+	u32 len;
+	u32 flags;
+};
+
+/*
+ * Pixmap structure definition
+ *
+ * The purpose of this structure is to translate data
+ * from the hardware independent format of fbdev to what
+ * format the hardware needs.
+ */
+
+#define FB_PIXMAP_DEFAULT 1	/* used internally by fbcon */
+#define FB_PIXMAP_SYSTEM  2	/* memory is in system RAM  */
+#define FB_PIXMAP_IO	  4	/* memory is iomapped	    */
+#define FB_PIXMAP_SYNC	  256	/* set if GPU can DMA	    */
+
+struct fb_pixmap {
+	u8  *addr;		/* pointer to memory			*/
+	u32 size;		/* size of buffer in bytes		*/
+	u32 offset;		/* current offset to buffer		*/
+	u32 buf_align;		/* byte alignment of each bitmap	*/
+	u32 scan_align;		/* alignment per scanline		*/
+	u32 access_align;	/* alignment per read/write (bits)	*/
+	u32 flags;		/* see FB_PIXMAP_*			*/
+	u32 blit_x;		/* supported bit block dimensions (1-32)*/
+	u32 blit_y;		/* Format: blit_x = 1 << (width - 1)	*/
+				/*	   blit_y = 1 << (height - 1)	*/
+				/* if 0, will be set to 0xffffffff (all)*/
+	/* access methods */
+	void (*writeio)(struct fb_info *info, void *dst, void *src, unsigned int size);
+	void (*readio) (struct fb_info *info, void *dst, void *src, unsigned int size);
+};
+
+#ifdef CONFIG_FB_DEFERRED_IO
+struct fb_deferred_io {
+	/* delay between mkwrite and deferred handler */
+	unsigned long delay;
+	struct mutex lock; /* mutex that protects the page list */
+	struct list_head pagelist; /* list of touched pages */
+	/* callback */
+	void (*deferred_io)(struct fb_info *info, struct list_head *pagelist);
+};
+#endif
+
+/* FBINFO_* = fb_info.flags bit flags */
+#define FBINFO_MODULE		0x0001	/* Low-level driver is a module */
+#define FBINFO_HWACCEL_DISABLED	0x0002
+	/* When FBINFO_HWACCEL_DISABLED is set:
+	 *  Hardware acceleration is turned off.  Software implementations
+	 *  of required functions (copyarea(), fillrect(), and imageblit())
+	 *  takes over; acceleration engine should be in a quiescent state */
+
+/* hints */
+#define FBINFO_PARTIAL_PAN_OK	0x0040 /* otw use pan only for double-buffering */
+#define FBINFO_READS_FAST	0x0080 /* soft-copy faster than rendering */
+
+/*
+ * A driver may set this flag to indicate that it does want a set_par to be
+ * called every time when fbcon_switch is executed. The advantage is that with
+ * this flag set you can really be sure that set_par is always called before
+ * any of the functions dependant on the correct hardware state or altering
+ * that state, even if you are using some broken X releases. The disadvantage
+ * is that it introduces unwanted delays to every console switch if set_par
+ * is slow. It is a good idea to try this flag in the drivers initialization
+ * code whenever there is a bug report related to switching between X and the
+ * framebuffer console.
+ */
+#define FBINFO_MISC_ALWAYS_SETPAR   0x40000
+
+/*
+ * Host and GPU endianness differ.
+ */
+#define FBINFO_FOREIGN_ENDIAN	0x100000
+/*
+ * Big endian math. This is the same flags as above, but with different
+ * meaning, it is set by the fb subsystem depending FOREIGN_ENDIAN flag
+ * and host endianness. Drivers should not use this flag.
+ */
+#define FBINFO_BE_MATH	0x100000
+
+struct fb_info {
+	int node;
+	int flags;
+	struct fb_var_screeninfo var;	/* Current var */
+	struct fb_fix_screeninfo fix;	/* Current fix */
+	struct fb_monspecs monspecs;	/* Current Monitor specs */
+	struct fb_pixmap pixmap;	/* Image hardware mapper */
+	struct fb_pixmap sprite;	/* Cursor hardware mapper */
+	struct fb_cmap cmap;		/* Current cmap */
+	struct list_head modelist;	/* mode list */
+	struct fb_videomode *mode;	/* current mode */
+
+	char *screen_base;	/* Virtual address */
+	unsigned long screen_size;	/* Amount of ioremapped VRAM or 0 */
+	void *pseudo_palette;		/* Fake palette of 16 colors */
+#define FBINFO_STATE_RUNNING	0
+#define FBINFO_STATE_SUSPENDED	1
+	u32 state;			/* Hardware state i.e suspend */
+	void *fbcon_par;		/* fbcon use-only private area */
+	/* From here on everything is device dependent */
+	void *par;
+};
+
+#define FBINFO_DEFAULT	0
+
+#define FBINFO_FLAG_MODULE	FBINFO_MODULE
+#define FBINFO_FLAG_DEFAULT	FBINFO_DEFAULT
+
+/* This will go away */
+#if defined(__sparc__)
+
+/* We map all of our framebuffers such that big-endian accesses
+ * are what we want, so the following is sufficient.
+ */
+
+/* This will go away */
+#define fb_readb sbus_readb
+#define fb_readw sbus_readw
+#define fb_readl sbus_readl
+#define fb_readq sbus_readq
+#define fb_writeb sbus_writeb
+#define fb_writew sbus_writew
+#define fb_writel sbus_writel
+#define fb_writeq sbus_writeq
+#define fb_memset sbus_memset_io
+
+#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__avr32__) || defined(__bfin__)
+
+#define fb_readb __raw_readb
+#define fb_readw __raw_readw
+#define fb_readl __raw_readl
+#define fb_readq __raw_readq
+#define fb_writeb __raw_writeb
+#define fb_writew __raw_writew
+#define fb_writel __raw_writel
+#define fb_writeq __raw_writeq
+#define fb_memset memset_io
+
+#else
+
+#define fb_readb(addr) (*(volatile u8 *) (addr))
+#define fb_readw(addr) (*(volatile u16 *) (addr))
+#define fb_readl(addr) (*(volatile u32 *) (addr))
+#define fb_readq(addr) (*(volatile u64 *) (addr))
+#define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b))
+#define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b))
+#define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b))
+#define fb_writeq(b,addr) (*(volatile u64 *) (addr) = (b))
+#define fb_memset memset
+
+#endif
+
+#define FB_LEFT_POS(p, bpp)	     (fb_be_math(p) ? (32 - (bpp)) : 0)
+#define FB_SHIFT_HIGH(p, val, bits)  (fb_be_math(p) ? (val) >> (bits) : \
+						      (val) << (bits))
+#define FB_SHIFT_LOW(p, val, bits)   (fb_be_math(p) ? (val) << (bits) : \
+						      (val) >> (bits))
+/* drivers/video/fbmon.c */
+#define FB_MAXTIMINGS		0
+#define FB_VSYNCTIMINGS		1
+#define FB_HSYNCTIMINGS		2
+#define FB_DCLKTIMINGS		3
+#define FB_IGNOREMON		0x100
+
+#define FB_MODE_IS_UNKNOWN	0
+#define FB_MODE_IS_DETAILED	1
+#define FB_MODE_IS_STANDARD	2
+#define FB_MODE_IS_VESA		4
+#define FB_MODE_IS_CALCULATED	8
+#define FB_MODE_IS_FIRST	16
+#define FB_MODE_IS_FROM_VAR	32
+
+
+/* drivers/video/fbcmap.c */
+
+extern int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp);
+extern void fb_dealloc_cmap(struct fb_cmap *cmap);
+extern int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to);
+extern int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to);
+extern int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *fb_info);
+extern int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *fb_info);
+extern const struct fb_cmap *fb_default_cmap(int len);
+extern void fb_invert_cmaps(void);
+
+struct fb_videomode {
+	const char *name;	/* optional */
+	u32 refresh;		/* optional */
+	u32 xres;
+	u32 yres;
+	u32 pixclock;
+	u32 left_margin;
+	u32 right_margin;
+	u32 upper_margin;
+	u32 lower_margin;
+	u32 hsync_len;
+	u32 vsync_len;
+	u32 sync;
+	u32 vmode;
+	u32 flag;
+};
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_FB_H */
diff --git a/include/linux/kbuild.h b/include/linux/kbuild.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab7805a3b44330931a4be453f85cc86597590753
--- /dev/null
+++ b/include/linux/kbuild.h
@@ -0,0 +1,20 @@
+/*
+ * Copied from Linux:
+ * commit 37487a56523d402e25650da16c337acf4cecd13d
+ * Author: Christoph Lameter <clameter@sgi.com>
+ */
+#ifndef __LINUX_KBUILD_H
+#define __LINUX_KBUILD_H
+
+#define DEFINE(sym, val) \
+	asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+
+#define BLANK() asm volatile("\n->" : : )
+
+#define OFFSET(sym, str, mem) \
+	DEFINE(sym, offsetof(struct str, mem))
+
+#define COMMENT(x) \
+	asm volatile("\n->#" x)
+
+#endif
diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h
index 03541cbf219be321a185efed402fe775142baadb..2967284274935aae238a834ca510669a34d5e37c 100644
--- a/include/linux/usb/cdc.h
+++ b/include/linux/usb/cdc.h
@@ -9,8 +9,6 @@
  *                      Remy Bohmer <linux@bohmer.net>
  */
 
-
-
 #define USB_CDC_SUBCLASS_ACM			0x02
 #define USB_CDC_SUBCLASS_ETHERNET		0x06
 #define USB_CDC_SUBCLASS_WHCM			0x08
@@ -199,7 +197,6 @@ struct usb_cdc_line_coding {
 #define	USB_CDC_PACKET_TYPE_BROADCAST		(1 << 3)
 #define	USB_CDC_PACKET_TYPE_MULTICAST		(1 << 4) /* filtered */
 
-
 /*-------------------------------------------------------------------------*/
 
 /*
@@ -221,4 +218,3 @@ struct usb_cdc_notification {
 	__le16	wIndex;
 	__le16	wLength;
 } __attribute__ ((packed));
-
diff --git a/include/mc13892.h b/include/mc13892.h
index 791e3ec878455460ef44a36f8708b4bc4f4e396f..61c3e6e621c4a59a9ae1c79f1abd730c70b21aa8 100644
--- a/include/mc13892.h
+++ b/include/mc13892.h
@@ -29,24 +29,24 @@
 
 /* REG_CHARGE */
 
-#define VCHRG0		0
+#define VCHRG0		(1 << 0)
 #define VCHRG1		(1 << 1)
 #define VCHRG2		(1 << 2)
 #define ICHRG0		(1 << 3)
 #define ICHRG1		(1 << 4)
 #define ICHRG2		(1 << 5)
 #define ICHRG3		(1 << 6)
-#define ICHRGTR0	(1 << 7)
-#define ICHRGTR1	(1 << 8)
-#define ICHRGTR2	(1 << 9)
+#define TREN		(1 << 7)
+#define ACKLPB		(1 << 8)
+#define THCHKB		(1 << 9)
 #define FETOVRD		(1 << 10)
 #define FETCTRL		(1 << 11)
 #define RVRSMODE	(1 << 13)
-#define OVCTRL0		(1 << 15)
-#define OVCTRL1		(1 << 16)
-#define UCHEN		(1 << 17)
+#define PLIM0		(1 << 15)
+#define PLIM1		(1 << 16)
+#define PLIMDIS		(1 << 17)
 #define CHRGLEDEN	(1 << 18)
-#define CHRGRAWPDEN	(1 << 19)
+#define CHGTMRRST	(1 << 19)
 #define CHGRESTART	(1 << 20)
 #define CHGAUTOB	(1 << 21)
 #define CYCLB		(1 << 22)
diff --git a/include/post.h b/include/post.h
index daa9047118e7de85e4ebf329c6439189c4b340b0..957ce3b16161f351b0d132b6a617310de7dfe9f7 100644
--- a/include/post.h
+++ b/include/post.h
@@ -60,6 +60,10 @@
 #include <asm/immap_85xx.h>
 #define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr))
 
+#elif defined (CONFIG_MPC86xx)
+#include <asm/immap_86xx.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr))
+
 #elif defined (CONFIG_4xx)
 #define _POST_WORD_ADDR \
 	(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
@@ -133,7 +137,7 @@ void post_output_backlog ( void );
 int post_run (char *name, int flags);
 int post_info (char *name);
 int post_log (char *format, ...);
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 void post_reloc (void);
 #endif
 unsigned long post_time_ms (unsigned long base);
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 08691a0f2a123d3b833ba824fa7e36758defbd6b..67600ed522817f36ced4f29f2a577b2a140d754d 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -161,7 +161,7 @@
 #define MPC83XX_SCCR_USB_DRCM_01	0x00100000
 #define MPC83XX_SCCR_USB_DRCM_10	0x00200000
 
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
 #elif defined(CONFIG_MPC85xx)
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
new file mode 100644
index 0000000000000000000000000000000000000000..22095610f931d8ef3253d58f23f78f045be565b0
--- /dev/null
+++ b/lib/asm-offsets.c
@@ -0,0 +1,29 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(GENERATED_GBL_DATA_SIZE,
+		(sizeof(struct global_data)+15) & ~15);
+
+	return 0;
+}
diff --git a/lib/hashtable.c b/lib/hashtable.c
index 57802cfb6ded27e14490e601c1cc081d0829a368..7ac3dddda693897f2a08cfda4ea682e943ab3e39 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -56,7 +56,7 @@
 
 /*
  * [Aho,Sethi,Ullman] Compilers: Principles, Techniques and Tools, 1986
- * [Knuth]            The Art of Computer Programming, part 3 (6.4)
+ * [Knuth]	      The Art of Computer Programming, part 3 (6.4)
  */
 
 /*
@@ -252,7 +252,7 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval,
 
 	if (htab->table[idx].used) {
 		/*
-                 * Further action might be required according to the
+		 * Further action might be required according to the
 		 * action value.
 		 */
 		unsigned hval2;
@@ -283,8 +283,8 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval,
 
 		do {
 			/*
-                         * Because SIZE is prime this guarantees to
-                         * step through all available indices.
+			 * Because SIZE is prime this guarantees to
+			 * step through all available indices.
 			 */
 			if (idx <= hval2)
 				idx = htab->size + idx - hval2;
@@ -323,8 +323,8 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval,
 	/* An empty bucket has been found. */
 	if (action == ENTER) {
 		/*
-                 * If table is full and another entry should be
-                 * entered return with error.
+		 * If table is full and another entry should be
+		 * entered return with error.
 		 */
 		if (htab->filled == htab->size) {
 			__set_errno(ENOMEM);
diff --git a/lib/qsort.c b/lib/qsort.c
index bb47319f8ba5b1dc30f1b51d3405209b07249414..e771dcfcf2756504bc53916cd0366643ff70a81d 100644
--- a/lib/qsort.c
+++ b/lib/qsort.c
@@ -23,9 +23,9 @@
 #endif
 
 void qsort(void  *base,
-           size_t nel,
-           size_t width,
-           int (*comp)(const void *, const void *))
+	   size_t nel,
+	   size_t width,
+	   int (*comp)(const void *, const void *))
 {
 	size_t wgap, i, j, k;
 	char tmp;
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index ccd0af25548e7520c594b698dfebdcf46b1474b2..d6244183c83b279b5c555e9f88514885f7da5af5 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -221,7 +221,7 @@ static int nand_load(struct mtd_info *mtd, unsigned int offs,
 	return 0;
 }
 
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
+#if defined(CONFIG_ARM)
 void board_init_f (ulong bootflag)
 {
 	relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c
index 21ed3fcff4b26a5bcaa6ebcf6a16bbf68053611f..a3f0f6ba51add514801f9ed84f33fac484258f50 100644
--- a/nand_spl/nand_boot_fsl_nfc.c
+++ b/nand_spl/nand_boot_fsl_nfc.c
@@ -263,7 +263,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
 	return 0;
 }
 
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
+#if defined(CONFIG_ARM)
 void board_init_f (ulong bootflag)
 {
 	relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile
index a86bc00864c870c9490193f806f556c68d01be85..7300692b77288c66878a98afe019c5fb97d24e4e 100644
--- a/onenand_ipl/board/vpac270/Makefile
+++ b/onenand_ipl/board/vpac270/Makefile
@@ -8,7 +8,6 @@ AFLAGS	+= -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
 CFLAGS	+= -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
 OBJCFLAGS += --gap-fill=0x00
 
-SOBJS	:= lowlevel_init.o
 SOBJS	+= start.o
 COBJS	:= vpac270.o
 COBJS	+= onenand_read.o
@@ -62,10 +61,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
 $(obj)vpac270.c:
 	@rm -f $@
 	ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@
-
-$(obj)lowlevel_init.S:
-	@rm -f $@
-	ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@
 endif
 
 #########################################################################
diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c
index 3067548483980a2921b22e0ea966601050ca4b0b..501369b6a1c56fd4f5af97fb60e3181aa513ed4d 100644
--- a/post/board/lwmon5/fpga.c
+++ b/post/board/lwmon5/fpga.c
@@ -227,8 +227,6 @@ static int fpga_mem_test(void)
 	return ret;
 }
 
-
-
 /* Verify FPGA addresslines */
 static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
 {
diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c
index b152deaf6abf52c91d164b49b0349b1b7795b004..4a1b1a49d17bd481e401070ad44b78d69779638b 100644
--- a/post/drivers/i2c.c
+++ b/post/drivers/i2c.c
@@ -21,70 +21,89 @@
  * MA 02111-1307 USA
  */
 
-#include <common.h>
-
 /*
  * I2C test
  *
  * For verifying the I2C bus, a full I2C bus scanning is performed.
  *
- * #ifdef I2C_ADDR_LIST
- *   The test is considered as passed if all the devices and
- *   only the devices in the list are found.
- * #else [ ! I2C_ADDR_LIST ]
+ * #ifdef CONFIG_SYS_POST_I2C_ADDRS
+ *   The test is considered as passed if all the devices and only the devices
+ *   in the list are found.
+ *   #ifdef CONFIG_SYS_POST_I2C_IGNORES
+ *     Ignore devices listed in CONFIG_SYS_POST_I2C_IGNORES.  These devices
+ *     are optional or not vital to board functionality.
+ *   #endif
+ * #else [ ! CONFIG_SYS_POST_I2C_ADDRS ]
  *   The test is considered as passed if any I2C device is found.
  * #endif
  */
 
+#include <common.h>
 #include <post.h>
 #include <i2c.h>
 
 #if CONFIG_POST & CONFIG_SYS_POST_I2C
 
+static int i2c_ignore_device(unsigned int chip)
+{
+#ifdef CONFIG_SYS_POST_I2C_IGNORES
+	const unsigned char i2c_ignore_list[] = CONFIG_SYS_POST_I2C_IGNORES;
+	int i;
+
+	for (i = 0; i < sizeof(i2c_ignore_list); i++)
+		if (i2c_ignore_list[i] == chip)
+			return 1;
+#endif
+
+	return 0;
+}
+
 int i2c_post_test (int flags)
 {
 	unsigned int i;
-	unsigned int good = 0;
-#ifdef I2C_ADDR_LIST
-	unsigned int bad  = 0;
+#ifndef CONFIG_SYS_POST_I2C_ADDRS
+	/* Start at address 1, address 0 is the general call address */
+	for (i = 1; i < 128; i++)
+		if (i2c_ignore_device(i))
+			continue;
+		if (i2c_probe (i) == 0)
+			return 0;
+
+	/* No devices found */
+	return -1;
+#else
+	unsigned int ret  = 0;
 	int j;
-	unsigned char i2c_addr_list[] = I2C_ADDR_LIST;
-	unsigned char i2c_miss_list[] = I2C_ADDR_LIST;
-#endif
+	unsigned char i2c_addr_list[] = CONFIG_SYS_POST_I2C_ADDRS;
 
-	for (i = 0; i < 128; i++) {
-		if (i2c_probe (i) == 0) {
-#ifndef	I2C_ADDR_LIST
-			good++;
-#else	/* I2C_ADDR_LIST */
-			for (j=0; j<sizeof(i2c_addr_list); ++j) {
-				if (i == i2c_addr_list[j]) {
-					good++;
-					i2c_miss_list[j] = 0xFF;
-					break;
-				}
-			}
-			if (j == sizeof(i2c_addr_list)) {
-				bad++;
-				post_log ("I2C: addr %02X not expected\n",
-						i);
+	/* Start at address 1, address 0 is the general call address */
+	for (i = 1; i < 128; i++) {
+		if (i2c_ignore_device(i))
+			continue;
+		if (i2c_probe(i) != 0)
+			continue;
+
+		for (j = 0; j < sizeof(i2c_addr_list); ++j) {
+			if (i == i2c_addr_list[j]) {
+				i2c_addr_list[j] = 0xff;
+				break;
 			}
-#endif	/* I2C_ADDR_LIST */
 		}
-	}
 
-#ifndef	I2C_ADDR_LIST
-	return good > 0 ? 0 : -1;
-#else	/* I2C_ADDR_LIST */
-	if (good != sizeof(i2c_addr_list)) {
-		for (j=0; j<sizeof(i2c_miss_list); ++j) {
-			if (i2c_miss_list[j] != 0xFF) {
-				post_log ("I2C: addr %02X did not respond\n",
-						i2c_miss_list[j]);
-			}
+		if (j == sizeof(i2c_addr_list)) {
+			ret = -1;
+			post_log("I2C: addr %02x not expected\n", i);
 		}
 	}
-	return ((good == sizeof(i2c_addr_list)) && (bad == 0)) ? 0 : -1;
+
+	for (i = 0; i < sizeof(i2c_addr_list); ++i) {
+		if (i2c_addr_list[i] == 0xff)
+			continue;
+		post_log("I2C: addr %02x did not respond\n", i2c_addr_list[i]);
+		ret = -1;
+	}
+
+	return ret;
 #endif
 }
 
diff --git a/post/post.c b/post/post.c
index 8a9fd0d2ec10d9a4a8c15067587d3e3d562cae2f..1b7f2aa075e2ea0679857dd9be5e57eb4252c43a 100644
--- a/post/post.c
+++ b/post/post.c
@@ -422,7 +422,7 @@ int post_log (char *format, ...)
 	return 0;
 }
 
-#ifndef CONFIG_RELOC_FIXUP_WORKS
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
 void post_reloc (void)
 {
 	unsigned int i;
diff --git a/tools/scripts/make-asm-offsets b/tools/scripts/make-asm-offsets
new file mode 100755
index 0000000000000000000000000000000000000000..4c33756d66e6d637dffe817c6fc1b59099eea6c1
--- /dev/null
+++ b/tools/scripts/make-asm-offsets
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+# Adapted from Linux kernel's "Kbuild":
+# commit 1cdf25d704f7951d02a04064c97db547d6021872
+# Author: Christoph Lameter <clameter@sgi.com>
+
+mkdir -p $(dirname $2)
+
+# Default sed regexp - multiline due to syntax constraints
+SED_CMD="/^->/{s:->#\(.*\):/* \1 */:; \
+	s:^->\([^ ]*\) [\$#]*\([-0-9]*\) \(.*\):#define \1 (\2) /* \3 */:; \
+	s:^->\([^ ]*\) [\$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
+	s:->::; p;}"
+
+(set -e
+ echo "#ifndef __ASM_OFFSETS_H__"
+ echo "#define __ASM_OFFSETS_H__"
+ echo "/*"
+ echo " * DO NOT MODIFY."
+ echo " *"
+ echo " * This file was generated by $(basename $0)"
+ echo " *"
+ echo " */"
+ echo ""
+ sed -ne "${SED_CMD}" $1 
+ echo ""
+ echo "#endif" ) > $2