diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 65195f528a8d7c884f2531cef1760d14e5062e0c..0e75794d225887b3068b3313745d08f3245643e4 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -1389,8 +1389,8 @@ in32r:
 relocate_code:
 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
 	/*
-	 * We need to flush the initial global data (gd_t) before the dcache
-	 * will be invalidated.
+	 * We need to flush the initial global data (gd_t) and bd_info
+	 * before the dcache will be invalidated.
 	 */
 
 	/* Save registers */
@@ -1398,10 +1398,11 @@ relocate_code:
 	mr	r10, r4
 	mr	r11, r5
 
-	/* Flush initial global data range */
-	mr	r3, r4
-	addi	r4, r4, GENERATED_GBL_DATA_SIZE@l
-	bl	flush_dcache_range
+	/*
+	 * Flush complete dcache, this is faster than flushing the
+	 * ranges for global_data and bd_info instead.
+	 */
+	bl	flush_dcache
 
 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
 	/*
diff --git a/post/cpu/ppc4xx/denali_ecc.c b/post/cpu/ppc4xx/denali_ecc.c
index 50ae7fb8f0decd9e5c974495cde72c2a5d0d6245..6d146355956252c9aa3ef1a1fd79d8b4262f7f5f 100644
--- a/post/cpu/ppc4xx/denali_ecc.c
+++ b/post/cpu/ppc4xx/denali_ecc.c
@@ -174,6 +174,7 @@ static int test_ecc(uint32_t ecc_addr)
 	clear_and_enable_ecc();
 	out_be32(ecc_mem, ECC_PATTERN);
 	out_be32(ecc_mem + 1, ECC_PATTERN);
+	ppcDcbf((u32)ecc_mem);
 
 	/* Verify no ECC error reading back */
 	value = in_be32(ecc_mem);
@@ -193,6 +194,7 @@ static int test_ecc(uint32_t ecc_addr)
 
 	/* Test for correctable error by creating a one-bit error */
 	out_be32(ecc_mem, ECC_PATTERN_CORR);
+	ppcDcbf((u32)ecc_mem);
 	clear_and_enable_ecc();
 	value = in_be32(ecc_mem);
 	disable_ecc();
@@ -212,6 +214,7 @@ static int test_ecc(uint32_t ecc_addr)
 
 	/* Test for uncorrectable error by creating a two-bit error */
 	out_be32(ecc_mem, ECC_PATTERN_UNCORR);
+	ppcDcbf((u32)ecc_mem);
 	clear_and_enable_ecc();
 	value = in_be32(ecc_mem);
 	disable_ecc();
@@ -232,6 +235,7 @@ static int test_ecc(uint32_t ecc_addr)
 
 	/* Remove error from SDRAM and enable ECC. */
 	out_be32(ecc_mem, ECC_PATTERN);
+	ppcDcbf((u32)ecc_mem);
 	clear_and_enable_ecc();
 
 	return ret;