diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 850d1c370e78389e121f9a877f6562dfd869c102..e7386130098aa4343efcdbde2baa1f41f33061e4 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -91,8 +91,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
- puts("\n DDR RAM: ");
-
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
diff --git a/board/mpc8313erdb/sdram.c b/board/mpc8313erdb/sdram.c
index 4b6778837f2d9afd1e883479502bbe62eb458bcd..e6e84107eb28384775c268a6aaa764600b4d3c55 100644
--- a/board/mpc8313erdb/sdram.c
+++ b/board/mpc8313erdb/sdram.c
@@ -112,8 +112,6 @@ long int initdram(int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
msize = fixed_sdram();
@@ -127,7 +125,6 @@ long int initdram(int board_type)
resume_from_sleep();
#endif
- puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return msize;
}
diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c
index 207fcdf8be3853d287a38fefa6d1960e1563c22b..7a45ded76a51861281c03b25c222945309954121 100644
--- a/board/mpc832xemds/mpc832xemds.c
+++ b/board/mpc832xemds/mpc832xemds.c
@@ -114,8 +114,6 @@ long int initdram(int board_type)
msize = fixed_sdram();
- puts("\n DDR RAM: ");
-
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index 2ad25ec5060adf7cbb83a5c7f91de9aeb07e5818..39c09162760eb3dcbc95ed487ec0fbd6ab92a81a 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -70,8 +70,6 @@ long int initdram (int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
@@ -90,7 +88,7 @@ long int initdram (int board_type)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
- puts(" DDR RAM: ");
+
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@@ -191,9 +189,6 @@ void sdram_init(void)
volatile lbus83xx_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
- puts("\n SDRAM on Local Bus: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
@@ -255,7 +250,6 @@ void sdram_init(void)
#else
void sdram_init(void)
{
- puts(" SDRAM on Local Bus is NOT available!\n");
}
#endif
diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c
index 125e6c0864a52b7246bb7e85d71103c8b706d1de..c82f7847a225cd7e6cad3115789dd20c76e51d8b 100644
--- a/board/mpc8349itx/mpc8349itx.c
+++ b/board/mpc8349itx/mpc8349itx.c
@@ -76,7 +76,7 @@ int fixed_sdram(void)
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
- im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
+ im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
im->ddr.sdram_mode =
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
im->ddr.sdram_interval =
@@ -162,7 +162,6 @@ long int initdram(int board_type)
ddr_enable_ecc(msize * 1048576);
#endif
- puts(" DDR RAM: ");
/* return total bus RAM size(bytes) */
return msize * 1024 * 1024;
}
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
index d6d0f4e25f76f46ad46b0b4f6970639257752055..0751c6fafdb75f5b4e7404effc55ef65f72f235b 100644
--- a/board/mpc8360emds/mpc8360emds.c
+++ b/board/mpc8360emds/mpc8360emds.c
@@ -149,7 +149,7 @@ long int initdram(int board_type)
* Initialize SDRAM if it is on local bus.
*/
sdram_init();
- puts(" DDR RAM: ");
+
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@@ -234,8 +234,6 @@ void sdram_init(void)
volatile lbus83xx_t *lbc = &immap->lbus;
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
- puts("\n SDRAM on Local Bus: ");
- print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
@@ -291,7 +289,6 @@ void sdram_init(void)
#else
void sdram_init(void)
{
- puts("SDRAM on Local Bus is NOT available!\n");
}
#endif
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 4cd447e097fe66a8699236e7245ecf77e81ea7b7..86166ea4439b6bb6e060a10018f82fddfc8f3ffc 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -64,8 +64,6 @@ long int initdram (int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
- puts("Initializing\n");
-
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
@@ -84,7 +82,6 @@ long int initdram (int board_type)
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
- puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
@@ -130,7 +127,7 @@ int fixed_sdram(void)
#if defined(CONFIG_DDR_2T_TIMING)
| SDRAM_CFG_2T_EN
#endif
- | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+ | SDRAM_CFG_SDRAM_TYPE_DDR1;
#if defined (CONFIG_DDR_32BIT)
/* for 32-bit mode burst length is 8 */
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 9c35e22c8e10ec556400513c4d0aa5f143804fa4..7d0b0554840e1edadb03ed130692b9b814f06441 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -114,7 +114,7 @@ long int initdram (int board_type)
/* enable DDR controller */
im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR);
+ SDRAM_CFG_SDRAM_TYPE_DDR1);
SYNC;
/* size detection */
@@ -388,7 +388,7 @@ static void set_ddr_config(void) {
/* don't enable DDR controller yet */
im->ddr.sdram_cfg =
SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR;
+ SDRAM_CFG_SDRAM_TYPE_DDR1;
SYNC;
/* Set SDRAM mode */
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 54f0c83d454013cb7564f7acd87fe6ce518b9afe..040836c42e09df55d7f1a36eb0ae36b742db164c 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -34,6 +34,30 @@
#include <asm/mmu.h>
#include <spd_sdram.h>
+void board_add_ram_info(int use_default)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ddr83xx_t *ddr = &immap->ddr;
+
+ printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
+ >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
+
+ if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
+ puts(", 32-bit");
+ else
+ puts(", 64-bit");
+
+ if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+ puts(", ECC on)");
+ else
+ puts(", ECC off)");
+
+#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
+ puts("\nSDRAM: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+#endif
+}
+
#ifdef CONFIG_SPD_EEPROM
DECLARE_GLOBAL_DATA_PTR;
@@ -109,7 +133,7 @@ long int spd_sdram()
unsigned int n_ranks;
unsigned int odt_rd_cfg, odt_wr_cfg;
unsigned char twr_clk, twtr_clk;
- unsigned char sdram_type;
+ unsigned int sdram_type;
unsigned int memsize;
unsigned int law_size;
unsigned char caslat, caslat_ctrl;
@@ -137,7 +161,7 @@ long int spd_sdram()
#endif
/* Check the memory type */
if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
- printf("DDR: Module mem type is %02X\n", spd.mem_type);
+ debug("DDR: Module mem type is %02X\n", spd.mem_type);
return 0;
}
@@ -578,17 +602,17 @@ long int spd_sdram()
burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
else
burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
- printf("\n DDR DIMM: data bus width is 32 bit");
+ debug("\n DDR DIMM: data bus width is 32 bit");
} else {
burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
- printf("\n DDR DIMM: data bus width is 64 bit");
+ debug("\n DDR DIMM: data bus width is 64 bit");
}
/* Is this an ECC DDR chip? */
if (spd.config == 0x02)
- printf(" with ECC\n");
+ debug(" with ECC\n");
else
- printf(" without ECC\n");
+ debug(" without ECC\n");
/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
Burst type is sequential
@@ -718,26 +742,26 @@ long int spd_sdram()
* sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
*/
if (spd.mem_type == SPD_MEMTYPE_DDR)
- sdram_type = 2;
+ sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
else
- sdram_type = 3;
+ sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
sdram_cfg = (0
- | (1 << 31) /* DDR enable */
- | (1 << 30) /* Self refresh */
- | (sdram_type << 24) /* SDRAM type */
+ | SDRAM_CFG_MEM_EN /* DDR enable */
+ | SDRAM_CFG_SREN /* Self refresh */
+ | sdram_type /* SDRAM type */
);
/* sdram_cfg[3] = RD_EN - registered DIMM enable */
if (spd.mod_attr & 0x02)
- sdram_cfg |= 0x10000000;
+ sdram_cfg |= SDRAM_CFG_RD_EN;
/* The DIMM is 32bit width */
if (spd.dataw_lsb == 0x20) {
if (spd.mem_type == SPD_MEMTYPE_DDR)
- sdram_cfg |= 0x000C0000;
+ sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
if (spd.mem_type == SPD_MEMTYPE_DDR2)
- sdram_cfg |= 0x00080000;
+ sdram_cfg |= SDRAM_CFG_32_BE;
}
ddrc_ecc_enable = 0;
@@ -758,7 +782,7 @@ long int spd_sdram()
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
- printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
+ debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
#if defined(CONFIG_DDR_2T_TIMING)
/*
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index e2ec0bc220026a125b93807ec367826ea6870b81..db79ce28f312ece5bc0f79c43ca7a5f4151774e2 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -113,12 +113,12 @@
/* 0x03200064 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
| SDRAM_CFG_DBW_32 )
#else
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
#endif
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 829dbf93878109934df3a81dfe9ea3073b79d2af..4d32c6a3764ac7a17d0d1b14140cb04b58af3c88 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -705,8 +705,9 @@
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
-#define SDRAM_CFG_SDRAM_TYPE 0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_32_BE 0x00080000