diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c
index d69b91517219c65e9d2502bb02b6cf84aa5fe04b..06ec60e2a75901a97971ff306f8a5e274a2d6af6 100644
--- a/board/spc1920/spc1920.c
+++ b/board/spc1920/spc1920.c
@@ -175,6 +175,11 @@ long int initdram (int board_type)
 	/* initalize the DSP Host Port Interface */
 	hpi_init();
 
+	/* PLD Setup */
+	memctl->memc_or4 = CFG_OR4_PRELIM;
+	memctl->memc_br4 = CFG_BR4_PRELIM;
+	udelay(1000);
+
 	/* PLD Setup */
 	memctl->memc_or5 = CFG_OR5_PRELIM;
 	memctl->memc_br5 = CFG_BR5_PRELIM;
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 8f5eace69257c25d53c9fc978cb78f748403cb0e..0b07a45d67414a35d4edd9dc0391a66a4f6e2910 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -391,11 +391,24 @@
 #define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
 #endif /* CONFIG_SPC1920_HPI_TEST */
 
+/*
+ * Ramtron FM18L08 FRAM 32KB on CS4
+ */
+#define CFG_SPC1920_FRAM_BASE	0x80100000
+#define CFG_PRELIM_OR4_AM	0xffff8000
+#define CFG_OR4_PRELIM		(CFG_PRELIM_OR4_AM | \
+					OR_ACS_DIV2 | \
+					OR_BI | \
+					OR_SCY_4_CLK | \
+					OR_TRLX)
+
+#define CFG_BR4_PRELIM ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
 /*
  * PLD CS5
  */
 #define CFG_SPC1920_PLD_BASE	0x80000000
-#define CFG_PRELIM_OR5_AM	0xfff00000
+#define CFG_PRELIM_OR5_AM	0xffff8000
 
 #define CFG_OR5_PRELIM		(CFG_PRELIM_OR5_AM | \
 					OR_CSNT_SAM | \