From 54fd6c93c28a0a45352fff5dd92673401ff563f2 Mon Sep 17 00:00:00 2001 From: Stefan Roese <sr@denx.de> Date: Tue, 13 Nov 2007 08:18:20 +0100 Subject: [PATCH] ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching Signed-off-by: Stefan Roese <sr@denx.de> --- board/lwmon5/lwmon5.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 77f998971a..9b24a7e55e 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -96,6 +96,23 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_FLASH_WP, 1); + /* + * Reset PHY's: + * The PHY's need a 2nd reset pulse, since the MDIO address is latched + * upon reset, and with the first reset upon powerup, the addresses are + * not latched reliable, since the IRQ line is multiplexed with an + * MDIO address. A 2nd reset at this time will make sure, that the + * correct address is latched. + */ + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 0); + gpio_write_bit(CFG_GPIO_PHY1_RST, 0); + udelay(1000); + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + return 0; } @@ -230,15 +247,6 @@ int misc_init_r(void) /* Write lime controller memory parameters */ out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); - /* - * Reset PHY's - */ - gpio_write_bit(CFG_GPIO_PHY0_RST, 0); - gpio_write_bit(CFG_GPIO_PHY1_RST, 0); - udelay(100); - gpio_write_bit(CFG_GPIO_PHY0_RST, 1); - gpio_write_bit(CFG_GPIO_PHY1_RST, 1); - /* * Init display controller */ -- GitLab