diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 02d069c9ec605359e09273073de01cd00497e6a4..3824aade89d30b91b1d2daf9491bfa0776d882dc 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -267,6 +267,9 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	tmrd_mclk = 2;
 #endif
 
+	if (popts->trwt_override)
+		trwt_mclk = popts->trwt;
+
 	ddr->timing_cfg_0 = (0
 		| ((trwt_mclk & 0x3) << 30)	/* RWT */
 		| ((twrt_mclk & 0x3) << 28)	/* WRT */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 1778cc56b6019a26ecbcee1d5d17ab3b8b056ff4..bc063ea892ae0447f7adf8e33bfaaf731dbc9f1b 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -271,6 +271,9 @@ typedef struct memctl_options_s {
 	unsigned int rcw_2;
 	/* control register 1 */
 	unsigned int ddr_cdr1;
+
+	unsigned int trwt_override;
+	unsigned int trwt;			/* read-to-write turnaround */
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);