diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index a28082e56e616e28e3adce01a3011a5622a8304e..08d31e12e4c872e3ff3c37042287d36eac6c9605 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -311,9 +311,17 @@
  */
 #define LCRR_CLKDIV			0x0000001F
 #define LCRR_CLKDIV_SHIFT		0
+#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
+    defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
+    defined(CONFIG_MPC8560)
 #define LCRR_CLKDIV_2			0x00000002
 #define LCRR_CLKDIV_4			0x00000004
 #define LCRR_CLKDIV_8			0x00000008
+#else
+#define LCRR_CLKDIV_4			0x00000002
+#define LCRR_CLKDIV_8			0x00000004
+#define LCRR_CLKDIV_16			0x00000008
+#endif
 
 /* LTEDR - Transfer Error Check Disable Register
  */
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 242466ae12048dce561b1fa480a25f442ee71c17..30642cdfef4a75eb7aa3be542c19f30885a31fd6 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
  */
 
-#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_2 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_4 | LCRR_EADC_3)
 
 /*
  * NAND flash configuration
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index deda20843afb5c79291b4e2e0e75d4288590eed6..d79231b8b8b306a283ebf65324e2eb1bcae75d89 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -103,7 +103,7 @@
  * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
  */
 
-#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
 
 /*
  * NAND flash configuration
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 3c58ebe39b2871640c1fb512ec49d2d7d55386cc..65e1afddc6930109f638184ebce13040e9c2bd12 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
  */
 
-#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
 
 /*
  * NAND flash configuration