diff --git a/MAINTAINERS b/MAINTAINERS
index 9734b1d0958954b896b73d849b16bf66276ed547..48db504dad42c4c65640e1919704fba9325a027b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -36,6 +36,7 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 	mecp5200	MPC5200
 	pf5200		MPC5200
 
+	caddy2		MPC8349
 	vme8349		MPC8349
 
 	CPCI750		PPC750FX/GX
diff --git a/MAKEALL b/MAKEALL
index 1b78778a434386d48d353b72808ba9c6f356097d..a6d0f20f46cfcfc12508e498df55ef364a6ee70f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -358,6 +358,7 @@ LIST_8260="		\
 #########################################################################
 
 LIST_83xx="		\
+	caddy2		\
 	kmeter1		\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
diff --git a/Makefile b/Makefile
index 7dca112c60bcc34baa2182b27eaaa4ea17ad26fc..1abe64aa5953c2f4fd42820799004d53c5aafdf5 100644
--- a/Makefile
+++ b/Makefile
@@ -2400,8 +2400,9 @@ SIMPC8313_SP_config: unconfig
 TQM834x_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
 
+caddy2_config \
 vme8349_config:		unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
+	@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
 
 #########################################################################
 ## MPC85xx Systems
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index e3bc15112dc057979dbf94552420336f415d2dbe..b0ebad72b2f24399c9f0f82a7583665b3b9a08aa 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -38,63 +38,13 @@
 #endif
 #include <asm/io.h>
 #include <asm/mmu.h>
+#include <spd.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <netdev.h>
 
 void ddr_enable_ecc(unsigned int dram_size);
 
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1);
-	     ddr_size = ddr_size>>1, ddr_size_log2++) {
-		if (ddr_size & 1)
-			return -1;
-	}
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar  = LAWAR_EN | ((ddr_size_log2 - 1) &
-						LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE == 512)
-	im->ddr.csbnds[0].csbnds = 0x0000001f;
-#else
-#warning Currently any DDR size other than 512MiB is not supported
-#endif
-	im->ddr.cs_config[0]     = CONFIG_SYS_DDR_CONFIG | 0x00330000;
-
-	/* currently we use only one CS, so disable the other banks */
-	im->ddr.csbnds[1].csbnds = 0x00000000;
-	im->ddr.csbnds[2].csbnds = 0x00000000;
-	im->ddr.csbnds[3].csbnds = 0x00000000;
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[2] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	sync();
-	udelay(200);
-
-	/* enable DDR controller */
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
-	return msize;
-}
-
 phys_size_t initdram(int board_type)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
@@ -103,10 +53,10 @@ phys_size_t initdram(int board_type)
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
-	/* DDR SDRAM - Main SODIMM */
+	/* DDR SDRAM - Main memory */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
-	msize = fixed_sdram();
+	msize = spd_sdram();
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/*
@@ -124,17 +74,148 @@ phys_size_t initdram(int board_type)
 
 int checkboard(void)
 {
-	puts("Board: esd VME8349\n");
+#ifdef VME_CADDY2
+	puts("Board: esd VME-CADDY/2\n");
+#else
+	puts("Board: esd VME-CPU/8349\n");
+#endif
 
 	return 0;
 }
 
+#ifdef VME_CADDY2
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
+
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
 }
 #endif
+
+int misc_init_r()
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
+
+	return 0;
+}
+
+/*
+ * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
+ * and VME-CADDY/2) have different SDRAM configurations.
+ */
+#ifdef VME_CADDY2
+#define SMALL_RAM	0xff
+#define LARGE_RAM	0x00
+#else
+#define SMALL_RAM	0x00
+#define LARGE_RAM	0xff
+#endif
+
+#define SPD_VAL(a, b)	(((a) & SMALL_RAM) | ((b) & LARGE_RAM))
+
+static spd_eeprom_t default_spd_eeprom = {
+	SPD_VAL(0x80, 0x80),	/* 00 use 128 Bytes */
+	SPD_VAL(0x07, 0x07),	/* 01 use 128 Bytes */
+	SPD_MEMTYPE_DDR2,	/* 02 type is DDR2 */
+	SPD_VAL(0x0d, 0x0d),	/* 03 rows: 13 */
+	SPD_VAL(0x09, 0x0a),	/* 04 cols:  9 / 10 */
+	SPD_VAL(0x00, 0x00),	/* 05 */
+	SPD_VAL(0x40, 0x40),	/* 06 */
+	SPD_VAL(0x00, 0x00),	/* 07 */
+	SPD_VAL(0x05, 0x05),	/* 08 */
+	SPD_VAL(0x30, 0x30),	/* 09 */
+	SPD_VAL(0x45, 0x45),	/* 10 */
+	SPD_VAL(0x02, 0x02),	/* 11 ecc used */
+	SPD_VAL(0x82, 0x82),	/* 12 */
+	SPD_VAL(0x10, 0x10),	/* 13 */
+	SPD_VAL(0x08, 0x08),	/* 14 */
+	SPD_VAL(0x00, 0x00),	/* 15 */
+	SPD_VAL(0x0c, 0x0c),	/* 16 */
+	SPD_VAL(0x04, 0x08),	/* 17 banks: 4 / 8 */
+	SPD_VAL(0x38, 0x38),	/* 18 */
+	SPD_VAL(0x00, 0x00),	/* 19 */
+	SPD_VAL(0x02, 0x02),	/* 20 */
+	SPD_VAL(0x00, 0x00),	/* 21 */
+	SPD_VAL(0x03, 0x03),	/* 22 */
+	SPD_VAL(0x3d, 0x3d),	/* 23 */
+	SPD_VAL(0x45, 0x45),	/* 24 */
+	SPD_VAL(0x50, 0x50),	/* 25 */
+	SPD_VAL(0x45, 0x45),	/* 26 */
+	SPD_VAL(0x3c, 0x3c),	/* 27 */
+	SPD_VAL(0x28, 0x28),	/* 28 */
+	SPD_VAL(0x3c, 0x3c),	/* 29 */
+	SPD_VAL(0x2d, 0x2d),	/* 30 */
+	SPD_VAL(0x20, 0x80),	/* 31 */
+	SPD_VAL(0x20, 0x20),	/* 32 */
+	SPD_VAL(0x27, 0x27),	/* 33 */
+	SPD_VAL(0x10, 0x10),	/* 34 */
+	SPD_VAL(0x17, 0x17),	/* 35 */
+	SPD_VAL(0x3c, 0x3c),	/* 36 */
+	SPD_VAL(0x1e, 0x1e),	/* 37 */
+	SPD_VAL(0x1e, 0x1e),	/* 38 */
+	SPD_VAL(0x00, 0x00),	/* 39 */
+	SPD_VAL(0x00, 0x06),	/* 40 */
+	SPD_VAL(0x37, 0x37),	/* 41 */
+	SPD_VAL(0x4b, 0x7f),	/* 42 */
+	SPD_VAL(0x80, 0x80),	/* 43 */
+	SPD_VAL(0x18, 0x18),	/* 44 */
+	SPD_VAL(0x22, 0x22),	/* 45 */
+	SPD_VAL(0x00, 0x00),	/* 46 */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	SPD_VAL(0x10, 0x10),	/* 62 */
+	SPD_VAL(0x7e, 0x1d),	/* 63 */
+	{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
+	SPD_VAL(0x00, 0x00),	/* 72 */
+#ifdef VME_CADDY2
+	{ "vme-caddy/2 ram   " }
+#else
+	{ "vme-cpu/2 ram     " }
+#endif
+};
+
+int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int old_bus = I2C_GET_BUS();
+	unsigned int l, sum;
+	int valid = 0;
+
+	I2C_SET_BUS(0);
+
+	if (i2c_read(chip, addr, alen, buffer, len) == 0)
+		if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
+			sum = 0;
+			for (l = 0; l < 63; l++)
+				sum = (sum + buffer[l]) & 0xff;
+			if (sum == buffer[63])
+				valid = 1;
+			else
+				printf("Invalid checksum in EEPROM %02x %02x\n",
+				       sum, buffer[63]);
+		}
+
+	if (valid == 0) {
+		memcpy(buffer, (void *)&default_spd_eeprom, len);
+		sum = 0;
+		for (l = 0; l < 63; l++)
+			sum = (sum + buffer[l]) & 0xff;
+		if (sum != buffer[63])
+			printf("Invalid checksum in FLASH %02x %02x\n",
+			       sum, buffer[63]);
+		buffer[63] = sum;
+	}
+
+	I2C_SET_BUS(old_bus);
+
+	return 0;
+}
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index f9db73b2dcdf3fbd38d08fcfff176aa229ed449d..dbc15b297f9131f123a6068901db58cc26aaa807 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -34,6 +34,13 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_MK_caddy2
+#define VME_CADDY2
+#endif
+
 /*
  * High Level Configuration Options
  */
@@ -43,6 +50,8 @@
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_VME8349		1	/* ESD VME8349 board specific */
 
+#define CONFIG_MISC_INIT_R
+
 #define CONFIG_PCI
 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
@@ -75,7 +84,9 @@
  */
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
 #define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
-#undef CONFIG_SPD_EEPROM		/* dont use SPD EEPROM for DDR setup*/
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_SYS_READ_SPD		vme8349_read_spd
 #define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */
 
 /*
@@ -96,54 +107,40 @@
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE		512	/* MB */
-
-#if (CONFIG_SYS_DDR_SIZE == 512)
-#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
-					 CSCONFIG_COL_BIT_10 | \
-					 CSCONFIG_BANK_BIT_3)
-#endif
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_TIMING_0	        0x00220802
-#define CONFIG_SYS_DDR_TIMING_1	        0x39377322
-#define CONFIG_SYS_DDR_TIMING_2	        0x2f9848ca	/* P9-45, tuning? */
-#define CONFIG_SYS_DDR_TIMING_3	        0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuf,no DYN_PWR */
-#define CONFIG_SYS_DDR_MODE		0x07940242
-#define CONFIG_SYS_DDR_MODE2		0x00000000
-/* autocharge,no open page */
-#define CONFIG_SYS_DDR_INTERVAL	        0x04060100
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x63000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x04061000
+#define CONFIG_SYS_DDRCDR		0x80080001
 
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER			        /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE           128		/* flash size in MB */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+#ifdef VME_CADDY2
+#define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
+					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
+					 BR_V)			/* valid */
 
+#define CONFIG_SYS_OR0_PRELIM		0xffc06ff7	/*   4 MB flash size */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000015	/*   4 MB window size */
+#else
+#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		128		/* flash size in MB */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
 					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
 					 BR_V)			/* valid */
 
-#define CONFIG_SYS_OR0_PRELIM		0xF8006FF7	/* 128 MB flash size */
+#define CONFIG_SYS_OR0_PRELIM		0xf8006ff7	/* 128 MB flash size */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001A	/* 128 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001a	/* 128 MB window size */
+#endif
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
 #define CONFIG_SYS_BR1_PRELIM		(0xf0000000 | 0x00001801)
-#define CONFIG_SYS_OR1_PRELIM		(0xffff8000 | 0x00000200)
+#define CONFIG_SYS_OR1_PRELIM		(0xfffc0008 | 0x00000200)
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	0xf0000000
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(0x80000000 | 0x0000000e)
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(0x80000000 | 0x00000011)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/
@@ -157,7 +154,7 @@
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
-#undef  CONFIG_SYS_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
@@ -174,11 +171,10 @@
 
 /*
  * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
+ *    LCRR:  no DLL bypass, Clock divider is 4
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
@@ -268,10 +264,10 @@
 #undef PCI_ONE_PCI1
 #endif
 
-#define CONFIG_PCI_PNP			/* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
+#ifndef VME_CADDY2
 #define CONFIG_NET_MULTI
+#endif
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -282,19 +278,26 @@
 	#define PCI_IDSEL_NUMBER	0xFIXME
 #endif
 
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
 #endif	/* CONFIG_PCI */
 
 /*
  * TSEC configuration
  */
+#ifdef VME_CADDY2
+#define CONFIG_E1000
+#else
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+#endif
 
 #if defined(CONFIG_TSEC_ENET)
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI
 #endif
 
-#define CONFIG_GMII		       /* MII PHY management */
+#define CONFIG_GMII			/* MII PHY management */
 #define CONFIG_TSEC1
 #define CONFIG_TSEC1_NAME	"TSEC0"
 #define CONFIG_TSEC2
@@ -312,6 +315,12 @@
 
 #endif	/* CONFIG_TSEC_ENET */
 
+#if defined(CONFIG_E1000)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+#endif
+
 /*
  * Environment
  */
@@ -560,7 +569,7 @@
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* boot command will set bootargs */
 
-#define CONFIG_BAUDRATE	 115200
+#define CONFIG_BAUDRATE	 9600
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
@@ -605,4 +614,9 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+		     unsigned char *buffer, int len);
+#endif
+
 #endif	/* __CONFIG_H */