diff --git a/README b/README
index 5cbe7c1e80daabeee8c43247db7041b999919025..46e6a33bc122da646e435e3ebd9bc1047468ab28 100644
--- a/README
+++ b/README
@@ -1929,6 +1929,27 @@ Configuration Settings:
 		Scratch address used by the alternate memory test
 		You only need to set this if address zero isn't writeable
 
+- CFG_MEM_TOP_HIDE (PPC only):
+		If CFG_MEM_TOP_HIDE is defined in the board config header,
+		this specified memory area will get subtracted from the top
+		(end) of ram and won't get "touched" at all by U-Boot. By
+		fixing up gd->ram_size the Linux kernel should gets passed
+		the now "corrected" memory size and won't touch it either.
+		This should work for arch/ppc and arch/powerpc. Only Linux
+		board ports in arch/powerpc with bootwrapper support, that
+		recalculate the memory size from the SDRAM controller setup
+		will have to get fixed.
+
+		This option can be used as a workaround for the 440EPx/GRx
+		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
+		be touched.
+
+		WARNING: Please make sure that this value is a multiple of
+		the Linux page size (normally 4k). If this is not the case,
+		then the end address of the Linux memory will be located at a
+		non page size aligned address and this could cause major
+		problems.
+
 - CFG_TFTP_LOADADDR:
 		Default load address for network file downloads
 
diff --git a/include/configs/korat.h b/include/configs/korat.h
index dcec9b039d865b3f6e3276e7b613327547c1b2a8..de672ea844fe7c6be6fca76f9b8a9f90dfdb8b0d 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -144,6 +144,8 @@
 #define SPD_EEPROM_ADDRESS	{0x50}
 #define CONFIG_PROG_SDRAM_TLB
 #define CFG_DRAM_TEST
+#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
 
 /*
  * I2C
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index ced7ba6f05cf3bf05e3fb09d09685811ba562068..3056cb0b4496aab6e57bcfa0a0829e318161e283 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -86,6 +86,8 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 #define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
 						/* unused GPT0 COMP reg	*/
+#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
 
 /* Additional registers for watchdog timer post test */
 
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index dfa8779bccc31c8f7118cb73c1dc55e4c2177ddd..555316ff63811598d64e6f365cd8c7330fd564d9 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -221,6 +221,8 @@
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #endif
+#define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
 
 /*
  * I2C
@@ -275,7 +277,7 @@
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
 	"flash_nfs=run nfsargs addip addtty addmisc;"			\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty addmisc;"			\
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 30383027c78d33d310c9468340ec635d7c4aed4a..5e6e1e6a31b581fd2d204d5b2847c5030c8c87ee 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -428,6 +428,7 @@ void board_init_f (ulong bootflag)
 	 * relocate the code and continue running from DRAM.
 	 *
 	 * Reserve memory at end of RAM for (top down in that order):
+	 *  - area that won't get touched by U-Boot and Linux (optional)
 	 *  - kernel log buffer
 	 *  - protected RAM
 	 *  - LCD framebuffer
@@ -436,6 +437,18 @@ void board_init_f (ulong bootflag)
 	 */
 	len = (ulong)&_end - CFG_MONITOR_BASE;
 
+	/*
+	 * Subtract specified amount of memory to hide so that it won't
+	 * get "touched" at all by U-Boot. By fixing up gd->ram_size
+	 * the Linux kernel should now get passed the now "corrected"
+	 * memory size and won't touch it either. This should work
+	 * for arch/ppc and arch/powerpc. Only Linux board ports in
+	 * arch/powerpc with bootwrapper support, that recalculate the
+	 * memory size from the SDRAM controller setup will have to
+	 * get fixed.
+	 */
+	gd->ram_size -= CFG_MEM_TOP_HIDE;
+
 #ifndef CONFIG_MAX_MEM_MAPPED
 #define CONFIG_MAX_MEM_MAPPED (256 << 20)
 #endif