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    ARM: Introduce erratum workaround for 798870 · c616a0df
    Nishanth Menon authored
    
    
    Add workaround for Cortex-A15 ARM erratum 798870 which says
    "If back-to-back speculative cache line fills (fill A and fill B) are
    issued from the L1 data cache of a CPU to the L2 cache, the second
    request (fill B) is then cancelled, and the second request would have
    detected a hazard against a recent write or eviction (write B) to the
    same cache line as fill B then the L2 logic might deadlock."
    
    Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
    will be widely different.
    
    Every SoC has slightly different manner of setting up access to L2ACLR
    and similar registers since the Secure Monitor handling of Secure
    Monitor Call(smc) is diverse. Hence an weak function is introduced
    which may be overriden to implement SoC specific accessor implementation.
    
    Based on ARM errata Document revision 18.0 (22 Nov 2013)
    
    Signed-off-by: default avatarNishanth Menon <nm@ti.com>
    Tested-by: default avatarMatt Porter <mporter@konsulko.com>
    Reviewed-by: default avatarTom Rini <trini@konsulko.com>
    c616a0df