1. 07 Jul, 2017 1 commit
  2. 31 May, 2017 1 commit
    • Tobias Diedrich's avatar
      flash: Add support for Atheros (ath79) SPI interface · 6b9d19d3
      Tobias Diedrich authored
      Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558
      Extended and revised version of my original patch submitted by Dmytro
      here: http://openocd.zylin.com/#/c/3390
      This driver is using pure SPI mode, so the flash base address is not
      used except some flash commands (e.g. "flash program") need it to
      distinguish the banks.
      Example config with all 3 chip selects:
      flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
      flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
      flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
      Example usage:
      > flash probe flash0
      Found flash device 'win w25q128fv' (ID 0x001840ef)
      flash 'ath79' found at 0x00000000
      > flash probe flash1
      No SPI flash found
      > flash probe flash2
      No SPI flash found
      > flash banks
      > flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000
      reading 4096 bytes from flash @0x00000000
      wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset
      0x00000000 in 28.688066s (0.139 KiB/s)
      Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8
      Signed-off-by: default avatarTobias Diedrich <ranma+openocd@tdiedrich.de>
      Reviewed-on: http://openocd.zylin.com/3612
      Tested-by: jenkins
      Reviewed-by: default avatarDmytro <dioptimizer@hotmail.com>
      Reviewed-by: default avatarPaul Fertser <fercerpav@gmail.com>
  3. 08 May, 2017 4 commits
  4. 24 May, 2016 2 commits
  5. 09 May, 2014 2 commits
    • Salvador Arroyo's avatar
      mips32: new code for pracc exec · 6cadbadb
      Salvador Arroyo authored
      This is only the basic code proposed for mips32_pracc_exec() function.
      It checks every pracc address against the expected address when
      reading (instruction fetch).
      The code expects to start at PRACC_TEXT and any subsequent read address
      is obtained by adding 4 to the previous one.
      After shifting out all the instructions the code executes a final check.
      It checks now for the first pass trough PRACC_TEXT and shift out
      only NOP instructions.
      A mips core does not need an additional NOP and after the first check
      it exits if there is no store access pending.
      After shifting out one NOP the core must be reading at pracc text or the
      code exits with error.
      The code continues shifting out NOPs until all store accesses have
      been performed.
      After shifting out 10 NOPs it exits with error.
      No assumption is made about the number of store instruction shifted out or
      the ordering of the store accesses. It only checks that the number of
      store accesses is the same as the number of store instructions at dmseg
      after execution.
      mips32_pracc_read_ctrl_addr() and mips32_pracc_finish() are added to
      simpify a bit the code. Fields pa_ctrl and pa_addr are added
      in ejtag_info for storing values of pracc control and address.
      Change-Id: If6322d5c8cbeadcd4acd3972c0f72c8490f53c34
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1827
      Tested-by: jenkins
      Reviewed-by: default avatarFreddie Chopin <freddie.chopin@gmail.com>
    • Salvador Arroyo's avatar
      mips32: cleanups in legacy pracc code · fcd7b90d
      Salvador Arroyo authored
      This is the first patch intended to make a more precise pracc check
      when running in legacy mode (code executed by mips32_pracc_exec()).
      It only makes some cleanups, mostly due to unnecessary code.
      With the last cache optimizations for processor access (pa for short)
      all the pracc functions generate the code following some rules that
      make pa more easily to check:
      	There are no load instructions from dmseg. All the read pas are
      	instruction fetches. PARAM_IN related stuff is not needed.
      	Registers are restored either from COP0 DeSave or from ejtag
      	info fields. PRACC_STACK related stuff is not needed any more.
      	The code starts execution at PRACC_TEXT and there are no branch or jump
      	instruction in the code, apart from the last jump to PRACC_TEXT.
      	The fetch address is ever known.
      	For every store instruction to dmseg the function code sets
      	the address of the write/store pa.
      	The address of every store pa is known.
      Current code ends execution when reading a second pass through PRACC_TEXT.
      This approach has same inconveniences:
      	If the code starts in the delay slot of a jump it makes a jump
      	to PRACC_TEXT after executing the first instruction. A second pass
      	through PRACC_TEXt is read and the function exits without any warning.
      	This seems to occur sometimes when a 24kc core is halted in the delay
      	slot of a branch.
      	If a debug mode exception is triggered during the execution of a
      	function the core restarts execution at PRACC_TEXT. Again the function
      	exits without any warning.
      	If for whatever reason the core starts fetching  at an unexpected
      	address the code now sends a jump instruction to PRACC_TEXT, but due
      	to the delay slot the core continues fetching at whatever address + 4
      	and a second jump instruction will be send for execution. The result
      	of a jump instruction in the delay slot of another jump is
      	UNPREDICTABLE. It may work as expected (ar7241), or let the core in
      	the delay slot of a jump to PRACC_TEXT for example. This means the
      	function called next may also fail (pic32mx).
      Change-Id: I9516a5146ee9c8c694d741331edc7daec9bde4e3
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1825
      Tested-by: jenkins
      Reviewed-by: default avatarFreddie Chopin <freddie.chopin@gmail.com>
  6. 31 Oct, 2013 1 commit
  7. 05 Jun, 2013 1 commit
  8. 20 Apr, 2013 2 commits
    • Salvador Arroyo's avatar
      mips: m4k alternate pracc code. Patch 3 · d5e56462
      Salvador Arroyo authored
      Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified.
      mips32_cp0_read() is very similar to mips32_read_u32() with one store access.
      mips32_pracc_read_regs() is the only function that can not be executed from only one queue.
      Now this function is modified to use reg8, it saves all the registers but does not restore reg8.
      To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in
      mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and
      restore it from ejtag info instead of using DeSave for save/restore.
      Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1195
      Tested-by: jenkins
      Reviewed-by: default avatarFreddie Chopin <freddie.chopin@gmail.com>
    • Salvador Arroyo's avatar
      mips: m4k alternate pracc code. Patch 1 · 109f37c1
      Salvador Arroyo authored
      This patch and the following patches define another way of doing processor access without the need to read back
      the pracc address as needed in current pracc code.
      Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
      and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
      Most of the processor accesses are fetch and some are store accesses.
      After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
      The pracc address for a store depends only on the store instruction given before.
      m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
      will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
      For reference: MD00249 mips32 m4k manual.
      A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
      lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
      current code or by the new one to generate the sequence of pracc accesses.
      For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
      This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
      The pracc bit is not checked before execution, is checked after the queue has been executed.
      Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
      with core clock at 4Mhz works  up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
      between scans is added by calling jtag_add_cloks().
      A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
      A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
      current code is executed, if lower, new code is executed.
      Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
      Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65
      Signed-off-by: default avatarSalvador Arroyo <sarroyofdez@yahoo.es>
      Reviewed-on: http://openocd.zylin.com/1193
      Tested-by: jenkins
      Reviewed-by: default avatarFreddie Chopin <freddie.chopin@gmail.com>
  9. 16 Nov, 2012 1 commit
  10. 06 Feb, 2012 1 commit
  11. 09 Aug, 2011 1 commit
    • Drasko DRASKOVIC's avatar
      mips32: Added CP0 coprocessor R/W routines · 1be71634
      Drasko DRASKOVIC authored
      This patch adds MIPS32 CP0 coprocessor R/W routines,
      as well as adequate commands to use these routines via
      telnet interface.
      Now is becomes possible to affect CP0 internal registers
      and configure CPU directly from OpenOCD.
  12. 29 Dec, 2010 1 commit
    • Andrew MacIsaac's avatar
      Compilation Warnings on OS X 10.5 · 50e79d60
      Andrew MacIsaac authored
      I received a number of "-Wshadow" related warnings (treated as errors) while
      trying to build on OS X Leopard.  In addition, there were two miscellaneous
      other warnings in the flash drivers.  Attached are two patches which correct
      these issues and the commit messages to accompany them.
      My system has the following configuration (taken from uname -a):
      Darwin 9.8.0 Darwin Kernel Version 9.8.0: Wed Jul 15 16:55:01 PDT 2009;
      root:xnu-1228.15.4~1/RELEASE_I386 i386
      === Werror_patch.txt Commit Message ===
      compilation: fixes for -Wshadow warnings on OS X
      These changes fix -Wshadow compilation warnings on OS X 10.5.8
      Compiled with the following configure command:
      ../configure --prefix=/usr/local --enable-maintainer-mode --enable-jlink
      === flash_patch.txt Commit Message ===
      compilation: fixes for flash driver warnings on OS X
      These changes fix two compilation warnings on OS X 10.5.8:
      ../../../../src/flash/nor/at91sam3.c:2767: warning: redundant redeclaration
      of 'at91sam3_flash'
      ../../../../src/flash/nor/at91sam3.c:101: warning: previous declaration of
      'at91sam3_flash' was here
      ../../../../src/flash/nor/stmsmi.c:205: warning: format not a string literal
      and no format arguments
      Compiled with the following configure command:
      ../configure --prefix=/usr/local --enable-maintainer-mode --enable-jlink
  13. 10 Apr, 2010 1 commit
  14. 07 Jan, 2010 1 commit
  15. 05 Jan, 2010 2 commits
  16. 13 Dec, 2009 1 commit
  17. 03 Dec, 2009 1 commit
  18. 22 Nov, 2009 1 commit
  19. 13 Nov, 2009 1 commit
  20. 09 Nov, 2009 1 commit
  21. 23 Jun, 2009 2 commits
  22. 18 Jun, 2009 3 commits
  23. 21 Apr, 2009 1 commit
  24. 05 Jan, 2009 1 commit
  25. 13 Dec, 2008 1 commit
  26. 26 Jul, 2008 1 commit