mips32_pracc.h 5.11 KB
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/***************************************************************************
 *   Copyright (C) 2008 by Spencer Oliver                                  *
 *   spen@spen-soft.co.uk                                                  *
 *                                                                         *
 *   Copyright (C) 2008 by David T.L. Wong                                 *
 *                                                                         *
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 *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
 *   drasko.draskovic@gmail.com                                            *
 *                                                                         *
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 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
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 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
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 ***************************************************************************/
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#ifndef OPENOCD_TARGET_MIPS32_PRACC_H
#define OPENOCD_TARGET_MIPS32_PRACC_H
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#include <target/mips32.h>
#include <target/mips_ejtag.h>
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#define MIPS32_PRACC_FASTDATA_AREA		0xFF200000
#define MIPS32_PRACC_FASTDATA_SIZE		16
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#define MIPS32_PRACC_BASE_ADDR			0xFF200000
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#define MIPS32_PRACC_TEXT				0xFF200200
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#define MIPS32_PRACC_PARAM_OUT			0xFF202000
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#define PRACC_UPPER_BASE_ADDR			(MIPS32_PRACC_BASE_ADDR >> 16)
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#define PRACC_MAX_CODE				(MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_TEXT)
#define PRACC_MAX_INSTRUCTIONS			(PRACC_MAX_CODE / 4)
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#define PRACC_OUT_OFFSET			(MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)

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#define MIPS32_FASTDATA_HANDLER_SIZE	0x80
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#define UPPER16(uint32_t)				(uint32_t >> 16)
#define LOWER16(uint32_t)				(uint32_t & 0xFFFF)
#define NEG16(v)						(((~(v)) + 1) & 0xFFFF)
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#define SWAP16(v)				((LOWER16(v) << 16) | (UPPER16(v)))
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/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
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#define PRACC_BLOCK	128	/* 1 Kbyte */

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typedef struct {
	uint32_t instr;
	uint32_t addr;
} pa_list;

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struct pracc_queue_info {
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	struct mips_ejtag *ejtag_info;
	unsigned isa;
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	int retval;
	int code_count;
	int store_count;
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	int max_code;		/* max intstructions with currently allocated memory */
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	pa_list *pracc_list;	/* Code and store addresses at dmseg */
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};
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void pracc_queue_init(struct pracc_queue_info *ctx);
void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
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void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize);
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void pracc_queue_free(struct pracc_queue_info *ctx);
int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
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			    struct pracc_queue_info *ctx, uint32_t *buf, bool check_last);
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int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
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		uint32_t addr, int size, int count, void *buf);
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int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
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		uint32_t addr, int size, int count, const void *buf);
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int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
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		int write_t, uint32_t addr, int count, uint32_t *buf);
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int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx,
				uint32_t *param_out, bool check_last);
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/**
 * \b mips32_cp0_read
 *
 * Simulates mfc0 ASM instruction (Move From C0),
 * i.e. implements copro C0 Register read.
 *
 * @param[in] ejtag_info
 * @param[in] val Storage to hold read value
 * @param[in] cp0_reg Number of copro C0 register we want to read
 * @param[in] cp0_sel Select for the given C0 register
 *
 * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
 */
int mips32_cp0_read(struct mips_ejtag *ejtag_info,
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		uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
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/**
 * \b mips32_cp0_write
 *
 * Simulates mtc0 ASM instruction (Move To C0),
 * i.e. implements copro C0 Register read.
 *
 * @param[in] ejtag_info
 * @param[in] val Value to be written
 * @param[in] cp0_reg Number of copro C0 register we want to write to
 * @param[in] cp0_sel Select for the given C0 register
 *
 * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
 */
int mips32_cp0_write(struct mips_ejtag *ejtag_info,
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		uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
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static inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count)
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{
	if (ejtag_info->isa && ejtag_info->endianness)
		for (int i = 0; i != count; i++)
			buf[i] = SWAP16(buf[i]);
}

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#endif /* OPENOCD_TARGET_MIPS32_PRACC_H */