Commit 8389b419 authored by David Mondou's avatar David Mondou
Browse files

update drive strength on all rad dts files

parent 8b4b4f2a
......@@ -119,7 +119,7 @@
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x80000000 /* SPDIF OUT */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x80000000 /* BT GPIO */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x17059 /* BT RST N */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* ENET1 RST N */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x00001020 /* ENET1 RST N */
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x80000000 /* RST BTN */
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80000000 /* BT INT N */
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x80000000 /* ENET1 INT N */
......@@ -147,71 +147,71 @@
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x03029
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00000010
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00002008
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x00002008
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00001088
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00001088
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00001088
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00001088
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00001088
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00001088
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00001088
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40001008
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x40001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x40001820
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x00007091
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x00007091
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x00007091
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x00007091
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x00007091
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x00007091
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x00001020
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x00001020
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x00001020
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x00001020
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x00001020
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x00001020
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00001020
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00001020
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00001020
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00001020
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00001020
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b1
......@@ -228,7 +228,7 @@
pinctrl_uart6: uart6grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x00001020
MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
>;
......@@ -237,7 +237,7 @@
pinctrl_uart7: uart7grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x1b0b1
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x1b0b1
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00001020
MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x1b0b1
>;
......@@ -246,7 +246,7 @@
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b1
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b1
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00001020
MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x1b0b1
>;
......@@ -254,27 +254,27 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017060
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00001010
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017060
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017060
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017060
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017060
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000010A0
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000090A0
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000090A0
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000010A0
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000010A0
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000010A0
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000010A0
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000010A0
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000010A0
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000010A0
>;
};
......
......@@ -119,7 +119,7 @@
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x80000000 /* SPDIF OUT */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x80000000 /* BT GPIO */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x17059 /* BT RST N */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* ENET1 RST N */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x00001020 /* ENET1 RST N */
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x80000000 /* RST BTN */
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80000000 /* BT INT N */
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x80000000 /* ENET1 INT N */
......@@ -145,29 +145,29 @@
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x03029
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00000010
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00002008
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x00002008
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00001088
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00001088
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00001088
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00001088
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00001088
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00001088
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00001088
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40001008
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x40001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x40001820
>;
};
......@@ -185,43 +185,43 @@
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x00007091
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x00007091
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x00007091
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x00007091
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x00007091
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x00007091
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x00001020
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x00001020
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x00001020
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x00001020
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x00001020
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x00001020
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00001020
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00001020
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00001020
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00001020
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00001020
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b1
......@@ -238,7 +238,7 @@
pinctrl_uart6: uart6grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x00001020
MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
>;
......@@ -256,7 +256,7 @@
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b1
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b1
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00001020
MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x1b0b1
>;
......@@ -264,27 +264,27 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017060
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00001010
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017060
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017060
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017060
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017060
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000010A0
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000090A0
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000090A0
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000010A0
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000010A0
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000010A0
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000010A0
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000010A0
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000010A0
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000010A0
>;
};
......
......@@ -120,7 +120,7 @@
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x80000000 /* SPDIF OUT */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x80000000 /* BT GPIO */
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x17059 /* BT RST N */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* ENET1 RST N */
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x00001020 /* ENET1 RST N */
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x80000000 /* RST BTN */
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80000000 /* BT INT N */
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x80000000 /* ENET1 INT N */
......@@ -146,29 +146,29 @@
pinctrl_wifi: wifigrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x03029
MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00000010
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00002008
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x00002008
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00001088
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00001088
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00001088
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00001088
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00001088
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00001088
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00001088
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40001008
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x40001820
MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x40001820
>;
};
......@@ -186,43 +186,43 @@
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x00007091
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x00007091
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x00007091
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x00007091
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x00007091
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x00007091
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x00001020
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x00001020
MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x00001020
MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x00001020
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x00001020
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x00001020
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00001020
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00001020
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00001020
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00001020
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00001020
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x1b0b1
......@@ -239,7 +239,7 @@
pinctrl_uart6: uart6grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x00001020
MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
>;
......@@ -248,7 +248,7 @@
pinctrl_uart7: uart7grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x1b0b1
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x1b0b1
MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00001020
MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x1b0b1
>;
......@@ -257,7 +257,7 @@
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b1
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b1
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00001020
MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x1b0b1
MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x1b0b1
>;
......@@ -265,27 +265,27 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017060
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00001010
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017060
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017060
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017060
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017060
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000010A0
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000090A0
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000090A0
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000010A0
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000010A0
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000010A0
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000010A0
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000010A0
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000010A0
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000010A0
>;
};
......
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